CN106484575A - A kind of ARINC429 bus failure injected system - Google Patents
A kind of ARINC429 bus failure injected system Download PDFInfo
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- CN106484575A CN106484575A CN201610866476.2A CN201610866476A CN106484575A CN 106484575 A CN106484575 A CN 106484575A CN 201610866476 A CN201610866476 A CN 201610866476A CN 106484575 A CN106484575 A CN 106484575A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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Abstract
A kind of ARINC429 bus failure injected system that the present invention is provided, including：ADC, FPGA module, DAC and Ethernet interface, wherein, FPGA module, for receiving the direct fault location sequence information issued from host computer, direct fault location sequence information includes multiple failure strategy, and the execution time period of each failure strategy；Start timing when direct fault location sequence information is received, in the execution time period of each failure strategy, direct fault location is carried out to ARINC429 signal according to corresponding failure strategy, the signal for completing direct fault location is sent to ARINC429 bus to be measured by DAC.The good direct fault location sequence information of user configuring after host computer is issued to the system of the present invention, system is according to the execution time period of each failure strategy, automatically go in order to execute, do not need user excessive go execute operation, the automaticity of various faults item injection is improve, and efficiency is higher.
Description
Technical field
The present invention relates to Failure Injection Technique field, more specifically, more particularly to a kind of ARINC429 bus failure note
Enter system.
Background technology
Direct fault location refers to the fault model according to design in advance, the method for artificially introducing fault in suspect system,
Promote system errors and failure, by observing reliability of state response of the comparison system after breaking down to system
Evaluated.
At present, what ARINC429 bus failure injected is achieved in that, after a kind of injection of fault item is completed, needs user
This fault item injection of manual-lock, and manually boot the injection of another kind of fault item.A kind of injection of fault item is often carried out, is needed
User carry out manually operated twice, so when carrying out various faults item and injecting, less efficient, and automaticity is relatively low.
Content of the invention
In view of this, the present invention proposes a kind of ARINC429 bus failure injected system, is intended to solve existing direct fault location side
Method inefficiency, and the relatively low technical problem of automaticity.
In order to solve above-mentioned technical problem, it is proposed that scheme as follows：
A kind of ARINC429 bus failure injected system, including：ADC, FPGA module, DAC and Ethernet interface, wherein,
The ADC, for the conversion of the ARINC429 signal simulation amount to receiving to digital quantity, and sends to described
FPGA module；
The FPGA module, for being connected with host computer by the Ethernet interface, is received and issues from the host computer
Direct fault location sequence information, the direct fault location sequence information includes multiple failure strategy, and each described failure strategy
The execution time period；And for starting timing when the direct fault location sequence information is received, in each failure strategy
The execution time period, fault item injection is carried out to the ARINC429 signal for receiving according to corresponding failure strategy, will complete therefore
The ARINC429 signal of barrier item injection is sent to the DAC；
The DAC, carries out digital quantity to simulation for the ARINC429 signal to completing direct fault location described in receiving
The conversion of amount, and send to ARINC429 bus to be measured.
Preferably, the FPGA module includes：Direct fault location sequence control unit, data receipt unit, Trouble Match list
Unit, direct fault location unit data transmitting element, wherein,
The direct fault location sequence control unit, for receiving the direct fault location sequence information；Receiving the event
Start timing after barrier injection sequence information, in the execution start time of each failure strategy, corresponding failure strategy is sent out
The Trouble Match unit is delivered to, and the Trouble Match unit and the direct fault location list is respectively sent to by signal is enabled
Unit；In the finish time of each failure strategy, forbidden energy signal is respectively sent to the Trouble Match unit and the event
Barrier injection unit；
The data receipt unit, for receiving the ARINC429 signal of ADC transmission, and according to ARINC429 agreement
Changed, obtained ARINC429 message；
The Trouble Match unit, for being mated to the ARINC429 message according to corresponding failure strategy, obtains
To fault item to be injected；
The direct fault location unit, for carrying out the injection of the fault item to the ARINC429 message；
The data transmission unit, for entering the ARINC429 message for completing the injection of fault item according to ARINC429 agreement
Row conversion, obtains ARINC429 signal and sends to the DAC.
Preferably, the direct fault location unit includes：Physical layer direct fault location subelement, electrical layer direct fault location subelement
With protocol layer direct fault location subelement, wherein,
The physical layer direct fault location subelement, for the injection of physical layer fault item, the physical layer fault item includes
Short trouble, open circuit fault, series impedance fault and/or parallel impedance fault；
The electrical layer direct fault location subelement, for the injection of electrical layer fault item, the electrical layer fault item includes
Amplitude fault, slope fault, dutycycle fault, rate failure and/or noise failure；
The protocol layer direct fault location subelement, for the injection of protocol layer fault item, the protocol layer fault item includes
Fault is replaced in LABEL domain, and SDI domain is replaced fault, data field and replaces fault, the replacement of SSM domain fault, parity check bit fault, refers to
Positioning failure and/or frame length fault.
Preferably, the electrical layer direct fault location subelement adopts pipeline processing mode.
Preferably, each described failure strategy includes multiple matching conditions and corresponding with matching condition each described
Fault item, each described matching condition include its corresponding priority, the Trouble Match unit specifically for：
According to the priority of the matching condition, mated with the ARINC429 message successively, until the match is successful
Till, using corresponding for the matching condition that the match is successful fault item as fault item to be injected.
Preferably, the direct fault location sequence information also includes order based on outer triggering signal initiating sequence or not base
Order in outer triggering signal initiating sequence；
The system also includes：External signal triggers interface, for receiving outer triggering signal；
The FPGA module, is additionally operable to receive whether the direct fault location sequence information is opened based on the outer triggering signal
Dynamic order, and, if the direct fault location sequence information is started based on outer triggering signal, touch the outside is received
Start timing, and the execution time period in each failure strategy after signalling, according to corresponding failure strategy to receiving
ARINC429 signal carry out fault item injection, by complete fault item injection ARINC429 signal send to the DAC.
Preferably, the system also includes：
The first digital regulation resistance being connected in the ARINC429 bus to be measured, and be connected in parallel on described to be measured
The second digital regulation resistance in ARINC429 bus,
The physical layer direct fault location subelement, for realizing string by controlling the resistance value of first digital regulation resistance
Row impedance fault injects, and realizes short trouble injection or parallel impedance by controlling the resistance value of second digital regulation resistance
Direct fault location.
Compared with prior art, technical scheme has advantages below：
A kind of ARINC429 bus failure injected system that technique scheme is provided, including：ADC, FPGA module, DAC
And Ethernet interface, wherein, FPGA module, for receiving the direct fault location sequence information issued from host computer, direct fault location sequence
Column information includes multiple failure strategy, and the execution time period of each failure strategy；FPGA module, is additionally operable to receiving
Start timing during to the direct fault location sequence information, in the execution time period of each failure strategy, according to corresponding event
Barrier strategy carries out direct fault location to the ARINC429 signal for receiving, and will complete the ARINC429 signal of direct fault location by DAC
Send to ARINC429 bus to be measured.The good direct fault location sequence information of user configuring is simultaneously issued to the present invention's by host computer
After ARINC429 bus failure injected system, system goes to hold according to the execution time period of each failure strategy in order automatically
OK, it is not necessary to which what user was excessive goes operation is executed, the automaticity of various faults item injection is improve, and efficiency is higher.
Description of the drawings
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
Accompanying drawing to be used needed for technology description is had to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, acceptable
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is a kind of structural representation of ARINC429 bus failure injected system provided in an embodiment of the present invention；
Fig. 2 is the structural representation of FPGA module in Fig. 1 provided in an embodiment of the present invention；
Fig. 3 is a kind of schematic diagram of the method for Trouble Match provided in an embodiment of the present invention；
Fig. 4 is the structural representation of another kind ARINC429 bus failure injected system provided in an embodiment of the present invention；
Fig. 5 is a kind of schematic diagram of physical layer direct fault location provided in an embodiment of the present invention.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
Embodiments provide a kind of ARINC429 bus (US Airways electronic engineering committee Airlines
The Avionics data bus that Engineering Committee is proposed) fault injection system, Fig. 1 is referred to, shows the structure of the system
Schematic diagram, the system include：ADC (Analog to Digital Converter, analog-digital converter) 11, FPGA (Field
Programmable Gate Array, field programmable gate array) module 12, DAC (Digital to analog
Converter, digital to analog converter) 13 and Ethernet interface 14, wherein,
The ADC11, for the conversion of the ARINC429 signal simulation amount to receiving to digital quantity, and sends to institute
State FPGA module 13；
The FPGA module 13, for being connected with host computer by the Ethernet interface 14, is received from the host computer
The direct fault location sequence information for issuing, the direct fault location sequence information include multiple failure strategy, and each described fault
The execution time period of strategy；And for starting timing when the direct fault location sequence information is received, in each fault
The execution time period of strategy, fault item injection is carried out to the ARINC429 signal for receiving according to corresponding failure strategy, will be complete
The ARINC429 signal of fault item injection is become to send to the DAC13；
The DAC13, carries out digital quantity to mould for the ARINC429 signal to completing direct fault location described in receiving
The conversion of analog quantity is simultaneously sent to ARINC429 bus to be measured.
User arranges direct fault location sequence information by host computer, and for example, user setup Fisrt fault strategy is unconditional
Series impedance fault is executed, the execution time period of Fisrt fault strategy is 1min～20min；Second failure strategy be for satisfaction
LABEL is changed to the fault of 0x11 for the message injection of SDI=2, and the execution time period of the second failure strategy is 30min～40min；
3rd failure strategy executes short trouble for unconditional, and the execution time period of the 3rd failure strategy is 40min～60min.FPGA
Module 13 starts timing, unconditionally executes string in 1min～20min after the direct fault location sequence information that host computer is issued is connected to
Row impedance fault, injects for the message for meeting SDI=2 in 30min～40min and for LABEL to be changed to 0x11 fault,
40min～60min unconditionally executes short trouble, terminates in 60min.
ARINC429 bus failure injected system provided in an embodiment of the present invention, according to the execution time of each failure strategy
Section, goes automatically in order to execute, it is not necessary to which what user was excessive goes to execute operation, improves the automation of various faults item injection
Degree, and efficiency is higher.
A kind of FPGA module is embodiments provided, Fig. 2 is referred to, show that the structure of FPGA module in Fig. 1 is shown
It is intended to, the FPGA module includes：Direct fault location sequence control unit 121, data receipt unit 122, Trouble Match unit 123,
124 data transmitting element 125 of direct fault location unit, wherein,
The direct fault location sequence control unit 121, for receiving the direct fault location sequence information；Described receiving
Start timing after direct fault location sequence information, in the execution start time of each failure strategy, by corresponding failure strategy
Send to the Trouble Match unit 123, and the Trouble Match unit 123 and the fault is respectively sent to by signal is enabled
Injection unit 124；In the finish time of each failure strategy, forbidden energy signal is respectively sent to the Trouble Match unit
123 and the direct fault location unit 124；
The data receipt unit 122, for receiving the ARINC429 signal of ADC transmission, and according to ARINC429
Agreement is changed, and obtains ARINC429 message；
The Trouble Match unit 123, for being mated to the ARINC429 message according to corresponding failure strategy,
Obtain fault item to be injected；
The direct fault location unit 124, for carrying out the injection of the fault item to the ARINC429 message；The event
Barrier injection unit 124 includes：The event of physical layer direct fault location subelement 1241, electrical layer direct fault location subelement 1242 and protocol layer
Barrier injection subelement 1243, wherein, the physical layer direct fault location subelement 1241, for the injection of physical layer fault item, institute
Stating physical layer fault item includes short trouble, open circuit fault, series impedance fault and/or parallel impedance fault；The electrical layer
Direct fault location subelement 1242, for the injection of electrical layer fault item, the electrical layer fault item includes amplitude fault, slope event
Barrier, dutycycle fault, rate failure and/or noise failure；The protocol layer direct fault location subelement 1243, for protocol layer event
Barrier item injection, the protocol layer fault item include LABEL domain replace fault, SDI domain replace fault, data field replace fault,
Fault, parity check bit fault, specific bit fault and/or frame length fault are replaced in SSM domain.
The data transmission unit 125, for assisting the ARINC429 message for completing the injection of fault item according to ARINC429
View is changed, and is obtained ARINC429 signal and is sent to the DAC.
For example：Direct fault location sequence control unit 121 starts timing after direct fault location sequence information is received, first
When the execution start time of failure strategy is 1min, Fisrt fault strategy is sent to Trouble Match unit 123, and letter will be enabled
Number be respectively sent to Trouble Match unit 123 and direct fault location unit 124, Trouble Match unit 123 receive enable signal and
After Fisrt fault strategy, it is unconditional to obtain matching condition according to Fisrt fault strategy, and fault item is series impedance fault, because
This, no matter ARINC429 message includes any content, and the fault item to be injected of acquisition is series impedance fault, direct fault location
After unit 124 receives enable signal and fault item to be injected, series impedance direct fault location is carried out to ARINC429 message；?
When the execution finish time of Fisrt fault strategy is 20min, forbidden energy signal is sent by direct fault location sequence control unit 121 respectively
To Trouble Match unit 123 and direct fault location unit 124, the system stops Trouble Match and direct fault location.Other failure strategy
Implementation procedure similar with the implementation procedure of Fisrt fault strategy, repeat no more.By matching condition to specifying ARINC429 to report
Text carries out the injection of corresponding failure item and can strengthen actually used validity, accelerates the fault to ARINC429 bus to be measured fixed
Position.
The electrical layer direct fault location subelement adopts pipeline processing mode.In the process of electrical layer, the reality of process
Be data point one by one on border, after pipeline processing mode, a kind of fault can be first realized in first order flowing water
Item injection, then by the data after process to next stage flowing water, proceeds the injection of another kind of fault item, so in next stage
After what cascade, last output again, can execute the injection of various faults item simultaneously, and therefore, electrical layer direct fault location subelement is adopted
With pipeline processing mode, can be any combination of various faults item during the fault item injection for carrying out an electrical layer.
Fig. 3 illustrates a kind of method of Trouble Match, and the failure strategy of user setup can include multiple matching conditions, and
Fault item corresponding with each matching condition, each matching condition include its corresponding priority, it should be noted that each
Join the corresponding fault item of condition can include multiple, for example：The corresponding fault item of matching condition 1 is amplitude fault, slope fault
Fault is replaced with DATA.Matching condition and the corresponding fault item of matching condition are freely joined according to the focus of oneself by user
Put.
After Trouble Match unit 123 receives enable signal and failure strategy, according to the priority of the matching condition, according to
Secondary mated with the ARINC429 message, till the match is successful, by corresponding for the matching condition that the match is successful fault
Item is used as fault item to be injected.
Such as 1 highest priority of user setup matching condition, 2 priority of matching condition are taken second place, and matching condition N priority is most
Low, the ARINC429 message that Trouble Match unit 123 is received directly is corresponded to according to matching condition 1 if matching condition 1 is met
Fault item 1 carry out fault item injection, remaining matching condition is not judged.User can be clicked through according to the concern of oneself
The self-defined planning of row, improves flexibility, and Test coverage face is wider.
Another kind of ARINC429 bus failure injected system is embodiments provided, Fig. 4 is referred to, show that this is
The structural representation of system, the system include：The triggering of ADC11, FPGA module 12, DAC13, Ethernet interface 14 and external signal connects
Mouth 15, wherein,
The FPGA module 13, for being connected with host computer by the Ethernet interface 14, is received from the host computer
The direct fault location sequence information for issuing, and receive what whether the direct fault location sequence information was started based on outer triggering signal
Order；The direct fault location sequence information includes multiple failure strategy, and the execution time period of each failure strategy；And
If outer triggering signal startup is not based on for the direct fault location sequence information, receiving the direct fault location sequence
Start timing during information, in the execution time period of each failure strategy, according to corresponding failure strategy to receiving
ARINC429 signal carries out fault item injection, and the ARINC429 signal for completing the injection of fault item is sent to the DAC13；Also use
If being to be started based on outer triggering signal in the direct fault location sequence information, open after the outer triggering signal is received
Beginning timing, and the execution time period in each failure strategy, according to corresponding failure strategy to the ARINC429 that receives
Signal carries out fault item injection, and the ARINC429 signal for completing the injection of fault item is sent to the DAC.
External signal triggers interface 15, for receiving outer triggering signal.
ARINC429 bus failure injected system disclosed in the embodiment of the present invention, to additionally providing outer triggering signal interface
15, therefore can be with Devices to test/system combined by this interface, Devices to test/system can provide outer triggering signal,
After the system receives outer triggering signal, start timing, in the execution time period of each failure strategy, according to corresponding fault
Strategy carries out fault item injection to the ARINC429 signal for receiving, and therefore strengthens and associating between Devices to test/system, completes
Joint test.
Fig. 5 shows the ARINC429 bus failure injected system that the present invention is provided, and carries out series impedance fault, short circuit event
Barrier injection and the schematic diagram of parallel impedance direct fault location.First digital regulation resistance is connected in ARINC429 bus to be measured, and second
Digital regulation resistance is connected in parallel between the ARINC429 bus to be measured.
Physical layer direct fault location subelement, realizes series impedance fault note by controlling the resistance value of the first digital regulation resistance
Enter, and short trouble injection or parallel impedance direct fault location is realized by controlling the resistance value of the second digital regulation resistance.By making
With digital regulation resistance substitute traditional realize jointly parallel impedance fault and series impedance fault using relay and resistance compared with,
Resistance control flexibility is not only enhanced, a large amount of relays is also reduced, and then is saved hardware space, increased ARINC429
Bus failure injected system is while the quantity of test ARINC429 bus, improves system closeness.
Herein, such as first and second or the like relational terms be used merely to by an entity or operation with another
One entity or operation make a distinction, and not necessarily require or imply between these entities or operation there is any this reality
Relation or order.And, term " including ", "comprising" or its any other variant are intended to the bag of nonexcludability
Contain, so that a series of process including key elements, method, article or equipment not only include those key elements, but also including
Other key elements being not expressly set out, or also include the key element intrinsic for this process, method, article or equipment.
In the absence of more restrictions, the key element for being limited by sentence "including a ...", it is not excluded that including the key element
Process, method, also there is other identical element in article or equipment.
In this specification, each embodiment is described by the way of going forward one by one, and what each embodiment was stressed is and other
The difference of embodiment, between each embodiment identical similar portion mutually referring to.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or uses the present invention.
Multiple modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized without departing from the spirit or scope of the present invention in other embodiments.Therefore, the present invention
The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one
The most wide scope for causing.
Claims (7)
1. a kind of ARINC429 bus failure injected system, it is characterised in that include：ADC, FPGA module, DAC and Ethernet connect
Mouthful, wherein,
The ADC, for the conversion of the ARINC429 signal simulation amount to receiving to digital quantity, and sends to the FPGA
Module；
The FPGA module, for being connected with host computer by the Ethernet interface, receives the event issued from the host computer
Barrier injection sequence information, the direct fault location sequence information include multiple failure strategy, and the holding of each failure strategy
The row time period；And for starting timing when the direct fault location sequence information is received, in holding for each failure strategy
The row time period, fault item injection is carried out to the ARINC429 signal for receiving according to corresponding failure strategy, fault item will be completed
The ARINC429 signal of injection is sent to the DAC；
The DAC, carries out digital quantity for the ARINC429 signal to completing direct fault location described in receiving and arrives analog quantity
Conversion, and send to ARINC429 bus to be measured.
2. system according to claim 1, it is characterised in that the FPGA module includes：Direct fault location sequence control list
Unit, data receipt unit, Trouble Match unit, direct fault location unit data transmitting element, wherein,
The direct fault location sequence control unit, for receiving the direct fault location sequence information；Receiving fault note
Enter after sequence information and start timing, in the execution start time of each failure strategy, by corresponding failure strategy send to
The Trouble Match unit, and the Trouble Match unit and the direct fault location unit is respectively sent to by signal is enabled；?
The finish time of each failure strategy, forbidden energy signal is respectively sent to the Trouble Match unit and the direct fault location
Unit；
The data receipt unit, for receiving the ARINC429 signal of ADC transmission, and is carried out according to ARINC429 agreement
Conversion, obtains ARINC429 message；
The Trouble Match unit, for being mated to the ARINC429 message according to corresponding failure strategy,
The fault item of injection；
The direct fault location unit, for carrying out the injection of the fault item to the ARINC429 message；
The data transmission unit, for carrying out turning the ARINC429 message for completing the injection of fault item according to ARINC429 agreement
Change, obtain ARINC429 signal and send to the DAC.
3. system according to claim 2, it is characterised in that the direct fault location unit includes：Physical layer direct fault location
Subelement, electrical layer direct fault location subelement and protocol layer direct fault location subelement, wherein,
The physical layer direct fault location subelement, for the injection of physical layer fault item, the physical layer fault item includes short circuit
Fault, open circuit fault, series impedance fault and/or parallel impedance fault；
The electrical layer direct fault location subelement, for the injection of electrical layer fault item, the electrical layer fault item includes amplitude
Fault, slope fault, dutycycle fault, rate failure and/or noise failure；
The protocol layer direct fault location subelement, for the injection of protocol layer fault item, the protocol layer fault item includes LABEL
Fault is replaced in domain, and SDI domain is replaced fault, data field and replaces fault, SSM domain replacement fault, parity check bit fault, specific bit event
Barrier and/or frame length fault.
4. system according to claim 3, it is characterised in that the electrical layer direct fault location subelement is using at streamline
Reason mode.
5. system according to claim 2, it is characterised in that each described failure strategy include multiple matching conditions, with
And fault item corresponding with matching condition each described, each described matching condition is comprising its corresponding priority, the fault
Matching unit specifically for：
According to the priority of the matching condition, mated with the ARINC429 message successively, till the match is successful,
Using corresponding for the matching condition that the match is successful fault item as fault item to be injected.
6. system according to claim 1, it is characterised in that the system also includes：External signal triggers interface, is used for
Receive outer triggering signal；
The FPGA module, is additionally operable to receive what whether the direct fault location sequence information was started based on the outer triggering signal
Order, and, if the direct fault location sequence information is started based on the outer triggering signal, touch the outside is received
Start timing, and the execution time period in each failure strategy after signalling, according to corresponding failure strategy to receiving
ARINC429 signal carry out fault item injection, by complete fault item injection ARINC429 signal send to the DAC.
7. system according to claim 3, it is characterised in that the system also includes：
The first digital regulation resistance being connected in the ARINC429 bus to be measured, and it is total to be connected in parallel on the ARINC429 to be measured
The second digital regulation resistance in line,
The physical layer direct fault location subelement, for realizing serial resistance by controlling the resistance value of first digital regulation resistance
Fault-resistant injects, and realizes short trouble injection or parallel impedance fault by controlling the resistance value of second digital regulation resistance
Injection.
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| CN108494599A (en) * | 2018-03-29 | 2018-09-04 | 北京润科通用技术有限公司 | A kind of ARINC664 bus failures injected system and method |
| CN108508295A (en) * | 2018-03-29 | 2018-09-07 | 北京润科通用技术有限公司 | A kind of switching value fault injection system and method |
| CN109696899A (en) * | 2017-10-20 | 2019-04-30 | 中国商用飞机有限责任公司 | A kind of dedicated quality synthesis evaluation system of aircraft ARINC429 bus |
| CN109976960A (en) * | 2019-03-29 | 2019-07-05 | 北京润科通用技术有限公司 | A kind of bus test data method for implanting and device |
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| CN107194044A (en) * | 2017-05-08 | 2017-09-22 | 天津大学 | A kind of FIR filter fault filling method operated based on input and output data |
| CN107194044B (en) * | 2017-05-08 | 2020-08-18 | 天津大学 | FIR filter fault injection method based on input and output data operation |
| CN109696899A (en) * | 2017-10-20 | 2019-04-30 | 中国商用飞机有限责任公司 | A kind of dedicated quality synthesis evaluation system of aircraft ARINC429 bus |
| CN109696899B (en) * | 2017-10-20 | 2022-02-18 | 中国商用飞机有限责任公司 | Special quality comprehensive evaluation system for aircraft ARINC429 bus |
| CN107976916A (en) * | 2017-11-24 | 2018-05-01 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of ARINC429 Bus simulator methods based on Ethernet |
| CN108009060A (en) * | 2017-11-29 | 2018-05-08 | 北京润科通用技术有限公司 | A kind of RS485 bus failures analogy method and device |
| CN108414852A (en) * | 2018-01-30 | 2018-08-17 | 北京润科通用技术有限公司 | A kind of fault injection system and method for high-voltage digital amount signal |
| CN108334060A (en) * | 2018-03-15 | 2018-07-27 | 北京润科通用技术有限公司 | A kind of bus failure injection device |
| CN108459184A (en) * | 2018-03-23 | 2018-08-28 | 北京润科通用技术有限公司 | A kind of current failure method for implanting and system |
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| CN108494599A (en) * | 2018-03-29 | 2018-09-04 | 北京润科通用技术有限公司 | A kind of ARINC664 bus failures injected system and method |
| CN108469807A (en) * | 2018-03-29 | 2018-08-31 | 北京润科通用技术有限公司 | A kind of MVB bus fault injection system and method |
| CN108462616A (en) * | 2018-03-29 | 2018-08-28 | 北京润科通用技术有限公司 | A kind of fault injection device and fault filling method |
| CN109976960A (en) * | 2019-03-29 | 2019-07-05 | 北京润科通用技术有限公司 | A kind of bus test data method for implanting and device |
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