CN106470428A - A kind of precise synchronization of parallel multi-channel channel test equipment and triggering method - Google Patents

Abstract

The present invention provides a precise synchronization and triggering method for parallel multi-channel channel test equipment. A main channel is selected among multiple channels, and each channel waits to receive the first rising edge of the synchronization pulse sent by the main channel until Received; within one cycle after the first rising edge of the sync pulse, each channel detects the time difference between the first rising edge of the common sync pulse clock and the first rising edge of the common trigger reference clock; according to the time difference, Automatically align the phases of the sampling clocks of all channels with the common trigger reference clock; with the falling edge of the common trigger reference clock, when the trigger signal sent from the main channel is sent to all channels and detected, the next common trigger Referring to the rising edge of the clock, all channels perform signal generation or signal acquisition simultaneously. The invention can achieve ps-level synchronization precision through the modular instrument and the modular instrument bus architecture.

Description

A Precise Synchronization and Triggering Method for Parallel Multi-Channel Channel Test Equipment

technical field

The invention relates to the technical field of wireless communication, in particular to a precise synchronization and trigger method for parallel multi-channel channel test equipment.

Background technique

Multiple-Input Multiple-Output MIMO (Multiple-Input Multiple-Output MIMO) technology refers to the use of multiple transmitting antennas and receiving antennas at the transmitting end and receiving end, so that signals are transmitted and received through multiple antennas at the transmitting end and receiving end, thereby improving communication quality. MIMO technology can make full use of space resources and realize multiple transmissions and multiple receptions through multiple antennas. Without increasing spectrum resources and antenna transmission power, it can double the system channel capacity and has obvious advantages. Therefore, it is regarded as the next generation The core technology of mobile communication. The test equipment corresponding to MIMO technology is parallel multi-channel channel test equipment.

3GPP has introduced 8 MIMO transmission modes downlink from the LTE-FDD version. Among them, the commonly used MIMO transmission modes of LTE-FDD are Mode 1 to Mode 6 (TM1~TM6), while Mode 7 (TM7) and Mode 8 (TM8) mainly Applied in TD-LTE system.

With the rapid development of wireless mobile communication technology, compared with MIMO technology, the corresponding test solution has lagged behind for a long time, and there is no overall solution that fully meets the needs of users. Therefore, when facing the MIMO technology at the initial stage, the MIMO system is usually tested separately as multiple single input single output (Single Input Single Output, SISO) systems.

Early MIMO test equipment is basically a MIMO test system composed of a single instrument stack. In this way, because the equipment does not share the local oscillator, the signal lines from the time base signal and trigger signal to each instrument have no unified control and length guarantee, and the performance cannot guarantee convergence and high precision. Therefore, such a MIMO test system can basically only be used to complete verification of some relatively single algorithms.

Therefore, the MIMO test method in the prior art has the following deficiencies:

(1) It cannot be fully applied to the synchronization between multiple channels;

(2) More attention is paid to starting at the same time, and the phase consistency of the synchronous channel is not strictly considered;

(3) Due to the limitations of openness and discreteness based on traditional instrument integration, the accuracy is generally at the ms level, which cannot reach the required accuracy.

The complexity of synchronizing multiple RF channels is that each RF channel can work under different sampling clocks, so how to make all the sampling clocks start at the same point will become a challenge; the second difficulty lies in the synchronization accuracy, how to make the channels It has also become a hot topic to achieve ps-level precision of inter-synchronization precision.

Contents of the invention

In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a precise synchronization and trigger method for parallel multi-channel channel test equipment, which is applied to MIMO wireless channel measurement, wave velocity shaping, and spatial angle positioning. The four steps of signal regeneration, real-time calibration, knocking signal and confirmation trigger are two-level trigger mechanism to achieve the precise synchronization of parallel multi-channel channel test equipment.

In order to achieve the above object and other related objects, the present invention provides a method for accurate synchronization and triggering of parallel multi-channel channel test equipment, including the following steps: Step S1, setting the sampling clock of each channel; Step S2, according to the sampling clock of each channel Sampling clock frequency and the number of channels calculate the shared signal of unified frequency, which is defined as a common trigger reference clock; step S3, distribute the reference clock of the parallel multi-channel channel test equipment bus to all channels, so as to be used as the phase-locking of all channel sampling clocks ; Step S4, setting the common synchronous pulse clock, and deploying the common synchronous pulse clock on all channels; Step S5, selecting one of the multiple channels as the main channel, when the common synchronous pulse clock is triggered by the bus When the line is at a logic high level, the main channel generates a synchronous pulse; Step S6, initialize each channel of the parallel multi-channel channel test equipment, each channel waits to receive the first rising edge of the synchronous pulse sent by the main channel, Until it is received; step S7, within one cycle after the first rising edge of the synchronization pulse, each channel detects the first rising edge of the common synchronization pulse clock and the first rising edge of the common trigger reference clock The time difference between two rising edges; Step S8, compare each time difference detected from the channel and the time difference detected by the master channel, automatically align the sampling clocks of all channels with the phase of the common trigger reference clock; Step S9, With the falling edge of the common trigger reference clock, when the trigger signal sent from the main channel is sent to all channels and detected, at the next rising edge of the common trigger reference clock, all channels simultaneously perform signal generation or signal Obtain.

According to the above precise synchronization and triggering method for parallel multi-channel channel test equipment, wherein: in the step S1, the frequency of the sampling clock of each channel is the same.

According to the above precise synchronization and triggering method for parallel multi-channel channel test equipment, wherein: in the step S2, the least common multiple of the sampling clock frequencies of all channels is the frequency of the common trigger reference clock.

According to the above precise synchronization and trigger method for parallel multi-channel channel test equipment, wherein: in the step S4, the frequency of the common synchronization pulse clock is the same as the frequency of the reference clock of the bus architecture.

According to the above precise synchronization and triggering method for parallel multi-channel channel test equipment, wherein: in the step S5, any channel in the selected multi-channel is the master channel, while other channels become the slave channels.

According to the above precise synchronization and trigger method for parallel multi-channel channel test equipment, wherein: in the step S8, the phases of the sampling clocks of all channels are automatically aligned with the phase of the common trigger reference clock by adjusting the DAC/ADC phase output.

According to the above precise synchronization and trigger method for parallel multi-channel channel test equipment, wherein: at least three signal lines for multi-channel synchronization are defined in the bus: a synchronization line, a trigger line, and a clock line.

According to the above-mentioned accurate synchronization and triggering method of parallel multi-channel channel test equipment, wherein: PCB lines of equal length are designed in the bus, so that the synchronization signal, trigger signal, and clock signal received by each channel pass through equal-length paths .

According to the above precise synchronization and trigger method for parallel multi-channel channel test equipment, a 10 MHz reference clock is used as the frequency of the common trigger reference clock.

As mentioned above, the precise synchronization and triggering method of the parallel multi-channel channel test equipment of the present invention has the following beneficial effects:

(1) Applied to multiple channels of the same device, the precise synchronization of parallel multi-channel channel test equipment is realized through the four-step two-level trigger mechanism of trigger signal regeneration, real-time calibration, knock signal and confirmation trigger;

(2) Applicable to technical fields such as spatial positioning, beamforming, and angle domain analysis of high-precision channel data;

(3) Synchronization accuracy of ps level can be achieved through modular instrument and modular instrument bus architecture.

Description of drawings

Fig. 1 is shown as the flow chart of the precise synchronization and triggering method of parallel multi-channel channel test equipment of the present invention;

Fig. 2 is shown as the schematic diagram of the sampling clocks of each channel aligned by the time difference in the present invention;

FIG. 3 is a schematic diagram of multi-channel trigger synchronization after calibration in the present invention.

detailed description

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

The precise synchronization and triggering method of the parallel multi-channel channel test equipment of the present invention is based on the modular instrument and the PXI-E bus modular instrument bus architecture, the mechanism of synchronization and triggering is designed, and the performance of synchronization and triggering is improved, so it can be directly MIMO devices are tested and can be applied to high-level applications that are sensitive to the phase between multiple channels, such as: signal angle domain estimation and analysis, beamforming, etc.

It should be noted that the precise synchronization and triggering method of the parallel multi-channel channel test equipment of the present invention is aimed at the synchronization between channels, that is, at the sending end, all transmitters of the multi-channel transmitter start to transmit at the same time, or according to the trigger signal. Start to transmit at the same time under a certain condition; at the receiving end, all receivers of the multi-channel receiver start to receive at the same time, or start to receive at the same time under a certain condition according to the trigger signal.

Among them, the present invention adopts a modular instrument bus architecture, and at least three signal lines for multi-channel synchronization are defined in the bus signal: a synchronization line, a trigger line, and a clock line. Specifically, PCB lines of equal length are designed in the bus architecture, so that the synchronization signal, trigger signal, and clock signal received by each channel pass through paths of equal length.

With reference to Fig. 1, the precise synchronization and triggering method of parallel multi-channel channel test equipment of the present invention comprises the following steps:

Step S1, setting the sampling clock of each channel.

Specifically, sampling clocks of different frequencies can be set for each channel through programming, and sampling clocks of the same frequency can also be set. At the same time, each channel has the function of receiving trigger signals. Preferably, the frequency of the sampling clock of each channel is set to be the same, so as to make subsequent tests easier.

Step S2, calculating a shared signal of uniform frequency according to the sampling clock frequency of each channel and the number of channels, which is defined as a shared trigger reference clock (Share Trigger Reference Clock, STRC).

Among them, the main control program calculates a shared signal with a unified frequency according to the sampling clock frequency and the number of channels of each channel, which is defined as STRC.

The least common multiple of the sampling clock frequencies of all channels is the STRC frequency.

Step S3 , distributing the 10 MHz reference clock of the parallel multi-channel channel test equipment bus to all channels, so as to be used as phase-locking of sampling clocks of all channels.

Among them, the sampling clocks of these channels are only phase-locked to the reference clock of the bus architecture, and phase alignment is not implemented.

Step S4, setting a common sync pulse clock (Share Sync Plus Clock, SSPC), and deploying the SSPC to all channels.

Specifically, the frequency of SSPC can be set through the main program, and deployed to all channels through the trigger line of the bus. Preferably, if the parallel multi-channel channel test application uses 10 MHz as the frequency of the SSPC, then the 10 MHz reference clock of the bus can be used as the SSPC at the same time.

Step S5, select one of the multiple channels as the main channel, and when the trigger line of the SSPC through the bus is at logic high level, the main channel generates a synchronization pulse.

Specifically, a certain channel among the multi-channels is set as the master channel through the master control program, and other channels are slave channels.

Step S6. Initialize each channel of the parallel multi-channel channel testing device, and each channel waits to receive the first rising edge of the synchronization pulse sent by the main channel until it receives it.

Step S7 , within one cycle after the first rising edge of the synchronization pulse, each channel detects the time difference between the first rising edge of SSPC and the first rising edge of STRC.

Specifically, within one cycle after the first rising edge of the synchronous pulse, when each channel detects the first rising edge of SSPC, the main control program controls each channel to detect the first rising edge of SSPC and the The time difference between the first rising edges of STRC within a period.

Step S8, comparing the time difference detected by each slave channel with the time difference detected by the master channel, and automatically aligning the phases of the sampling clocks of all channels with the STRC.

Specifically, the time difference detected by any channel may also be compared with the time differences detected by other channel devices. The phases of the sampling clocks of all channels are automatically aligned with the phase of the STRC by adjusting the DAC/ADC (Digital-to-Analog Converter/Analog-to-Digital Converter) phase output.

Step S9, when the trigger signal sent from the main channel is sent to all channels and detected along with the falling edge of STRC, at the next rising edge of STRC, all channels perform signal generation or signal acquisition simultaneously.

Specifically, with the alignment of the sampling clocks of each channel, the trigger signal is deployed to all channels from the agreed master channel at the falling edge of STRC. On the rising edge of the next STRC of the master channel, all slave channels are programmed to perform signal generation or signal acquisition. This final real trigger signal can be deployed via bus architecture trigger signals or external wiring.

The precise synchronization and triggering method of the parallel multi-channel channel test equipment of the present invention will be described in detail below through specific embodiments.

In this embodiment, an 8-channel parallel channel test device is integrated using a vector signal transceiver (Vector Signal Transceiver, VTS)-based modular instrument and a PXI-E bus architecture. PXI-E bus provides 10MHz public trigger reference clock signal, 100MHz differential clock and trigger bus, etc. All channels share the same local oscillator source. The sending end of the channel testing equipment is an 8-channel transmitter, which sends an orthogonal pseudo-noise sequence (Pseudo-noise Sequence, PN); the receiving end of the channel testing equipment is an 8-channel receiver, which receives the transmitted data stream. The data of the channel test needs to be analyzed in multiple dimensions of time-frequency-space, which has high requirements for phase synchronization, which specifically includes the following steps:

(1) The function of setting the sampling clock of the same frequency and receiving the trigger signal for 8 channels by programming.

(2) The main control program sets the frequency of STRC as 2 times the sampling clock frequency.

(3) The 10MHz reference clock of the bus architecture is distributed to all channels to be used as the phase lock of the sampling clocks of all radio frequency channels. Among them, the sampling clock of each channel is phase-locked to the 10MHz reference signal of the bus, but the sampling clocks of these channels are not phase-aligned.

(4) Adopt 10MHz reference clock as the frequency of SSPC.

(5) Set the first channel as the main channel, and send a trigger signal to the main channel through the GPS integrated in the chassis. After receiving the trigger signal, the main channel generates a synchronous pulse for triggering, and passes the Distributed to slave channels and to self.

(6) After all channels are initialized, they wait to receive the rising edge of the first sync pulse until it is received.

(7) When the rising edge of the first sync pulse is detected, each channel is programmed to test the time difference between the first rising edge of SSPC and the first rising edge of STRC. Each channel detects its own time difference.

As shown in Figure 2, for channel 1 and channel N, although the sampling clock is phase-locked with the 10MHz reference clock, the phases are not aligned. There is a time difference of ΔT2 between the time difference between channel 1 and channel N.

(8) The time difference of each channel is compared with that of the main channel, and the sampling clocks of all channels and STRC are automatically aligned by adjusting the DAC/ADC phase output.

As shown in Figure 3, after calibration, all channels are triggered synchronously.

(9) After all channel sampling clocks are aligned with the STRC phase, the trigger pulse for synchronization generated by the main channel is sent to all channels along with the falling edge of the main channel STRC, and is detected. On the next rising edge of STRC, all RF channels of the 8-channel transmitter transmit, and all RF channels of the 8-channel receiver receive. This final real trigger signal is also deployed through the trigger lines of the PXI-E bus.

After the above steps are implemented on the FPGA boards of each radio frequency channel, a synchronization accuracy of 43 ps is obtained in actual measurement.

In summary, the precise synchronization and triggering method of the parallel multi-channel channel test equipment of the present invention is applied between multiple channels of the same equipment, through the four steps of trigger signal regeneration, real-time calibration, knocking signal and determining trigger. Level trigger mechanism to achieve precise synchronization of parallel multi-channel channel test equipment; suitable for spatial positioning, beamforming, high-precision channel data angle domain analysis and other technical fields; through modular instruments and modular instrument bus architecture can reach ps level synchronization accuracy. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (9)

1. a kind of precise synchronization of parallel multi-channel channel test equipment and triggering method it is characterised in that：Comprise the following steps：

Step S1, the sampling clock of each passage is set；

Step S2, the sample clock frequency according to each passage and port number calculate the shared signal of unified frequency, are defined as Public triggering reference clock；

Step S3, the reference clock of parallel multi-channel channel test equipment bus is assigned to all of passage, for use as institute There is the lock phase of channel sample clock；

Step S4, the public lock-out pulse clock of setting, and described public lock-out pulse clock is deployed on all passages；

Step S5, select one in multiple passages as main channel, when described public lock-out pulse clock passes through bus When firing line is in logic high, main channel produces a lock-out pulse；

Step S6, each passage of initialization parallel multi-channel channel test equipment, each passage etc. is to be received to be led to by main First rising edge of the described lock-out pulse that road sends, till receiving；

In step S7, a cycle after the first rising edge of described lock-out pulse, public described in each Air conduct measurement Time difference between first rising edge of first rising edge of lock-out pulse clock and described public triggering reference clock；

Step S8, compare each time difference detected by from passage and the time difference detected by main channel, will be all logical The sampling clock in road and the phase place automatic aligning of described public triggering reference clock；

Step S9, the trailing edge with described public triggering reference clock, the trigger sending from main channel is sent to institute When having passage and being detected, in the rising edge of the described public triggering reference clock of the next one, all passages execute signal simultaneously Occur or signal acquisition.

2. the precise synchronization of parallel multi-channel channel test equipment according to claim 1 and triggering method it is characterised in that：Institute State in step S1, the frequency of the sampling clock of each passage is identical.

3. the precise synchronization of parallel multi-channel channel test equipment according to claim 1 and triggering method it is characterised in that：Institute State in step S2, the least common multiple of the sample clock frequency of all passages is the frequency of public triggering reference clock.

4. the precise synchronization of parallel multi-channel channel test equipment according to claim 1 and triggering method it is characterised in that：Institute State in step S4, the frequency of described public lock-out pulse clock is identical with the frequency of the reference clock of bus architecture.

5. the precise synchronization of parallel multi-channel channel test equipment according to claim 1 and triggering method it is characterised in that：Institute State in step S5, the arbitrary passage in selected multichannel is main channel, and other passages then become from passage.

6. the precise synchronization of parallel multi-channel channel test equipment according to claim 1 and triggering method it is characterised in that：Institute State in step S8, the phase place of the sampling clock of all passages is automatically public with described by adjusting DAC/ADC phase output The phase alignment of triggering reference clock.

7. the precise synchronization of parallel multi-channel channel test equipment according to claim 1 and triggering method it is characterised in that：Institute Stating at least definition in bus has line synchro, firing line, three kinds of clock line to be used for the holding wire of multi-channel synchronous.

8. the precise synchronization of parallel multi-channel channel test equipment according to claim 1 and triggering method it is characterised in that：? Design isometric PCB circuit in described bus, make synchronizing signal, trigger, clock signal that each channel reception arrives Through isometric path.

9. the precise synchronization of parallel multi-channel channel test equipment according to claim 1 and triggering method it is characterised in that：Adopt With 10MHz reference clock as the described public frequency triggering reference clock.