Specific embodiment
Fig. 1 is the schematic diagram of the wireless power transmission device of one embodiment of the invention.Referring to Fig. 1, wireless power transmission device
100 include power-switching circuit 110, resonance circuit 120, detection circuit 130 and control circuit 140.Wherein, resonance circuit 120
Include the resonance coil 121 and resonant capacitance 122 sequentially concatenated.
The input terminal of power-switching circuit 110 is electrically connected to front stage circuits 150, and receives from front stage circuits 150
Input signal Vi, and the control terminal of power-switching circuit 110 is electrically connected to control circuit 140, and receives and come from control circuit
140 first control signal Vc1 and second control signal Vc2.The first end of the resonance coil 121 of resonance circuit 120 electrically connects
It is connected to power-switching circuit 110, and receives the modulating signal Vm from power-switching circuit 110.The resonance electricity of resonance circuit 120
The first end of appearance 122 is electrically connected to the second end of resonance coil 121, and the first end of the resonant capacitance 122 of resonance circuit 120
It is electrically connected to connects end altogether Gnd.Detection circuit 130 is electrically connected to the second end of resonance coil 121, and receives and carry out self-resonance electricity
The power supply information Dp on road 120.The input terminal of control circuit 140 is electrically connected to the output end of detection circuit 130, and receives and come from
The first predetermined period parameter P1, the second predetermined period parameter P2 and the pre-set delay parameter P3 of detection circuit 130.Control circuit
140 clock pulse end is electrically connected to time clock source (not shown), and receives the clock signal clk from time clock source.
Front stage circuits 150 are to generate input signal Vi.In this, front stage circuits 150 can be a kind of power-supply unit, example
Such as battery, and input signal Vi caused by front stage circuits 150 can be a kind of voltage signal or current signal.
Power-switching circuit 110 to according to first control signal Vc1 and second control signal Vc2 to input signal Vi into
Row conversion, to generate corresponding modulating signal Vm.In this, power-switching circuit 110 can be to be made of two power switch M1, M2
Converter of semi-bridge type, and this two power switch M1, M2 are respectively by first control signal Vc1 and second control signal Vc2 institute
Control.In one embodiment, as first control signal Vc1 conducting power switch M1, second control signal Vc2 can not be simultaneously connected
Power switch M2, that is, the phase of first control signal Vc1 and second control signal Vc2 can mutually stagger.However, the present invention is simultaneously
It is non-as limit, power-switching circuit 110 can also the full-bridge converter composed by four power switch realize.
In this, power-switching circuit 110 is responsibility cycle (duty cycle, the duty according to first control signal Vc1
Than) with the size of the responsibility cycle of second control signal Vc2 generate corresponding modulating signal Vm.For example, when the first control
The responsibility cycle of signal Vc1 processed and the responsibility cycle of second control signal Vc2 are bigger, and power-switching circuit 110 can believe input
The time that number Vi is converted is longer, therefore the energy of modulating signal Vm that corresponding conversion goes out is also bigger;Conversely, when the first control
The responsibility cycle of signal Vc1 processed and the responsibility cycle of second control signal Vc2 are smaller, and power-switching circuit 110 can believe input
The time that number Vi is converted is shorter, therefore the energy of modulating signal Vm that corresponding conversion goes out is also smaller.
In the present embodiment, front stage circuits 150 above-mentioned can be direct current power supply unit, and provided input signal
Vi is DC power signal, and power-switching circuit 110 can be switcher for changing DC into AC, and the modulating signal Vm converted out is
Ac supply signal.
Resonance circuit 120 generates corresponding power supply letter to the modulating signal Vm according to caused by power-switching circuit 110
Number Vp, and power supply signal Vp is sent to and receives electric installation (not shown).In this, though resonance circuit 120 is only painted a resonance coil
121 and a resonant capacitance 122, but actually the quantity of resonance coil 121 and a resonant capacitance 122 be can be according to the difference of design
And change, and the sequential system of the coupling resonant capacitance 122 of resonance coil 121 can also be changed to couple resonance line by resonant capacitance 122
The sequential system of circle 121, the present invention is not limited thereto.
Detection circuit 130 is to generate corresponding first predetermined period parameter according to the power supply information Dp of resonance circuit 120
P1, the second predetermined period parameter P2 and pre-set delay parameter P3.Detection circuit 130 may include processing unit 131 and detection unit
132。
In the present embodiment, the detection unit 132 of detection circuit 130 can be a kind of direct current sensing circuit, to be detected in
The DC voltage or DC current of node N1, and the processing unit 131 of detection circuit 130 can be according to detection unit 132 in section
The size of DC voltage or DC current that point N1 is detected is default to adjust the first predetermined period parameter P1, second that it is exported
Cycle parameter P2 and pre-set delay parameter P3, use change in the DC voltage or DC current of node N1, in this, electricity at this time
Source information Dp is DC voltage or DC current above-mentioned.However, invention is not limited thereto, and in another embodiment, inspection
The detection unit 132 of slowdown monitoring circuit 130 also can be a kind of temperature sensing circuit, to be detected in the temperature of node N1, and detect electricity
The processing unit 131 on road 130 can adjust the first predetermined period of its output according to the temperature level detected in node N1
Parameter P1, the second predetermined period parameter P2 and pre-set delay parameter P3 use change in the temperature of node N1, in this, at this time
Power supply information Dp is temperature above-mentioned.
In addition, may include storage element 133 in detection circuit 130, include to store comparison list, and in this table of comparisons
The corresponding relationship of power supply information Dp and the first predetermined period parameter P1, the second predetermined period parameter P2 and pre-set delay parameter P3.
Therefore, processing unit 131 can capture corresponding first predetermined period ginseng according to the numerical value of power supply information Dp from the table of comparisons
Number P1, the second predetermined period parameter P2 and pre-set delay parameter P3 are exported.
Control circuit 140 is to the first predetermined period parameter for being exported according to clock signal clk and detection circuit 130
P1, the second predetermined period parameter P2, which generate the control of corresponding first control signal Vc1 and second with pre-set delay parameter P3, to be believed
Number Vc2, to control in power-switching circuit 110 above-mentioned during the conducting of each power switch M1, M2.In this, the first control is believed
The responsibility cycle of number Vc1 corresponds to the first predetermined period parameter P1, and the responsibility cycle of second control signal Vc2 corresponds to
Second predetermined period parameter P2.In addition, there is poor t1 at the first time between first control signal Vc1 and second control signal Vc2,
And poor t1 corresponds to pre-set delay parameter P3 at the first time.
Fig. 2 is the schematic diagram of an embodiment of control circuit in Fig. 1.Fig. 1 and Fig. 2 are please referred to, control circuit 140 is wrapped
Mould group 143 and the second output mould group 144 are exported containing signal generator 141, delay mould group 142, first.
The input terminal of signal generator 141 is electrically connected to the processing unit 131 of detection circuit 130, and receives from place
Manage the first predetermined period parameter P1, the second predetermined period parameter P2 and the pre-set delay parameter P3 of unit 131.Signal generator
141 signal end is electrically connected to time clock source, and receives the clock signal clk from time clock source.The electrical property of delay mould group 142 connects
It is connected to time clock source, and receives the clock signal clk from time clock source.When the clock pulse end of first output mould group 143 is electrically connected to
Arteries and veins source, and receive the clock signal clk from time clock source.The control terminal of first output mould group 143 is electrically connected to detection circuit
130 processing unit 131, and receive the first predetermined period parameter P1 from processing unit 131.First output mould group 143
First input end is electrically connected to signal generator 141, and receives the first coarse tuned output signal from signal generator 141
Voc1, and at least one second input terminal of the first output mould group 143 is electrically connected to delay mould group 142, and receives and carry out self-dalay
An at least postpones signal for mould group 142.The clock pulse end of second output mould group 144 is electrically connected to time clock source, and receives when coming from
The clock signal clk in arteries and veins source.The control terminal of second output mould group 144 is electrically connected to the processing unit 131 of detection circuit 130,
And receive the second predetermined period parameter P2 from processing unit 131.The first input end of second output mould group 144 is electrically connected
To signal generator 141, and the second coarse tuned output signal Voc2 from signal generator 141 is received, and the second output mould group
144 at least one second input terminal is electrically connected to delay mould group 142, and receives at least one delay for carrying out self-dalay mould group 142
Signal.In this, the first predetermined period parameter P1 includes the first coarse adjustment parameter P11 and the first fine tuning parameter P12, and second is default all
Period parameters P2 includes the second coarse adjustment parameter P21 and the second fine tuning parameter P22.
In the present embodiment, signal generator 141 includes the first signal generation unit 1411, trigger unit 1412 and the
Binary signal generates unit 1413.Wherein, the first signal generation unit 1411 is electrically connected to time clock source, and receives and come from time clock source
Clock signal clk, and the first signal generation unit 1411 is electrically connected to the processing unit 131 of detection circuit 130, and receives
The first predetermined period parameter P1 from processing unit 131, and then can be according to the first coarse adjustment in the first predetermined period parameter P1
Parameter P11 generates the first coarse tuned output signal Voc1.Trigger unit 1412 is electrically connected to time clock source, and receives and come from time clock source
Clock signal clk, and trigger unit 1412 is electrically connected to the processing unit 131 of detection circuit 130, and receives from processing
The pre-set delay parameter P3 of unit 131, and then trigger signal Vt can be generated according to pre-set delay parameter P3.Second signal generates single
Member 1413 is electrically connected to time clock source, and receives the clock signal clk from time clock source, and second signal generates 1413 electricity of unit
Property be connected to the processing unit 131 of detection circuit 130, and receive the second predetermined period parameter P2 from processing unit 131, again
Second signal generates unit 1413 and is electrically connected to trigger unit 1412, and receives the trigger signal from trigger unit 1412
Vt, and then the second coarse adjustment output can be generated according to the second coarse adjustment parameter P21 in trigger signal Vt, the second predetermined period parameter P2
Signal Voc2.
In this, first signal generation unit 1411 can be realized with counter, such as: there is the counting for being loaded into numerical value function
Device.Therefore, in one embodiment, the first signal generation unit 1411 can be loaded into the first coarse adjustment parameter P11, and be based on clock signal
The frequency of clk counts the numerical value of the first coarse adjustment parameter P11, to generate the first coarse tuned output signal Voc1.Wherein, first is thick
The responsibility cycle of output signal Voc1 is adjusted to correspond to the first coarse adjustment parameter P11.
Trigger unit 1412 also can with counter, such as: have be loaded into numerical value function lower counter (down
Counter), arrange in pairs or groups anti-or lock (NOR gate) Lai Shixian.Therefore, in one embodiment, trigger unit 1412 can pass through lower number
Counter is loaded into pre-set delay parameter P13, with the number for the pre-set delay parameter P13 that the frequency based on clock signal clk is loaded into certainly
Value counts downwards, and generates trigger signal Vt through anti-or lock after having counted.
And second signal generation unit 1413 is generally identical as the first signal generation unit 1411, and also can be with counter
To realize.In this, second signal generates unit 1413 and starts to make after receiving the trigger signal Vt from trigger unit 1412
It is dynamic, and it can be loaded into the second coarse adjustment parameter P21, and based on numerical value work of the frequency of clock signal clk to the second coarse adjustment parameter P21
Number, to generate the second coarse tuned output signal Voc2.Wherein, it is thick to correspond to second for the responsibility cycle of the second coarse tuned output signal Voc2
Adjust parameter P21.
In this, the period of the first coarse tuned output signal Voc1 above-mentioned substantially the first coarse adjustment parameter P11 and clock pulse are believed
Twice of the product in the period of number clk, that is, the period of the first coarse tuned output signal Voc1 formula can indicate later: TVOC1=2*
One coarse adjustment parameter * Tclk, wherein TVOC1For the period of the first coarse tuned output signal Voc1, TclkFor the period of clock signal clk.Together
Sample, the substantially week of the second coarse adjustment parameter P21 and clock signal clk in the period of the second coarse tuned output signal Voc2 above-mentioned
Twice of the product of phase, that is, the period of the second coarse tuned output signal Voc2 formula can indicate later: TVOC2The second coarse adjustment of=2* ginseng
Number * Tclk, wherein TVOC2For the period of the second coarse tuned output signal Voc2, TclkFor the period of clock signal clk.
Therefore, under the frequency based on same clock signal clk, as the first coarse adjustment parameter P1 that detection circuit 130 is exported
Or second coarse adjustment parameter it is bigger when, the letter of the first coarse tuned output signal Voc1 caused by the first signal generation unit 1411 or second
Number generate unit 1413 caused by the second coarse tuned output signal Voc2 period it is bigger, in other words, the first coarse tuned output signal
The frequency of Voc1 or the second coarse tuned output signal Voc2 are smaller.
Fig. 3 is the waveform of an embodiment of the first coarse tuned output signal, the second coarse tuned output signal and clock signal in Fig. 2
Schematic diagram.Please refer to Fig. 2 and Fig. 3, due to second signal generate unit 1413 after receiving trigger signal Vt just
Actuation, therefore second signal generates the second coarse tuned output signal Voc2 and the first coarse tuned output signal Voc1 caused by unit 1413
Between can have poor t1 at the first time.In this, poor t1 substantially pre-set delay parameter P3 and clock signal clk at the first time
The product in period, in other words, the second coarse tuned output signal Voc2 can be delayed by the integral multiple in the period of clock signal clk.
In the present embodiment, the duty of the responsibility cycle of the first coarse tuned output signal Voc1 and the second coarse tuned output signal Voc2
Appointing the period is essentially 50%.
Postpone mould group 142 sequentially to generate N number of postpones signal according to clock signal clk, wherein N be more than or equal to
1 positive integer.In one embodiment, delay mould group 142 can have the delay line of N number of delay-level to realize.Hereinafter, being with N
For 7, i.e., delay mould group 142 can be the delay line as composed by seven delay-level 1421~1427, and postpone mould group 142
Seven delay-level 1421~1427 sequentially concatenating be can pass through sequentially to generate seven postpones signals according to clock signal clk
Vd1~Vd7, but the present invention is not limited thereto, and the quantity end of the postpones signal of delay-level and its generation is depending on Demand Design.
As shown in Fig. 2, each delay-level 1421~1427 can produce postpones signal Vd1~Vd7 of correspondence.First is prolonged
Slow grade 1421 is electrically connected to time clock source, and receives the clock signal clk from time clock source, to generate first postpones signal
Vd1 output, wherein having one second time difference t2 between first postpones signal Vd1 and clock signal clk;Second delay-level
1422 are electrically connected to the output end of first delay-level 1421, and receive first delay from first delay-level 1421
Signal Vd1, to generate second postpones signal Vd2 output, wherein second postpones signal Vd2 and first postpones signal Vd1
Also there is the second time difference t2, sequentially class is pushed into the 7th delay-level 1427 with this.
Fig. 4 is the waveform schematic diagram of an embodiment of clock signal and postpones signal in Fig. 2.It please arrange in pairs or groups refering to Fig. 2
With Fig. 4, all there is the second time difference t2 between each two adjacent postpones signals, and clock signal clk and adjacent delay are believed
Also there is the second time difference t2 between number (that is, first postpones signal Vd1).In other words, clock signal clk, seven delay letters
Sequentially there is the second time difference t2 between number Vd1~Vd7.Wherein, the second time difference t2 substantially period of clock signal clk
Divided by (N+1), that is, the second time difference t2 formula can be indicated later: the second time difference t2=Tclk/ (N+1), and N >=1, wherein
Tclk is the period of clock signal clk.
First output mould group 143 is to first coarse tuned output signal according to caused by the first signal generation unit 1411
Voc1, clock signal clk, postpones signal Vd1~Vd7 and the first fine tuning parameter P12 generate the first control signal after fine tuning
Vc1.In the present embodiment, the first output mould group 143 may include N+1 the first sampling units, the first signal behavior unit 1432
And first signal generation unit 1433.
Each first sampling unit is respectively provided with an input terminal D, clock pulse end CK and output end Q.Wherein, first first sampling
The input terminal D of unit 1431a is electrically connected to the first signal generation unit 1411, comes from the first signal generation unit to receive
1411 the first coarse tuned output signal Voc1, the clock pulse end CK of first the first sampling unit 1431a is electrically connected to time clock source,
To receive the clock signal clk from time clock source, and first the first sampling unit 1431a can be according to the first coarse tuned output signal
Voc1 and clock signal clk generates first the first fine tuning output signal Vf11;And the input terminal D of the first sampling unit of m-th
It is electrically connected to the output end Q of M-1 the first sampling units, it is thin to receive first from M-1 the first sampling units
Output signal is adjusted, the clock pulse end CK of the first sampling unit of m-th is electrically connected to the M-1 delay-level in delay mould group 142
Output end, to receive the postpones signal from the M-1 delay-level, and M-1 the first sampling units can be according to M-1 the
One fine tuning output signal and the M-1 postpones signal generate the first fine tuning of m-th output signal.In this, aforementioned M can for comprising
All positive integers greater than 1 and less than or equal to N.Be illustrated so that N is equal to 7 as an example hereinafter, connecting, wherein M include greater than 1 and
All positive integers less than or equal to 7.
In an embodiment of the present invention, the first output mould group 143 may include eight first sampling unit 1431a~1431h,
And it can produce eight first fine tuning output signal Vf11~Vf18 altogether.Wherein, first the first sampling unit 1431a is based on clock pulse
The frequency of signal clk samples the first coarse tuned output signal Voc1, and generates first the first fine tuning output signal Vf11;Second
A frequency of the first sampling unit 1431b based on first postpones signal Vd1 takes first the first fine tuning output signal Vf11
Sample, and generate second the first fine tuning output signal Vf12;The first sampling unit 1431c of third is based on second postpones signal
The frequency of Vd2 samples second the first fine tuning output signal Vf12, and generates the first fine tuning output signal Vf13 of third;The
Four frequencies of the first sampling unit 1431d based on third postpones signal Vd3 are to the first fine tuning output signal Vf13 of third
Sampling, and generate the 4th the first fine tuning output signal Vf14;Sequentially class is pushed into the 8th the first sampling unit 1431f according to this.
In this, second the first sampling unit 1431b is based between first postpones signal Vd1 and clock signal clk
Two time difference t2, second the first fine tuning output signal Vf12 generated is also between first the first fine tuning output signal Vf11
With the second time difference t2;The first sampling unit 1431c of third is based on second postpones signal Vd2 and first postpones signal
The second time difference t2 between Vd1, the first fine tuning output signal Vf13 of the third generated are also exported with second the first fine tuning
There is the second time difference t2 between signal Vf12, sequentially analogized with this.
In addition, to be generally equal to the first coarse adjustment defeated for the waveform of all first fine tuning output signal Vf11~Vf18 above-mentioned
The waveform of signal Voc1 out, and the responsibility cycle of each first fine tuning output signal Vf11~Vf18 and the first coarse tuned output signal
The responsibility cycle of Voc1 is generally equal and can be 50%.
In some embodiments, each first sampling unit in the first output mould group 143 can be realized with D-type flip-flop.
First signal behavior unit 1432 has control terminal and input terminal, wherein the control of the first signal behavior unit 1432
End is electrically connected to the processing unit 131 of detection circuit 130, and receives the first fine tuning parameter P12 from processing unit 131,
And first the input terminal of signal behavior unit 1432 be electrically connected to the output end Q of N+1 the first sampling unit, and receive and come from
All first fine tuning output signals of N+1 the first sampling units.Therefore, the first signal behavior unit 1432 can be thin according to first
It adjusts numerical value corresponding to parameter P12 and selects one of them first fine tuning output signal in all first fine tuning output signals
Output.
In some embodiments, the first signal behavior unit 1432 can be with multiplexer (Multiplexer, MUX) Lai Shixian.
First signal generation unit 1433 has two input terminals, wherein the input terminal electricity of the first signal generation unit 1433
Property be connected to the output end of first the first sampling unit 1431a, and receive from first the first sampling unit 1431a the
One the first fine tuning output signal Vf11, and another input terminal of the first signal generation unit 1433 is then electrically connected to the first letter
Number selecting unit 1432, and receive by first the first fine tuning output signal of the first signal behavior unit 1432 selection output
Vf11.Therefore, the first signal generation unit 1433 can according to first the first fine tuning output signal Vf11 with selected first
Fine tuning output signal generates the first control signal Vc1 after fine tuning.
Fig. 5 is the waveform schematic diagram of an embodiment of the first fine tuning output signal and first control signal in Fig. 2.Please
Collocation is refering to Fig. 2 to Fig. 5, and below by taking N is equal to 7 as an example, in one embodiment of this invention, the frequency of clock signal clk can be
40 megahertzs (MHz), the i.e. period of clock signal clk substantially 25 nanoseconds (nS), and the first predetermined period parameter P1 can be 12
The parameter of bit, such as: (111111110001)2.Wherein, preceding 9 bits are the first coarse adjustment in the first predetermined period parameter P1
Parameter P11, and last 3 bit is the first fine tuning parameter P12 in the first predetermined period parameter P1.
Therefore, the first signal generation unit 1411 can be loaded into the first coarse adjustment parameter P11, and the frequency based on clock signal clk
Rate and counted according to the first coarse adjustment parameter P11, with generate have corresponding to the first coarse adjustment parameter P11 the first coarse adjustment export
Signal Voc1.Since the first coarse adjustment parameter P11 is (111111111) at this time2, i.e. the numerical value of the first coarse adjustment parameter P11 is 512,
Therefore the width of the responsibility cycle of the first coarse tuned output signal Voc1 be approximately equal to 512 multiplied by clock signal clk period, i.e.,
The width of the responsibility cycle of one coarse tuned output signal Voc substantially 12.8 microseconds (μ S).In addition, delay mould group 142 can basis
Clock signal clk generate seven postpones signal Vd1~Vd7, and clock signal clk, postpones signal Vd1~Vd7 sequentially two-by-two it
Between there is the second time difference t2, and the second time difference t2 substantially period of clock signal clk divided by 8, that is, at this time second
Time difference t2 substantially 3.125 nanoseconds (nS).
Take second place, first the first sampling unit 1431a in the first output mould group 143 can be according to clock signal clk to the
One coarse tuned output signal Voc1 is sampled and is generated first the first fine tuning output signal Vf11, and in the first output mould group 143
Second the first sampling unit 1431b to the 8th the first sampling unit 1431h is then respectively according to corresponding postpones signal to preceding
First fine tuning output signal sampling caused by one the first sampling unit, with generate the first fine tuning output signal Vf12~
Vf18, as shown in figure 5, at this point, also there is the second time difference t2, and the second time difference t2 between every one first fine tuning output signal
Substantially 3.125 nanoseconds (nS).
It connects, the first signal behavior unit 1432 can be loaded into the first fine tuning parameter P12, and according to the first fine tuning parameter P12
Numerical value choose the output of corresponding first fine tuning output signal.Since the first fine tuning parameter P12 is (001) at this time2, i.e., first is thin
The numerical value of parameter P12 is adjusted at this time to be 1 and correspond to second the first fine tuning output signal Vf12, therefore the first signal behavior unit
1432 can export corresponding second the first fine tuning output signal Vf12 to first according to the numerical value of the first fine tuning parameter P12
Signal generation unit 1433.And the first signal generation unit 1433 can according to first the first fine tuning output signal Vf11 and
Second the first fine tuning output signal Vf12 generates first control signal Vc1, and the responsibility cycle of first control signal Vc1 at this time
Width correspond to the first predetermined period parameter P1.In this, the width of the responsibility cycle of first control signal Vc is approximately equal to
12.8 microseconds (μ S) add 3.125 nanoseconds (nS), i.e. 12.803125 microseconds (μ S).
In some embodiments, the first signal generation unit 1433 above-mentioned can be or lock (OR gate), by first
First fine tuning output signal is synthesized with the first fine tuning output signal selected that the first signal behavior unit 1432 is exported
First control signal Vc1.
Second output mould group 144 can be used to second thick output signal according to caused by second signal generation unit 1413
Voc2, clock signal clk, postpones signal Vd1~Vd7 and the second fine tuning parameter P22 generate required second control signal
Vc2.In the present embodiment, the second output mould group 144 may include N+1 the second sampling units, second signal selecting unit 1442
And second signal generates unit 1443.Wherein, the second sampling unit is substantially the same in the first sampling unit, second signal choosing
Unit 1442 is selected to be substantially the same in the first signal behavior unit 1432, and second signal generate unit 1443 be substantially the same in
First signal generation unit 1433.
Each second sampling unit is respectively provided with an input terminal D, clock pulse end CK and output end Q.Wherein, first second sampling
The input terminal D of unit 1441a is electrically connected to second signal and generates unit 1413, generates unit from second signal to receive
1413 the second coarse tuned output signal Voc2, the clock pulse end CK of first the second sampling unit 1441a is electrically connected to time clock source,
To receive the clock signal clk from time clock source, and first the second sampling unit 1441a can be according to the second coarse tuned output signal
Voc2 and clock signal clk generates first the second fine tuning output signal Vf21;And the input terminal D of the second sampling unit of m-th
It is electrically connected to the output end Q of M-1 the second sampling units, it is thin to receive second from M-1 the second sampling units
Output signal is adjusted, the clock pulse end CK of the second sampling unit of m-th is electrically connected to the M-1 delay-level in delay mould group 142
Output end, to receive the postpones signal from the M-1 delay-level, and M-1 the second sampling units can be according to M-1 the
Two fine tuning output signals and the M-1 postpones signal generate the second fine tuning of m-th output signal.In this, aforementioned M can for comprising
All positive integers greater than 1 and less than or equal to N.
Hereinafter, being to be illustrated so that N is equal to 7 as an example, wherein M includes all positive integers greater than 1 and less than or equal to 7.
Therefore, in an embodiment of the present invention, the second output mould group 144 may include eight second sampling unit 1441a~1441h, and
It can produce eight second fine tuning output signal Vf21~Vf28 altogether, however the present invention is not limited thereto, the second sampling unit
Quantity end is depending on design requirement, and the quantity of the second sampling unit might not be equal to the quantity of the first sampling unit.
In this, first the second frequency of the sampling unit 1441a based on clock signal clk is to the second coarse tuned output signal
Voc2 sampling, and generate first the second fine tuning output signal Vf21;Second the second sampling unit 1441b is based on first and prolongs
The frequency of slow signal Vd1 samples first the second fine tuning output signal Vf21, and generates second the second fine tuning output signal
Vf22;The second frequency of the sampling unit 1441c based on second postpones signal Vd2 of third is to second the second fine tuning output letter
Number Vf22 sampling, and generate the second fine tuning output signal Vf23 of third;4th the second sampling unit 1441d is based on third
The frequency of postpones signal Vd3 generates the 4th the second fine tuning output letter to third the second fine tuning output signal Vf23 sampling
Number Vf24;Sequentially class is pushed into the 8th the second sampling unit 1441f according to this.
In this, second the second sampling unit 1441b is based between first postpones signal Vd1 and clock signal clk
Two time difference t2, second the second fine tuning output signal Vf22 generated is also between first the second fine tuning output signal Vf21
With the second time difference t2;The second sampling unit 1441c of third is based on second postpones signal Vd2 and first postpones signal
The second time difference t2 between Vd1, the second fine tuning output signal Vf23 of the third generated are also exported with second the second fine tuning
There is the second time difference t2 between signal Vf22, sequentially analogized with this.
In addition, to be generally equal to the second coarse adjustment defeated for the waveform of all second fine tuning output signal Vf21~Vf28 above-mentioned
The waveform of signal Voc2 out, and the responsibility cycle of each second fine tuning output signal Vf21~Vf28 and the second coarse tuned output signal
The responsibility cycle of Voc2 is generally equal and can be 50%.
In some embodiments, each second sampling unit in the second output mould group 144 can be realized with D-type flip-flop.
Second signal selecting unit 1442 has control terminal and input terminal, the wherein control of second signal selecting unit 1442
End is electrically connected to the processing unit 131 of detection circuit 130, and receives the second fine tuning parameter P22 from processing unit 131,
And the input terminal of second signal selecting unit 1442 is electrically connected to the output end Q of N+1 the second sampling units, and receives and come from
All second fine tuning output signals of N+1 the second sampling units.Therefore, second signal selecting unit 1442 can be thin according to second
It adjusts numerical value corresponding to parameter P22 and selects one of them second fine tuning output signal in all second fine tuning output signals
Output.
In some embodiments, second signal selecting unit 1442 can be with multiplexer (Multiplexer, MUX) Lai Shixian.
Second signal, which generates unit 1443, has two input terminals, and wherein second signal generates the input terminal electricity of unit 1443
Property be connected to the output end of first the second sampling unit 1441a, and receive from first the second sampling unit 1441a the
One the second fine tuning output signal Vf21, and another input terminal that second signal generates unit 1443 is then electrically connected to the second letter
Number selecting unit 1442, and receive by the second fine tuning output signal of the selection output of second signal selecting unit 1442.Therefore,
Binary signal generates unit 1443 can be according to first the second fine tuning output signal Vf21 and the second fine tuning output signal selected
Second control signal Vc2 after generating fine tuning.
Fig. 6 is the waveform schematic diagram of an embodiment of the second fine tuning output signal and second control signal in Fig. 2.Please
Collocation is refering to Fig. 2 to Fig. 6, and in one embodiment of this invention, the frequency of clock signal clk can be 40 megahertzs (MHz), i.e. clock pulse
The period of signal clk substantially 25 nanoseconds (nS), and the second predetermined period parameter P2 can be the parameter of 12 bits, such as:
(111111111011)2.Wherein, preceding 9 bits are the second coarse adjustment parameter P21 in the second predetermined period parameter P2, and second is pre-
If last 3 bit is the second fine tuning parameter P22 in cycle parameter P2.
Therefore, second signal generates unit 1413 after receiving the trigger signal Vt from trigger unit 1412,
Be loaded into the second coarse adjustment parameter P21, and the frequency based on clock signal clk and counted according to the second coarse adjustment parameter P21, to produce
Raw the second coarse tuned output signal Voc2 having corresponding to the second coarse adjustment parameter P21.Since the second coarse adjustment parameter P21 is at this time
(111111111)2, i.e. the numerical value of the second coarse adjustment parameter P21 is 512, therefore the responsibility cycle of the second coarse tuned output signal Voc2
Width be approximately equal to 512 multiplied by clock signal clk period, i.e. the width of the responsibility cycle of the second coarse tuned output signal Voc
Substantially 12.8 microseconds (μ S).In addition, delay mould group 142 can according to clock signal clk generate seven postpones signal Vd1~
Vd7, and clock signal clk, postpones signal Vd1~Vd7 sequentially have the second time difference t2, and the second time difference t2 between any two
The substantially period of clock signal clk is divided by 8, that is, the second time difference t2 substantially 3.125 nanoseconds (nS) at this time.
Take second place, first the second sampling unit 1441a in the second output mould group 144 can be according to clock signal clk to the
Two coarse tuned output signal Voc2 are sampled and are generated first the second fine tuning output signal Vf21, and in the second output mould group 144
Second the second sampling unit 1441b to the 8th the second sampling unit 1441h is then respectively according to corresponding postpones signal to preceding
Second fine tuning output signal sampling caused by one the second sampling unit, with generate the second fine tuning output signal Vf22~
Vf28, as shown in fig. 6, at this point, also there is the second time difference t2, and the second time difference t2 between every one second fine tuning output signal
Substantially 3.125 nanoseconds (nS).
It connects, second signal selecting unit 1442 can be loaded into the second fine tuning parameter P22, and according to the second fine tuning parameter P22
Numerical value choose the output of corresponding second fine tuning output signal.Since the second fine tuning parameter P22 is (011) at this time2, i.e., second is thin
The numerical value of parameter P12 is adjusted at this time to be 3 and correspond to the 4th the second fine tuning output signal Vf24, therefore second signal selecting unit
1442 can export corresponding 4th the second fine tuning output signal Vf24 to second according to the numerical value of the second fine tuning parameter P22
Signal generation unit 1443.And second signal generate unit 1443 can according to first the second fine tuning output signal Vf21 and
4th the second fine tuning output signal Vf24 generates second control signal Vc2, and the responsibility cycle of second control signal Vc2 at this time
Width correspond to the second predetermined period parameter P2.In this, the width of the responsibility cycle of second control signal Vc is approximately equal to
12.8 microseconds (μ S) add 9.375 nanoseconds (that is, 3.375*3), i.e. 12.809375 microseconds (μ S).
Moreover, it is assumed that the pre-set delay parameter P3 of the present embodiment is (011)2, i.e., the numerical value of pre-set delay parameter P3 is at this time
It is 3, then is just generated after the period that the second coarse tuned output signal Voc2 above-mentioned is delayed by 3 arteries and veins signal clk, therefore the second coarse adjustment
First time poor t1 between output signal Voc2 and the first coarse tuned output signal Voc1 can be 75 nanoseconds (nS), and the second control is believed
Also there is number between Vc2 and first control signal Vc1 poor t1 (i.e. 75 nanoseconds) at the first time.
In some embodiments, second signal above-mentioned, which generates unit 1443, can be or lock (OR gate), by first
Second fine tuning output signal is synthesized with the second fine tuning output signal selected that second signal selecting unit 1442 is exported
Second control signal Vc2.
Fig. 7 is the flow diagram of the wireless power transmission method of one embodiment of the invention.Please refer to Fig. 1 to Fig. 7, the present invention one
The wireless power transmission method of embodiment includes the responsibility of the responsibility cycle and second control signal Vc2 according to first control signal Vc1
Input signal Vi is converted to modulating signal Vm (step S10), emits electricity according to modulating signal Vm using resonance circuit 120 by the period
Source signal Vp (step S20), corresponding first predetermined period parameter P1, the are generated according to the power supply information Dp of resonance circuit 120
Two predetermined period parameter P2 and pre-set delay parameter P3 (step S30), according to clock signal clk and the first predetermined period parameter P1
It generates first control signal Vc1 (step S40), and according to clock signal clk, pre-set delay parameter P3 and the second predetermined period
Parameter P2 generates second control signal Vc2 (step S50).
In step slo, the power-switching circuit 110 of wireless power transmission device 100 can correspond to first control signal Vc1's
The responsibility cycle actuation of responsibility cycle and second control signal Vc2.Therefore, power-switching circuit 110 can be based on the first control letter
The width size of the responsibility cycle of the width size and second control signal Vc2 of the responsibility cycle of number Vc1 and by input signal Vi
Corresponding conversion is modulating signal Vm.In this, power-switching circuit 110 can be converter of semi-bridge type.
In step S20, wireless power transmission device 100 is generated and transmitted by through resonance circuit 120 according to modulating signal Vm
Corresponding power supply signal Vp out.In this, resonance circuit 120 may include resonance coil 121 and resonant capacitance 122.
In step s 30, the detection circuit 130 of wireless power transmission device 100 can be according to the power supply information in resonance circuit 120
Dp generates corresponding first predetermined period parameter P1, the second predetermined period parameter P2 and pre-set delay parameter P3.In this, power supply is provided
Interrogating Dp can be resonance circuit 120 in information such as the DC voltages, DC current or temperature of node N1, and detection circuit 130 is produced
Raw the first predetermined period parameter P1, the second predetermined period parameter P2 and pre-set delay parameter P3 can be used to adjust control circuit
The responsibility cycle of first control signal Vc1 and second control signal Vc2 caused by 140.
In step s 40, control circuit 140 can be according to clock signal clk and the first predetermined period parameter P1 to generate
The first control signal Vc1 needed, and the responsibility cycle of first control signal Vc1 can correspond to the number of the first predetermined period parameter P1
Value.In this, the first predetermined period parameter P1 includes the first coarse adjustment parameter P11 and the first fine tuning parameter P12, wherein the first coarse adjustment
The width of responsibility cycle of the parameter P11 to adjust first control signal Vc1 roughly, and the first fine tuning parameter P12 is to finely tune
The width of the responsibility cycle of whole first control signal Vc1, to improve the precision of first control signal Vc1.
In one embodiment of this invention, step S40 is comprising may include according to clock signal clk and the first coarse adjustment parameter
P11 generates the first coarse tuned output signal Voc1 (step S41), N number of postpones signal (step S42) is generated according to clock signal clk,
First the first fine tuning output signal (step S43), basis are generated according to clock signal clk and the first coarse tuned output signal Voc1
The M-1 postpones signal and M-1 the first fine tuning output signals generate m-th the first fine tuning output signal (step S44), according to
It is selected one of these the first fine tuning output signals (step S45) according to the first fine tuning parameter P12, and according to first
One fine tuning output signal generates first control signal Voc1 (step S46) with the first fine tuning output signal selected.
In step S41, the first signal generation unit 1411 that control circuit 140 can pass through signal generator 141 is based on
The frequency of clock signal clk and generate the first coarse tuned output signal Voc1 according to the first coarse adjustment parameter P11, wherein the first coarse adjustment is defeated
The responsibility cycle of signal Voc1 corresponds to the first coarse adjustment parameter P11 out.In the present embodiment, the first signal generation unit 1411 can
For counter.In this, the period of the first coarse tuned output signal Voc1 substantially the first coarse adjustment parameter P1 and clock signal clk
Twice of product of period, and the responsibility cycle of the first coarse tuned output signal Voc1 is substantially 50%.
In step S42, the delay mould group 142 of control circuit 140 can sequentially generate N number of prolong according to clock signal clk
Slow signal, wherein N is the positive integer more than or equal to 1.In the present embodiment, delay mould group 142 can for by N number of delay-level sequentially
Delay line made of concatenation, and N number of postpones signal sequentially has the second time difference t2 between any two.In this, the second time difference t2
It can be the period of clock signal clk divided by (N+1).In one embodiment, the value of N can be 7.
In step S43, first the first sampling unit 1431a in the first output mould group 143 of control circuit 140 can
First the first fine tuning output signal Vf11 is generated according to clock signal clk and the first coarse tuned output signal Voc1.
In step S44, the first sampling unit of m-th in the first output mould group 143 of control circuit 140 can be according to the
M-1 postpones signal and M-1 the first fine tuning output signals generate the first fine tuning of m-th output signals, wherein M can for comprising
All positive integers greater than 1 and less than or equal to N.In this, the responsibility cycle of all first fine tuning output signals is generally with first
The responsibility cycle of coarse tuned output signal Voc1 is equal.
In step S45, the first signal behavior unit 1432 in the first output mould group 143 of control circuit 140 can be according to
An output is selected in these first fine tuning output signals according to the numerical value of the first fine tuning parameter P12.In this, the first signal behavior
Unit 1432 can be multiplexer.
In step S46, the first signal output unit 1433 in the first output mould group 143 of control circuit 140 can root
First control signal Vc1 is generated with the first fine tuning output signal selected according to first the first fine tuning output signal Vf11, and
The responsibility cycle of first control signal Vc1 corresponds to the first predetermined period parameter P1.
In step s 50, control circuit 140 more can be according to clock signal clk, pre-set delay parameter P3 and second default week
Period parameters P2 generates required second control signal Vc2.Wherein, the numerical value of pre-set delay parameter P3 is K, second control signal
It is differed between Vc2 and first control signal Vc1 the period of K clock signal clk, and the responsibility cycle of second control signal Vc2
The numerical value of the second predetermined period parameter P2 can be corresponded to.In this, the second predetermined period parameter P2 include the second coarse adjustment parameter P21 with
And the second fine tuning parameter P22, wherein responsibility cycle of the second coarse adjustment parameter P21 to adjust second control signal Vc2 roughly
Width, and width of the second fine tuning parameter P22 to the responsibility cycle of micro-adjustment second control signal Vc2, to improve the second control
The precision of signal Vc2 processed.
Fig. 8 is the flow diagram of an embodiment of step S50 in Fig. 7.Fig. 2 to Fig. 8 is please referred to, it is real of the invention one
It applies in example, step S50 includes to generate trigger signal Vt (step S51), basis according to clock signal clk and pre-set delay parameter P3
Trigger signal Vt, clock signal clk and the second coarse adjustment parameter P21 generate the second coarse tuned output signal Voc2 (step S52), basis
Clock signal clk generates N number of postpones signal (step S53), is generated according to clock signal clk and the second coarse tuned output signal Voc2
First the second fine tuning output signal Vf21 (step S54), it is exported according to the M-1 postpones signal and M-1 the second fine tunings
Signal generates m-th the second fine tuning output signal (step S55), selects these second fine tunings defeated according to the second fine tuning parameter P22
One of signal (step S56) out, and according to first the second fine tuning output signal Vf21 with selected it is second thin
Output signal is adjusted to generate second control signal Vc2 (step S57).
However, in another embodiment of the invention, since step S53 and aforementioned step S42 are substantially the same, in this
It can then omit, therefore step S50 can only include step S51, step S52, step S54, step S55, step S56 and step S57.
In step s 51, the trigger unit 1412 that control circuit 140 can pass through signal generator 141 is based on clock signal
The frequency of clk and according to pre-set delay parameter P3 generate trigger signal Vt output, with trigger second signal generate unit 1413 make
It is dynamic.
In step S52, second signal generates unit 1413 in receiving trigger signal Vt after activating, and second signal produces
Raw unit 1413 can the frequency based on clock signal clk and generate the second coarse tuned output signal according to the second coarse adjustment parameter P21
Voc2, wherein the responsibility cycle of the second coarse tuned output signal Voc2 corresponds to the second coarse adjustment parameter P21.In the present embodiment,
It can be counter that binary signal, which generates unit 1413,.In this, substantially the second coarse adjustment of the period of the second coarse tuned output signal Voc2
Twice of the product in the period of parameter P21 and clock signal clk, and the responsibility cycle of the second coarse tuned output signal Voc2 is substantially
50%.
In step S54, control circuit 140 is through first the second sampling unit 1441 in the second output mould group 144
The second coarse tuned output signal Voc2 is sampled according to clock signal clk and generates first the second fine tuning output signal Vf21.
In step S55, control circuit 140 can pass through the second sampling unit of m-th and be based on the M-1 postpones signal sampling
M-1 the second fine tuning output signals and generate m-th the second fine tuning output signal, wherein M can be for comprising being greater than 1 and being less than etc.
In all positive integers of N.In this, the responsibility cycle of all second fine tuning output signals generally with the second coarse tuned output signal
The responsibility cycle of Voc2 is equal.
In step S56, control circuit 140 can pass through the second signal selecting unit 1442 in the second output mould group 144
An output is selected in these second fine tuning output signals according to the second fine tuning parameter P22.In this, second signal selecting unit
1442 can be multiplexer.
In step S57, control circuit 140 can pass through the second signal output unit 1443 in the second output mould group 144
Second control signal Vc2 is generated with the second fine tuning output signal selected according to first the second fine tuning output signal Vf21,
And the responsibility cycle of first control signal Vc2 corresponds to the second predetermined period parameter P2.
In conclusion wireless power transmission device according to an embodiment of the invention and its method, control circuit are only needed using low
The clock signal of frequency, clock signal or other additional phase-locked loops (phase locked without using high frequency
Loop, PLL), the circuits of the complicated architectures such as delay-locked loop (delay locked loop, DLL), that is, can produce has height
Two control signals of precision and mutual dislocation regulate and control power supply signal caused by wireless power transmission device, and make wireless power transmission
The transmission energy that device is sent to electronic device can equal the cost consumption for accurately exporting, and reducing wireless power transmission device.
Technology contents of the invention are disclosed with preferred embodiment as above-mentioned, and however, it is not to limit the invention, any
Be familiar with this those skilled in the art, do not depart from spirit of the invention do it is a little change and retouch, should all be covered by scope of the invention
It is interior, therefore protection scope of the present invention should be defined by the scope of the appended claims.