CN106453017A - A kind of MII interface and GPMC interface data communication system and communication method - Google Patents

Abstract

The invention relates to the technical field of communication, and provides a data communication system and a data communication method for an MII interface and a GPMC interface, wherein the system comprises an MII interface data receiving module, an MII interface data sending module, an RAM module, a GPMC interface communication module and a clock management module: the MII interface data receiving module merges the received communication data into 8-byte bit width data and stores the data into the RAM module; the GPMC interface communication module stores the received communication data into a data packet of the RAM module, and controls to send the data packet to be sent to the DM3730 chip through a GPMC protocol; the MII interface data sending module splits 8-byte bit width data in a data packet to be sent into two 4-byte bit width data, and sends the two 4-byte bit width data to an MII interface of the PHY chip through an MII interface protocol, so that communication between the DM3730 chip and the Ethernet PHY chip is realized.

Description

A kind of MII interface and GPMC interface data communication system and communication method

technical field

The invention belongs to the technical field of communication, and in particular relates to a data communication system and a communication method between an MII interface and a GPMC interface.

Background technique

Media independent interface or media independent interface (Media Independent Interface, MII) is an Ethernet industry standard defined by IEEE-802.3. This interface includes two independent channels of the transmitter and receiver, and each channel has its own data and clock. and control signals, the MII interface is used for communication between the Ethernet PHY chip and the Ethernet MAC chip.

Currently, TI's DM3730 chip uses a General-Purpose Memory Controller (GPMC) interface for high-speed communication with external storage devices. Since it does not have a MII interface, the DM3730 chip cannot directly communicate with an Ethernet PHY chip.

Contents of the invention

The purpose of the present invention is to provide a MII interface and GPMC interface data communication system, aiming to solve the problem that the DM3730 chip cannot directly communicate with the Ethernet PHY chip in the prior art.

The present invention is achieved in that a kind of MII interface and GPMC interface data communication system, described system comprises MII interface data receiving module, MII interface data sending module, RAM module, GPMC interface communication module and clock management module:

The MII interface data receiving module is connected with the Ethernet PHY chip and the RAM module respectively, for receiving communication data from the MII interface of the Ethernet PHY chip, and merging the communication data into 8-byte bit-width data stored in the data packet of the RAM module;

Described GPMC interface communication module is connected with DM3730 chip, described RAM module respectively, is used for receiving communication data from described DM3730 chip, and communication data is stored in the data packet of described RAM module, simultaneously, in described clock Under the control of the management module, the control reads the data packet to be sent from the RAM module, and sends the data packet to be sent to the DM3730 chip by the GPMC protocol;

The MII interface data sending module is connected with the RAM module and the Ethernet PHY chip respectively, and is used to read the data packet to be sent from the RAM module, and the 8-byte bit width data in the data packet to be sent split into two 4-byte bit-width data, and send the 4-byte bit-width data to the MII interface of the PHY chip through the MII interface protocol.

As an improved solution, the RAM module is an embedded dual-port RAM module.

As an improved solution, the MII interface data receiving module, MII interface data sending module, RAM module, GPMC interface communication module and clock management module are built in the programmable controller.

Another object of the present invention is to provide a kind of communication method based on MII interface and GPMC interface data communication system, described method comprises the steps:

The MII interface data receiving module receives communication data from the MII interface of the Ethernet PHY chip, and merges the communication data into 8-byte bit-width data, and stores them in the data packet of the RAM module;

Under the control of the clock management module, the GPMC interface communication module controls to read the data packets to be sent from the RAM module, and sends the data packets to be sent to the DM3730 chip through the GPMC protocol.

As an improved solution, the MII interface data receiving module also includes the following steps before the step of receiving communication data from the MII interface of the Ethernet PHY chip:

The MII interface data receiving module receives the data frame transmission start flag sent by the MII interface of the Ethernet PHY chip.

As an improved solution, the method also includes the following steps:

Establish communication connections between the MII interface data receiving module and the MII interface of the Ethernet PHY chip, and between the GPMC interface communication module and the DM3730 chip in advance.

As an improved solution, the RAM module is an embedded dual-port RAM module.

Another object of the present invention is to provide a kind of communication method based on MII interface and GPMC interface data communication system, described method comprises the steps:

The GPMC interface communication module receives communication data from the DM3730 chip, and stores the communication data into the data packet of the RAM module;

The MII interface data sending module reads the data packet to be sent from the RAM module, splits the 8-byte bit-width data in the data packet to be sent into two 4-byte bit-width data, and converts the 4-byte bit-width data through the MII interface protocol. The byte-wide data is sent to the MII interface of the PHY chip.

As an improved solution, the method also includes the following steps:

Establish communication connections between the MII interface data receiving module and the MII interface of the Ethernet PHY chip, and between the GPMC interface communication module and the DM3730 chip in advance.

As an improved solution, the RAM module is an embedded dual-port RAM module.

In the embodiment of the present invention, MII interface and GPMC interface data communication system comprise MII interface data receiving module, MII interface data sending module, RAM module, GPMC interface communication module and clock management module: MII interface data receiving module from described Ethernet The MII interface of the PHY chip receives the communication data, and combines the communication data into 8-byte bit-width data and stores them in the data packet of the RAM module; the GPMC interface communication module receives the communication data from the DM3730 chip, and stores the communication data in the In the data packet of the RAM module, under the control of the clock management module, the control reads the data packet to be sent from the RAM module, and sends the data packet to be sent to the DM3730 chip by the GPMC protocol; the MII interface data transmission module Read the data packet to be sent from the RAM module, split the 8-byte bit-width data in the data packet to be sent into two 4-byte bit-width data, and pass the 4-byte bit-width data through the MII interface protocol The bit width data is sent to the MII interface of the PHY chip to realize the communication between the DM3730 chip and the Ethernet PHY chip.

Since the RAM module is an embedded dual-port RAM module, packet loss during continuous data packet transmission is prevented, and data transmission efficiency is also improved.

In the embodiment of the present invention, the MII interface data receiving module receives the communication data from the MII interface of the Ethernet PHY chip, and the communication data is merged into 8-byte bit width data, which is stored in the data packet of the RAM module; Under the control of the module, the GPMC interface communication module controls to read the data packets to be sent from the RAM module, and sends the data packets to be sent to the DM3730 chip through the GPMC protocol to realize the data transmission from the Ethernet PHY chip to the DM3730 chip.

In the embodiment of the present invention, the GPMC interface communication module receives the communication data from the DM3730 chip, and stores the communication data in the data packet of the RAM module; the MII interface data sending module reads the data packet to be sent from the RAM module, and sends the data packet to be sent The 8-byte bit-width data in the data packet is split into two 4-byte bit-width data, and the 4-byte bit-width data is sent to the MII interface of the PHY chip through the MII interface protocol to realize the DM3730 chip-to-Ethernet Network PHY chip DM3730 chip data transmission.

Description of drawings

Fig. 1 is the structural representation of MII interface provided by the invention and GPMC interface data communication system;

Fig. 2 and Fig. 3 are respectively the implementation flowchart of the MII interface and GPMC interface data communication method provided by the present invention.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

Fig. 1 shows the structural representation of MII interface and GPMC interface data communication system that the present invention provides, for the convenience of explanation, only provided the relevant part of the present invention in the figure.

MII interface and GPMC interface data communication system includes MII interface data receiving module, MII interface data sending module, RAM module, GPMC interface communication module and clock management module:

The MII interface data receiving module is connected to the Ethernet PHY chip and the RAM module respectively, and is used to receive communication data from the MII interface of the Ethernet PHY chip, and merge the communication data into 8-byte bit-width data and store it in the data of the RAM module in the bag;

The GPMC interface communication module is connected with the DM3730 chip and the RAM module respectively, and is used to receive communication data from the DM3730 chip and store the communication data in the data packet of the RAM module. At the same time, under the control of the clock management module, control the slave RAM module Read the data packet to be sent in the computer, and send the data packet to be sent to the DM3730 chip through the GPMC protocol;

The MII interface data sending module is connected to the RAM module and the Ethernet PHY chip respectively, and is used to read the data packet to be sent from the RAM module, and split the 8-byte wide data in the data packet to be sent into two 4 Bytes of bit-width data, and send 4-byte bit-width data to the MII interface of the PHY chip through the MII interface protocol.

Of course, in this embodiment, other functional modules are also included, such as packet loss self-check, calculation of data packet byte quantity, calculation and rules of data storage address, etc., which will not be repeated here, but are not intended to limit the present invention.

Wherein, the above-mentioned RAM module is an embedded dual-port RAM module, which stores at most 16 sending data packets and 16 receiving data packets in the embedded dual-port RAM module, and the setting of the embedded dual-port RAM module avoids continuous transmission of data packets The problem of packet loss in the process is also improved, and the transmission efficiency of the entire MII interface and GPMC interface data communication system is also improved.

In the embodiment of the present invention, the MII interface data receiving module, the MII interface data sending module, the RAM module, the GPMC interface communication module and the clock management module are built in the programmable controller, that is, the MII interface and the GPMC interface data communication system are built-in A system circuit in the programmable controller will not be repeated here.

Fig. 2 has shown the implementation flowchart of the MII interface that the embodiment of the present invention one provides and GPMC interface data communication method, and it specifically comprises the following steps:

In step S101, the MII interface data receiving module receives communication data from the MII interface of the Ethernet PHY chip, and combines the communication data into 8-byte bit-width data, and stores them in the data packet of the RAM module.

In step S102, under the control of the clock management module, the GPMC interface communication module controls to read the data packet to be sent from the RAM module, and sends the data packet to be sent to the DM3730 chip through the GPMC protocol.

Wherein, in the above step S101, the MII interface data receiving module also includes the following steps before the step of receiving communication data from the MII interface of the Ethernet PHY chip:

The MII interface data receiving module receives the data frame transmission start flag sent by the MII interface of the Ethernet PHY chip.

In the embodiment of the present invention, communication connections are respectively established between the MII interface data receiving module and the MII interface of the Ethernet PHY chip, and between the GPMC interface communication module and the DM3730 chip.

In this embodiment, the implementation process of the data communication method between the MII interface and the GPMC interface shown in FIG. 2 realizes the data transmission from the Ethernet PHY chip to the DM3730 chip.

Fig. 3 has shown the implementation flowchart of the MII interface that the embodiment of the present invention two provides and GPMC interface data communication method, and it specifically comprises the following steps:

In step S201, the GPMC interface communication module receives communication data from the DM3730 chip, and stores the communication data into the data packet of the RAM module.

In step S202, the MII interface data sending module reads the data packet to be sent from the RAM module, splits the 8-byte bit-width data in the data packet to be sent into two 4-byte bit-width data, and passes The MII interface protocol sends 4-byte bit-width data to the MII interface of the PHY chip.

In the embodiment of the present invention, communication connections are respectively established between the MII interface data receiving module and the MII interface of the Ethernet PHY chip, and between the GPMC interface communication module and the DM3730 chip.

In this embodiment, the implementation flow of the data communication method between the MII interface and the GPMC interface shown in FIG. 3 realizes the data transmission from the DM3730 chip to the Ethernet PHY chip DM3730 chip.

In the embodiment of the present invention, MII interface and GPMC interface data communication system comprise MII interface data receiving module, MII interface data sending module, RAM module, GPMC interface communication module and clock management module: MII interface data receiving module is from Ethernet PHY chip The MII interface of the MII interface receives the communication data, and combines the communication data into 8-byte bit-width data and stores them in the data packet of the RAM module; the GPMC interface communication module receives the communication data from the DM3730 chip, and stores the communication data into the data of the RAM module In the packet, under the control of the clock management module, the control reads the data packet to be sent from the RAM module, and sends the data packet to be sent to the DM3730 chip through the GPMC protocol; the MII interface data sending module reads the data packet to be sent from the RAM module Data packet, split the 8-byte bit-width data in the data packet to be sent into two 4-byte bit-width data, and send the 4-byte bit-width data to the MII interface of the PHY chip through the MII interface protocol , to realize the communication between the DM3730 chip and the Ethernet PHY chip.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. within range.

Claims (10)

1. a kind of MII interface with GPMC interface data communication system it is characterised in that described system includes MII interface data connects Receive module, MII interface data sending module, RAM module, GPMC interface communication module and Clock management module：

Described MII interface data receiver module, is connected with ethernet PHY chip, described RAM module respectively, for from described with The MII interface communication data of too net PHY chip, and communication data is merged into described in bit wide data Cun Chudao of 8 bytes In the packet of RAM module；

Described GPMC interface communication module, is connected with DM3730 chip, described RAM module respectively, for from described DM3730 core Piece receives communication data, and communication data is stored in the packet of described RAM module, meanwhile, in described Clock management mould Under the control of block, control and read packet to be sent from described RAM module, and by GPMC agreement, packet to be sent is sent out Give described DM3730 chip；

Described MII interface data sending module, is connected with described RAM module, ethernet PHY chip, respectively for from described RAM Read packet to be sent in module, 8 byte bit wide data in packet to be sent are split as the bit wide of two 4 bytes Data, and by MII interface protocol, the bit wide data is activation of 4 bytes is given the MII interface of described PHY chip.

2. MII interface according to claim 1 and GPMC interface data communication system are it is characterised in that described RAM module For Embedded Double port RAM module.

3. MII interface according to claim 1 and GPMC interface data communication system are it is characterised in that described MII interface Data reception module, MII interface data sending module, RAM module, GPMC interface communication module and Clock management module are built-in In Programmable Logic Controller.

4. a kind of communication means based on the MII interface described in claim 1 and GPMC interface data communication system, its feature exists In methods described comprises the steps：

MII interface data receiver module is from the MII interface communication data of ethernet PHY chip, and communication data is merged For the bit wide data of 8 bytes, store in the packet of RAM module；

Under the control of Clock management module, packet to be sent is read in the control of GPMC interface communication module from RAM module, and Packet to be sent is sent to by DM3730 chip by GPMC agreement.

5. MII interface according to claim 4 and GPMC interface data communication means are it is characterised in that described MII interface Data reception module also comprised the steps before the step of the MII interface communication data of ethernet PHY chip：

The data frame transfer that described MII interface data receiver module receives the MII interface transmission of described ethernet PHY chip starts Mark.

6. MII interface according to claim 4 and GPMC interface data communication means it is characterised in that methods described also Comprise the steps：

In advance between described MII interface data receiver module and the MII interface of described ethernet PHY chip, GPMC interface lead to Communication connection is set up respectively between letter module and DM3730 chip.

7. MII interface according to claim 4 and GPMC interface data communication system are it is characterised in that described RAM module For Embedded Double port RAM module.

8. a kind of communication means based on the MII interface described in claim 1 and GPMC interface data communication system, its feature exists In methods described comprises the steps：

GPMC interface communication module receives communication data from DM3730 chip, and communication data is stored the data of RAM module Bao Zhong；

MII interface data sending module reads packet to be sent from RAM module, by 8 bytes in packet to be sent Bit wide data is split as the bit wide data of two 4 bytes, and passes through MII interface protocol by the bit wide data is activation of 4 bytes to PHY The MII interface of chip.

9. MII interface according to claim 8 and GPMC interface data communication means it is characterised in that methods described also Comprise the steps：

In advance between described MII interface data receiver module and the MII interface of described ethernet PHY chip, GPMC interface lead to Communication connection is set up respectively between letter module and DM3730 chip.

10. MII interface according to claim 1 and GPMC interface data communication system are it is characterised in that described RAM mould Block is Embedded Double port RAM module.