CN106449745B - Current-controllable electrostatic induction transistor based on channel buried layer - Google Patents
Current-controllable electrostatic induction transistor based on channel buried layer Download PDFInfo
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- CN106449745B CN106449745B CN201610847814.8A CN201610847814A CN106449745B CN 106449745 B CN106449745 B CN 106449745B CN 201610847814 A CN201610847814 A CN 201610847814A CN 106449745 B CN106449745 B CN 106449745B
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- 230000006698 induction Effects 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 claims abstract description 9
- 239000000463 material Substances 0.000 claims abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 8
- 108091006146 Channels Proteins 0.000 description 21
- 230000000694 effects Effects 0.000 description 10
- 230000033228 biological regulation Effects 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/7722—Field effect transistors using static field induced regions, e.g. SIT, PBT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
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- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention relates to a current-controllable electrostatic induction transistor (SIT) based on a channel buried layer, which comprises a drain electrode, a low-resistance monocrystalline substrate positioned above the drain electrode, a high-resistance epitaxial layer positioned above the low-resistance monocrystalline substrate, a buried layer positioned below the channel in the high-resistance epitaxial layer and a plurality of SIT units positioned in parallel connection with each other in the high-resistance epitaxial layer, and is characterized in that the buried layer is positioned below the channel by 0.3-0.7 um, and the doping concentration is 5 multiplied by 10 14 ～1×10 15 cm ‑3 The thickness of the buried layer is 0.4-0.6 um. The device can regulate and control the electrical parameters of the SIT by changing independent parameters under the condition of keeping the manufacturing parameters of structures, materials, processes and the like which are mutually influenced, so as to regulate and control the output characteristics of the SIT, thereby preparing the SIT with excellent performance.
Description
Technical Field
The invention relates to an electrostatic induction transistor, in particular to a current-controllable electrostatic induction transistor based on a channel buried layer.
Background
An electrostatic induction transistor (SIT) is an electrostatic induction device capable of operating under high frequency and high power conditions, and has a wide application prospect in the fields of electronic switches and the like. The micro-size effect of the SIT is very remarkable, the structure is extremely sensitive, and the relation between the current-voltage characteristic (I-V characteristic) and the electrical performance parameter of the SIT and the manufacturing parameters of the structure, the material, the process and the like is very complex and is related with each other. In the prior art, control of output characteristics such as SIT output current is mainly achieved by changing the ratio of channel length to channel width, channel doping concentration, and the like. However, changing a certain structural parameter affects other electrical characteristic parameters, which is easy to cause the problems of difficult control of manufacturing technology, unstable process, low yield and the like. Therefore, it is required to find a new method capable of adjusting and controlling the electrical parameters of the SIT by changing independent parameters while maintaining manufacturing parameters of structures, materials, processes, etc. that are affected each other, thereby enhancing the output characteristics of the SIT, preparing the SIT with excellent performance by a more stable manufacturing process, and improving the yield.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a method capable of regulating and controlling SIT output characteristics so as to obtain SIT meeting the requirements.
The invention relates to a current-controllable electrostatic induction transistor, which comprises a drain electrode, a low-resistance monocrystalline substrate positioned on the drain electrode, a high-resistance epitaxial layer positioned on the low-resistance monocrystalline substrate and a buried layer positioned below a channel in the high-resistance epitaxial layer, and is characterized in that the buried layer is positioned below the channel by 0.3-0.7 um, and the doping concentration is 5 multiplied by 10 14 ～1×10 15 cm -3 The thickness of the buried layer is 0.4-0.6 um. The thickness and concentration of the buried layer can be changed to regulate and control the output characteristics of SIT such as output current. The simulation by software shows that as the thickness of the buried layer increases, the output current of the device is continuously increased, but when the current is increased to a certain degree, the current saturation occurs and the current is not changed any more. With the continuous increase of the concentration of the buried layer, the output current of the device is gradually increased under the same bias, the corresponding on-resistance is reduced, and when the concentration is increased to a certain degree, the characteristic curves are overlapped and even deformed to a certain extent, so that the concentration is not excessively large. In the actual selection process, the doping concentration, the thickness and the difficulty of the device manufacturing process need to be comprehensively considered. The doping concentration of the buried layer is generally 5 multiplied by 10 14 ～1×10 15 cm -3 The thickness is selected to be 0.4-0.6 um.
Further, the buried layer is applicable to both the N-channel SIT and the P-channel SIT. The buried layer is manufactured below the channel, and the regulation of the drain voltage on the channel potential barrier is similarly improved from the drain electrode to the buried layer, so that the regulation of the drain voltage on the intrinsic gate potential passes through a part of drift region and acts on the saddle point more directly and more effectively, the drain control efficiency of the device is improved, the leakage current of the device is further increased, and the thickness of the drift region of the device is not changed. In addition, the device exhibits excellent breakdown characteristics while ensuring an increase in the output current and a decrease in on-resistance of the device. Furthermore, for P-channel SIT, the introduction of buried layers can compensate for the negative effects of lower mobility and thus lower current density caused by holes as carriers.
Further, the current-controllable electrostatic induction transistor of the invention adopts silicon slices as low-resistance monocrystalline substrate material of SIT, the thickness is 30-40 um, the doping concentration is 1 multiplied by 10 18 ～1×10 19 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the Growing a layer with the thickness of 20-26 um and the doping concentration of 5 multiplied by 10 on the substrate slice 12 ～1×10 13 cm -3 Is a micro-doped high-resistance epitaxial layer; manufacturing an active region of SIT on the high-resistance epitaxial layer, wherein the channel length of the active region is 2-3 um, and the doping concentration of the gate region is 1 multiplied by 10 18 ～1×10 19 cm -3 The doping concentration of the source region is also 1×10 18 ～1×10 19 cm -3 。
Further, the current-controllable electrostatic induction transistor is an electrostatic induction transistor with output characteristics which can be changed along with the position, doping concentration and thickness change of the buried layer.
The invention has the following technical effects:
buried layers with specific doping concentration and specific thickness are buried in proper positions of the SIT, so that the control efficiency of drain-source bias voltage on a channel barrier can be effectively improved, the output current and other output characteristics of the device are improved, and a new approach is developed for solving the problem of too small current caused by low mobility in a P-type channel. Under the condition that other parameters are the same, the output current of the P-channel SIT is equivalent to that of the N-channel SIT by introducing the buried layer, the output characteristics of the P-channel SIT and the N-channel SIT are symmetrical, and the P-channel SIT and the N-channel SIT can be used in a matched mode. And the thickness and the concentration of the buried layer can be controlled to regulate and control the output characteristics of SIT such as output current, thereby optimizing the output performance of SIT and preparing SIT meeting the use requirement.
Drawings
Fig. 1 is a schematic cross-sectional view of a current-controlled electrostatic induction transistor. In the figure: 1 is a drain electrode, 2 is a low-resistance monocrystalline substrate, 3 is a high-resistance epitaxial layer, 4 is a buried layer, 5 is a gate region, 6 is SiO 2 Layer 7 is the source region.
Fig. 2 is a graph showing the effect of buried layers of different concentrations on the I-V output characteristics of a P-channel SIT.
Fig. 3 is a graph showing the effect of buried layers of different thicknesses on the I-V output characteristics of a P-channel SIT.
Fig. 4 is a graph showing the effect of buried layers at different locations on the I-V output characteristics of a P-channel SIT.
Fig. 5 is an I-V characteristic diagram of an N-channel SIT with and without a buried layer.
Detailed Description
The drawings are illustrative embodiments of the invention and are described below with reference to the drawings.
Referring to fig. 1, the current-controllable electrostatic induction transistor of the invention comprises a drain electrode 1, a low-resistance monocrystalline substrate 2 positioned above the drain electrode, a high-resistance epitaxial layer 3 positioned above the low-resistance monocrystalline substrate, and a buried layer 4 positioned below a channel in the high-resistance epitaxial layer, and is characterized in that the buried layer 4 is positioned below the channel by 0.3-0.7 um, and the doping concentration is 5 multiplied by 10 14 ～1×10 15 cm -3 The thickness of the buried layer is 0.4-0.6 um.
The control capability of the thickness and doping concentration of the buried layer on the SIT output characteristics was analyzed separately with the other parameters kept unchanged. The process and results are as follows:
SIT structural parameter set point
| Parameters (parameters) | Numerical value | Unit (B) |
| Gate region doping concentration | 1.0e19 | cm -3 |
| Source region doping concentration | 1.0e19 | cm -3 |
| Doping concentration of epitaxial layer | 1.0e13 | cm -3 |
| Drain region doping concentration | 1.0e19 | cm -3 |
| Total cell width | 9.0 | mm |
| Total device thickness | 37.0 | mm |
| Half width of gate contact window | 0.75 | mm |
| Source contact window width | 1.5 | mm |
| Thickness of drain contact layer | 2.0 | mm |
| Junction depth of gate region | 1.0 | mm |
| Source junction depth | 3.0 | mm |
| Thickness of drain contact layer | 2.0 | mm |
For P-channel SIT, at concentration n=1×10 13 cm -3 A P-type buried layer with the thickness set to 0.5um is introduced at the position 0.5um below the channel in the epitaxial layer, and the concentration is respectively N=5x10 13 cm -3 、1×10 14 cm -3 、5×10 14 cm -3 、1×10 15 cm -3 、5×10 15 cm -3 、1×10 16 cm -3 And no buried layer, FIG. 2 shows the gate voltage V G Taking 1V, and leaking pressure V D At 0 to-200V, the effect of buried layers of different concentrations on the I-V output characteristics of the device. It can be found that the device output characteristics are substantially unchanged when the buried layer concentration is close to the epitaxial layer concentration; with the continuous increase of the concentration of the buried layer, the output current of the device is gradually increased under the same bias voltage, and the corresponding on-resistance is continuously reduced. However, when the concentration is increased to a certain extent, the characteristic curves are overlapped or even deformed to a certain extent, so that the concentration is not too large, and the concentration of the buried layer is generally 5 multiplied by 10 14 ～1×10 15 cm -3 。
At concentration n=1×10 13 cm -3 Is set to 1 x 10 by introducing doping concentration at 0.5um below the channel in the epitaxial layer of (a) 15 cm -3 The thickness of the P-type buried layer is respectively 0.5um, 1.0um, 1.5um and 2 um0um and 2.5um to obtain grid voltage V G Taking 1V, and leaking pressure V D The output characteristic curves at 0 to-200V are compared with the P-channel SIT characteristics without buried layer, and the results are shown in FIG. 3. From the figure, as the thickness of the buried layer increases, the output current of the device also increases continuously, and when the thickness of the buried layer is 0.5um, the output current is obviously larger than that of the device without the buried layer. However, as the thickness of the buried layer continues to increase, the output current increases to generate a current saturation phenomenon, the I-V characteristic curve starts to deform when the I-V characteristic curve appears on the image, and the deformation of the I-V characteristic curve of the SIT can seriously affect the performance of the device, so that the thickness of the buried layer is generally selected to be 0.4-0.6 um.
At concentration n=1×10 13 cm -3 Is set to 1 x 10 by introducing a doping concentration into the epitaxial layer 15 cm -3 A P-type buried layer with thickness of 0.5um, which is respectively positioned at 0.5um, 1.0um, 1.5um, 2.0um, 2.5um, 3.0um, 10um and 20um below the channel to obtain grid voltage V G Taking 1V, and leaking pressure V D The output characteristic curves at 0 to-200V were compared with the P-channel SIT characteristics without buried layer, and the results are shown in fig. 4. From the figure, it can be seen that the effect of the position of the buried layer on the device characteristics is much smaller than the doping concentration and thickness, i.e. the current output of the device does not increase much when the buried layer is at different positions of the drift region. In order to simplify the process flow, the buried layer is generally selected from 0.3-0.7 um below the channel.
In the first embodiment of the present invention, the output characteristics before and after adding the buried layer to the P-channel SIT were simulated, and the results as described above show that the introduction of the buried layer has a remarkable improving effect on the increase of the output current and the decrease of on-resistance of the P-channel SIT, and the larger the output current of SIT with the increase of the doping concentration and thickness of the buried layer. Because the buried layer is introduced below the channel, the regulation of the drain voltage on the channel potential barrier is similarly improved from the drain electrode to the position of the buried layer, so that the regulation of the drain voltage on the intrinsic gate potential passes over part of the drift region and acts on the saddle point more directly and more effectively, the drain control efficiency of the device is improved, the leakage current of the device is further increased, and the thickness of the drift region of the device is not changed. In addition, the device exhibits excellent breakdown characteristics while ensuring an increase in the output current and a decrease in on-resistance of the device.
The second embodiment of the present invention is substantially identical to the previous embodiment, which is a contention for N-channel SIT. The output characteristics before and after adding the buried layer to the N-channel SIT are simulated, and as shown in the figure 5, the input buried layer has obvious improvement effects on the increase of the output current of the N-channel SIT and the reduction of the on-resistance, and the rule is similar to that of the P-channel SIT.
The SIT of the invention can effectively improve the control efficiency of drain-source bias voltage on the channel barrier, thereby improving the output current and other output characteristics of the device. Under the same bias voltage, the output current of the device is continuously increased and the on-resistance is continuously reduced along with the increase of the doping concentration of the buried layer and the increase of the thickness of the buried layer. However, when the concentration is increased to a certain degree, the characteristic curves are overlapped and even deformed to a certain extent, so that the concentration is not excessively large. Likewise, when the thickness of the buried layer is increased to a certain extent, current saturation occurs when the thickness is further increased, and a certain superposition appears for the output characteristic on the image. Therefore, in the actual selection process, the doping concentration, the thickness and the difficulty of the device manufacturing process need to be comprehensively considered, and the SIT with the required specific output characteristics can be obtained by setting specific buried layer parameters. Typically, the buried layer is located at 0.3-0.7 um below the channel with a doping concentration of 5×10 14 ～1×10 15 cm -3 When the thickness is 0.4 to 0.6um, the SIT can obtain excellent output characteristics.
Claims (1)
1. A current controllable electrostatic induction transistor comprises a drain electrode, a low-resistance monocrystalline substrate positioned on the drain electrode, a high-resistance epitaxial layer positioned on the low-resistance monocrystalline substrate and a buried layer positioned below a channel in the high-resistance epitaxial layer, and is characterized in that the buried layer is positioned below the channel by 0.3-0.7 um, and the doping concentration is 5 multiplied by 10 14 ~1×10 15 cm -3 The buried layer has a thickness of 0.4-0.6 um and is ledThe buried layer is suitable for the P-channel SIT;
the buried layers are positioned below the four grid regions and are connected into a whole;
silicon slice is adopted as a low-resistance monocrystalline substrate material of SIT, the thickness is 30-40 um, and the doping concentration is 1 multiplied by 10 18 ~1×10 19 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the Growing a layer with the thickness of 20-26 um and the doping concentration of 5 multiplied by 10 on the substrate slice 12 ~1×10 13 cm -3 Is a micro-doped high-resistance epitaxial layer; manufacturing an active region of SIT on the high-resistance epitaxial layer, wherein the channel length of the active region is 2-3 um, and the doping concentration of the gate region is 1 multiplied by 10 18 ~1×10 19 cm -3 The doping concentration of the source region is also 1×10 18 ~1×10 19 cm -3 。
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1393792A (en) * | 1971-04-28 | 1975-05-14 | Handotai Kenkyu Shinkokai | Field effect transistor |
| US4216490A (en) * | 1977-03-31 | 1980-08-05 | Kabushiki Kaisha Daini Seikosha | Static induction transistor |
| KR20010023215A (en) * | 1998-09-09 | 2001-03-26 | 가나이 쓰토무 | Static induction transistor, method of manufacturing same and electric power conversion apparatus |
| CN104810395A (en) * | 2015-04-16 | 2015-07-29 | 兰州大学 | Surface grid-type static induction transistor |
| CN204632764U (en) * | 2015-04-16 | 2015-09-09 | 兰州大学 | A kind of surperficial grid-type static induction transistor |
| CN206040648U (en) * | 2016-09-23 | 2017-03-22 | 兰州大学 | Controllable type static induction transistor of electric current |
-
2016
- 2016-09-23 CN CN201610847814.8A patent/CN106449745B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1393792A (en) * | 1971-04-28 | 1975-05-14 | Handotai Kenkyu Shinkokai | Field effect transistor |
| US4216490A (en) * | 1977-03-31 | 1980-08-05 | Kabushiki Kaisha Daini Seikosha | Static induction transistor |
| KR20010023215A (en) * | 1998-09-09 | 2001-03-26 | 가나이 쓰토무 | Static induction transistor, method of manufacturing same and electric power conversion apparatus |
| CN104810395A (en) * | 2015-04-16 | 2015-07-29 | 兰州大学 | Surface grid-type static induction transistor |
| CN204632764U (en) * | 2015-04-16 | 2015-09-09 | 兰州大学 | A kind of surperficial grid-type static induction transistor |
| CN206040648U (en) * | 2016-09-23 | 2017-03-22 | 兰州大学 | Controllable type static induction transistor of electric current |
Non-Patent Citations (1)
| Title |
|---|
| Short-Circuit Operation of SiC Buried Gate Static Induction Transistors;Koji Yano等;《Silicon Carbide and Related Materials 2008》;第615-617卷;739-742 * |
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