CN106449592A - High-quality-factor differential inductor structure and manufacturing process therefor - Google Patents

High-quality-factor differential inductor structure and manufacturing process therefor Download PDF

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CN106449592A
CN106449592A CN201610708670.8A CN201610708670A CN106449592A CN 106449592 A CN106449592 A CN 106449592A CN 201610708670 A CN201610708670 A CN 201610708670A CN 106449592 A CN106449592 A CN 106449592A
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silicon
hole
layout
metal wire
layer
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CN106449592B (en
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赵文生
郑杰
陈世昌
王晶
王高峰
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Hangzhou Dianzi University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/81024—Applying flux to the bonding area

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Coils Or Transformers For Communication (AREA)

Abstract

The invention discloses a high-quality-factor differential inductor structure and a manufacturing process therefor. The differential inductor is positioned in a circular ring through silicon via array and divides through silicon vias in the circular ring into a left side and a right side, including a first through silicon via, a second through silicon via, a third through silicon via, a fourth through silicon via, a fifth through silicon via and a sixth through silicon via from the top to bottom; and the through silicon vias are subjected to connection of a metal layer and a re-layout layer according to design requirements. According to the manufacturing process, a groove is formed in a silicon substrate in a digging manner through a bosch process so as to reduce the loss of the silicon substrate; the three-dimensional differential inductor is configured through the through silicon via array in the circular ring; and the inductance value is increased due to the coupling (the flowing directions of the current in metal lines in the metal layer and the re-layout layer are opposite to each other) of the interior of the differential inductor and a relatively small effective area.

Description

The differential inductor structure of a kind of high quality factor and manufacture craft thereof
Technical field
The invention belongs to passive electronic technical field, relate to a kind of high quality factor differential inductor structure and Manufacture craft.
Background technology
With the development of wireless telecommunications, radio frequency microwave circuit is at aspects such as Medical Devices, WLAN and Smart Homes It is widely applied.Wherein inductance plays an important role in the circuit such as wave filter, amplifier, frequency mixer and oscillator. With constantly reducing of integrated device, conventional two-dimensional inductor is on area occupied and cannot meet demand on packaging cost.
In recent years, developing rapidly with three dimensional integrated circuits, a kind of emerging ic manufacturing process silicon through hole work Skill receives significant attention.The circuit of silicon chip surface can be connected to silicon chip back side by silicon through hole by it, it is achieved different layers device it Between electric property connect.And silicon through hole technology can provide bigger design freedom and more preferable electric property to design not Same components and parts.Wherein based on silicon through hole technology can be used for construction the piece such as three dimensional inductor and transformer on element, this inductor with Conventional two-dimensional inductor is compared, and has higher quality factor.
The good and bad main judging quota of inductor performance is quality factor, if its quality factor are higher, then and inductance component Performance is better.And the quality factor improving inductor mainly can be carried out from the following aspects：1. reduce the parasitic effect of substrate Should；2. reduce the resistance of inductor own；3. improve self effective inductance value.
Other U.S. Patent No. 8,143,952 B2 patent gives and utilizes silicon hole configuration inductor and transformer Component structure.Wherein utilize the chain structure construction inductor structure of silicon through hole, but this connected mode exists a large amount of incorgruous electricity Stream, weakens inductance value greatly, and then impact makes the quality factor of inductor decline.The present invention will be connected by effective Adjacent silicon through hole and the sense of current in metal interconnecting wires are kept consistent by mode, so will strengthen mutual inductance, and then increase total electricity Inductance value (i.e. improves self effective inductance value).
With more urgent to the demand of bandwidth, the operating frequency of three dimensional integrated circuits improves constantly, noise coupling and electricity Magnetic disturbance problem is further serious.Differential configuration circuit will effectively suppress electromagnetic interference, reduce noise.And differential inductance can extensively answer For in the RF ICs such as mobile phone, TV, wireless network.But traditional plane differential inductance still face area occupied and The problems such as quality factor are low.And current existing silicon via process is to utilize plasma etching through hole, chemical gaseous phase is used to sink Shallow lake method forms oxide layer in through-hole surfaces, fills through hole finally by copper electro-plating method, and uses chemical Mechanical Polishing Technique Remove unnecessary copper electrodeposited coating.In this silicon via process there is loss in silicon base substrate, thus makes the performance of inductance component Decline, i.e. quality factor have reduced.The present invention will provide the three-dimensional differential inductor structure of a kind of high quality factor.With tradition Inductor is compared, and the coupling within differential inductance and less effective area will improve inductance value.
Content of the invention
It is an object of the invention to for the deficiencies in the prior art, provide a kind of based on hollowing out groove technique in silicon base Three-dimensional differential inductor structure, by two-layer coil around silicon through hole cross wiring, improve the inductance value of effective area.
Differential inductor of the present invention is positioned in annulus silicon via-hole array, and described through-silicon via structure is for through silicon base Copper, for preventing leakage current, is provided with the insulating barrier that material is silica in copper periphery, and typically its thickness is 0.5 μm, at insulating barrier Periphery is then silicon base.Be made up of circular ring structure 12 through-silicon via structures, above-mentioned 12 through-silicon via structures are divided into the left and right sides Distribution, left side silicon through hole is symmetrical with right side silicon through hole, and the adjacent silicon through-hole spacing of annulus the same side is identical.Wherein said passes through The radius of the copper of silicon base is 10 μm, and height is 230 μm；Described annulus outer radius is 100 μm, and inside radius is 80 μm；
As preferably, the spacing of annulus the same side adjacent silicon through hole is 31 μm；Left side the first silicon through hole and right side the first silicon The spacing of through hole is 115 μm.
Silicon through hole in annulus is divided into left side and right side, and is the first, second, third and fourthth, the 5th, six silicon through hole from top to bottom. Using the metal level end of left side the first silicon through hole and right side the first silicon through hole as input port, left side the 6th silicon through hole and right side The metal level end of six silicon through holes is as output port.First carry out metal wire arrangement, external metallization line at differential inductor top Connecting input port respectively, the metal level end of left side the second silicon through hole and the metal level end of right side the 3rd silicon through hole pass through metal wire Interconnection, the metal level end of left side the 3rd silicon through hole is intersected even by metal wire with the metal level end of right side the second silicon through hole Connecing, the metal level end of left side the 4th silicon through hole passes through metal wire interconnection, left side with the metal level end of right side the 5th silicon through hole The metal level end of the 5th silicon through hole passes through metal wire interconnection with the metal level end of right side the 4th silicon through hole, and output port is respectively Externally connected by metal wire；
Bottom differential inductor, layout layer carries out metal wire arrangement, the layer end of layout again of left side the first silicon through hole again Pass through metal wire interconnection, the layer end of layout again of left side the second silicon through hole with the layer end of layout again of right side the second silicon through hole Pass through metal wire interconnection, the layer end of layout again of left side the 3rd silicon through hole with the layer end of layout again of right side the first silicon through hole Pass through metal wire interconnection, the layer end of layout again of left side the 4th silicon through hole with the layer end of layout again of right side the 4th silicon through hole Pass through metal wire interconnection, the layer end of layout again of left side the 5th silicon through hole with the layer end of layout again of right side the 3rd silicon through hole Pass through metal wire interconnection, the layer end of layout again of left side the 6th silicon through hole with the layer end of layout again of right side the 6th silicon through hole Pass through metal wire interconnection with the layer end of layout again of right side the 5th silicon through hole.
A further object of the present invention is to provide the process for making of above-mentioned three-dimensional differential inductor structure.The method bag Containing following steps：
Step (1), first to carry out silicon base wafer thinning, and is polished silicon chip upper and lower surface；
Step (2), carry out precipitation of silica in silicon chip upper and lower surface and form oxide layer (its thickness be more than 0.5 μm), and Define silicon via regions, pass sequentially through anisotropic corrosion silica；
Step (3), in defining silicon via regions, utilize Bosch technique etching silicon wafer, form through hole；
Step (4), the thickness 0.5 μm defining oxide layer, and remove the blocked up oxide layer of silicon chip upper and lower surface, until Its thickness reaches 0.5 μm, and the additionally sidewall synchronization at through hole forms the oxide layer that thickness is 0.5 μm；
Step (5), use copper electric plating method carry out copper filling to through hole, fill through hole full；
Step (6), use bosch technique hollow out groove structure around copper vias so that the silicon base thickness around copper is 10μm；
Step (7), in silicon chip metal layer at top according to the layout designing, carry out metal wire connection；
Step (8), on new silicon chip, layout layer carries out metal wire connection by the layout designing again, afterwards again Add solder joint with another corresponding position of silicon chip silicon through hole on layout layer.
Step (9), finally two pieces of silicon chips are fitted up and down.
The present invention utilizes bosch technique to hollow out groove in silicon base, reduces silicon base loss.Utilize the silicon through hole battle array in annulus Row construction three-dimensional differential inductor, the coupling (electric current in metal wire in metal level and again layout layer within differential inductance Flow to incorgruous two-by-two) and less effective area will improve inductance value.
Brief description
Fig. 1 is the inductance unit according to the utilization silicon hole configuration shown by U.S. Patent No. 8,143,952 B2 patent Part；
Fig. 2 is the top and bottom sectional view of three-dimensional differential inductor；
Fig. 3 is the stereogram of three-dimensional differential inductor；
Fig. 4 A-H is the process chart that the present invention makes inductor.
Fig. 1 mark as follows：Inductance element 100, first input port 101, the second input port 102, runs through substrate Silicon through hole 103, the metal wire 104 in base top metal level M1, the metal wire 105 in the layer of layout again bottom substrate；
Fig. 2, mark is as follows in 3：Left side the first silicon through hole 401, left side the second silicon through hole 402, left side the 3rd silicon through hole 403, left side the 4th silicon through hole 404, left side the 5th silicon through hole 405, left side the 6th silicon through hole 406, right side the first silicon through hole 407, Right side the second silicon through hole 408, right side the 3rd silicon through hole 409, right side the 4th silicon through hole 410, right side the 5th silicon through hole 411, right side 6th silicon through hole 412；
Fig. 4 mark as follows：Silicon chip 601, silicon chip upper and lower surface silica 602, silicon via regions 603, through hole 604, Through-hole side wall oxide layer 605, copper 606, dead slot structure 607, again layout layer 608, solder joint 609.
Detailed description of the invention
Below in conjunction with accompanying drawing, the invention will be further described.
Fig. 1 is the inductance unit according to the utilization silicon hole configuration shown by U.S. Patent No. 8,143,952 B2 patent Part 100, it include input port 101 and the 102nd, run through substrate silicon through hole the 103rd, base top metal level M1 in metal wire 104 and substrate bottom the layer of layout again in metal wire 105.It utilizes silicon through hole technology to extend metal wire as seen from the figure Length, thus obtain bigger inductance value.But being limited to silicon clear size of opening, its self-induction is less, and metal level M1 and layout layer again Middle metal wire exists substantial amounts of heterodrome, overall inductance value can be reduced.
Fig. 2 is top and the bottom section figure of three-dimensional differential inductor.Differential inductor is positioned in annulus silicon via-hole array, Silicon through hole in annulus is divided into left side and right side, and is the first, second, third and fourthth, the 5th, six silicon through hole from top to bottom.By left side The metal level end of one silicon through hole 401 and right side the first silicon through hole 407 is as input port, left side the 6th silicon through hole 406 and right side The metal level end of the 6th silicon through hole 412 is as output port.Metal level end at differential inductor carries out metal wire arrangement, outside Metal wire is respectively connecting to the metal level end (input port) of left side and right side the first silicon through hole, left side the second silicon through hole 402 Metal level end passes through metal wire interconnection, the gold of left side the 3rd silicon through hole 403 with the metal level end of right side the 3rd silicon through hole 409 The metal level end belonging to layer end with right side the second silicon through hole 408 passes through metal wire interconnection, the metal of left side the 4th silicon through hole 404 Layer end passes through metal wire interconnection, the metal level of left side the 5th silicon through hole 405 with the metal level end of right side the 5th silicon through hole 411 End passes through metal wire interconnection, the metal of left side and right side the 6th silicon through hole with the metal level end of right side the 4th silicon through hole 410 Layer end (output port) is externally connected by metal wire respectively；
Carry out metal wire arrangement, the layer end of layout again of left side the first silicon through hole 401 at differential inductor again layout layer Pass through metal wire interconnection, the cloth again of left side the second silicon through hole 402 with the layer end of layout again of right side the second silicon through hole 408 Office's layer end passes through metal wire interconnection with the layer end of layout again of right side the first silicon through hole 407, left side the 3rd silicon through hole 403 Again layout layer end and the layer end of layout again of right side the 4th silicon through hole 410 pass through metal wire interconnection, and left side the 4th silicon leads to Again the layout layer end in hole 404 and the layer end of layout again of right side the 3rd silicon through hole 409 pass through metal wire interconnection, left side the Again the layout layer end of five silicon through holes 405 passes through metal wire interconnection with the layer end of layout again of right side the 6th silicon through hole 412, The left side layer end of layout again of the 6th silicon through hole 406 is handed over by metal wire with the layer end of layout again of right side the 5th silicon through hole 411 Fork connects.
Fig. 3 is the stereogram of three-dimensional differential inductor, the course of work of this inductance element：Electric current is respectively from two input ports (413 and 414) begin to flow into, and first electric current is flowed into the gold of left side the first silicon through hole 401 from input port 413 by metal wire Belong to layer end, and flow to its layout layer end again by silicon through hole, then by metal wire flow on the right side of the weight of the second silicon through hole 408 New layout layer end, and by flowing to its metal level end, then flowed into the metal level of left side the 3rd silicon through hole 403 by metal wire End, and flow to its layout layer end again by silicon through hole, then by metal wire flow on the right side of the cloth again of the 4th silicon through hole 410 Office's layer end, and flow to its metal level end by silicon through hole, the metal of left side the 5th silicon through hole 405 is then flowed into by metal wire Layer end, and flow to its layout layer end again by silicon through hole, then by metal wire flow on the right side of the 6th silicon through hole 412 again Layout layer end, and by flowing to its metal level end, then flow to its output port 416；Another electric current passes through from input port 414 Metal wire flows into the metal level end of right side the first silicon through hole 407, and flows to its layout layer end again by silicon through hole, then leads to Cross the layer end of layout again of the second silicon through hole 402 on the left of the metal wire flow direction, and by flowing to its metal level end, then pass through metal Line flows into the metal level end of right side the 3rd silicon through hole 409, and flows to its layout layer end again by silicon through hole, then by gold Belong to the layer end of layout again of the 4th silicon through hole 404 on the left of the line flow direction, and flow to its metal level end by silicon through hole, then by gold Belong to line and flow into the metal level end of right side the 5th silicon through hole 411, and flow to its layout layer end again by silicon through hole, then pass through Again the layout layer end of the 6th silicon through hole 406 on the left of the metal wire flow direction, and by flowing to its metal level end, then flow to its output Port 415.
The manufacture craft process of above-mentioned inductor：
Step one, as shown in Figure 4 A, it is thinning first to carry out wafer, and is polished silicon chip 601 upper and lower surface；
Step 2, as shown in Figure 4 B, carries out silica 602 precipitation in silicon chip 601 upper and lower surface and forms oxide layer (its thickness Degree is more than 0.5 μm), and define silicon via regions 603, pass sequentially through anisotropic corrosion silica.
Step 3, as shown in Figure 4 C, in defining silicon via regions, utilizes Bosch technique etching silicon wafer, forms through hole 604；
Step 4, as shown in Figure 4 D, the thickness defining oxide layer is 0.5 μm, and it is blocked up to remove silicon chip upper and lower surface Oxide layer 602, until its thickness reaches 0.5 μm, additionally the sidepiece synchronization at through hole 604 forms thickness is the oxygen of 0.5 μm Change layer 605.
Step 5, as shown in Figure 4 E, uses copper electric plating method to carry out copper to through hole and fills 606；
Step 6, as illustrated in figure 4f, uses bosch technique to hollow out groove structure 607 around copper vias so that around copper Silicon base thickness is 10 μm；
Step 7, at silicon chip metal level according to the layout of Fig. 4 A (differential inductor), carries out metal wire connection；
Step 8, as shown in Figure 4 G, the layer of layout again on new silicon chip is according to the layout of Fig. 4 B (differential inductor) Connect, on layout layer 608 again, add solder joint 609 with another corresponding position of silicon chip silicon through hole afterwards.
Two pieces of silicon chips as shown at figure 4h, are finally fitted by step 9 up and down.
Above-described embodiment is not the restriction for the present invention, and the present invention is not limited only to above-described embodiment, as long as meeting Application claims, belongs to protection scope of the present invention.

Claims (9)

1. one kind based on the novel differential inductor hollowing out groove technique in silicon base, it is characterised in that differential inductor is positioned at circle In ring silicon via-hole array, in this annulus, silicon through hole is provided with 12, the uniform setting in above-mentioned 12 silicon through hole left and right sides, and left side silicon Through hole is symmetrical with right side silicon through hole, and the adjacent silicon through-hole spacing of the same side is identical；
Left and right side silicon through hole is the first, second, third and fourthth, the 5th, six silicon through hole from top to bottom；By left side the first silicon through hole and right side The metal level end of one silicon through hole is as input port, and the metal level end of left side the 6th silicon through hole and right side the 6th silicon through hole is as defeated Go out port；
First carry out metal wire arrangement at differential inductor top, external metallization line connects input port, left side the second silicon respectively The metal level end of through hole passes through metal wire interconnection, the gold of left side the 3rd silicon through hole with the metal level end of right side the 3rd silicon through hole Belong to the metal level end of layer end and right side the second silicon through hole and pass through metal wire interconnection, the metal level end of left side the 4th silicon through hole with The metal level end of right side the 5th silicon through hole passes through metal wire interconnection, the metal level end of left side the 5th silicon through hole and right side the 4th The metal level end of silicon through hole passes through metal wire interconnection, and output port is externally connected by metal wire respectively；
Bottom differential inductor, layout layer carries out metal wire arrangement, the layer end of layout again of left side the first silicon through hole and the right side again Again the layout layer end of side the second silicon through hole passes through metal wire interconnection, the layer end of layout again of left side the second silicon through hole and the right side Again the layout layer end of side the first silicon through hole passes through metal wire interconnection, the layer end of layout again of left side the 3rd silicon through hole and the right side Again the layout layer end of side the 4th silicon through hole passes through metal wire interconnection, the layer end of layout again of left side the 4th silicon through hole and the right side Again the layout layer end of side the 3rd silicon through hole passes through metal wire interconnection, the layer end of layout again of left side the 5th silicon through hole and the right side Again the layout layer end of side the 6th silicon through hole passes through metal wire interconnection, the layer end of layout again of left side the 6th silicon through hole and the right side Again the layout layer end of side the 5th silicon through hole passes through metal wire interconnection.
2. a kind of based on the novel differential inductor hollowing out groove technique in silicon base as claimed in claim 1, its feature exists In through-silicon via structure, the thickness of copper periphery insulating barrier is 0.5 μm.
3. a kind of based on the novel differential inductor hollowing out groove technique in silicon base as claimed in claim 1, its feature exists The radius of the copper passing through silicon base in through-silicon via structure is 10 μm, and height is 230 μm.
4. a kind of based on the novel differential inductor hollowing out groove technique in silicon base as claimed in claim 1, its feature exists Being 100 μm in the annulus outer radius of described annulus silicon via-hole array, inside radius is 80 μm.
5. a kind of based on the novel differential inductor hollowing out groove technique in silicon base as claimed in claim 1, its feature exists It it is 31 μm in the spacing of annulus the same side adjacent silicon through hole.
6. a kind of based on the novel differential inductor hollowing out groove technique in silicon base as claimed in claim 1, its feature exists It it is 115 μm in the spacing of left side the first silicon through hole and right side the first silicon through hole.
7. a kind of making work based on the novel differential inductor hollowing out groove technique in silicon base as claimed in claim 1 Skill, it is characterised in that this process includes as follows：
Step (1), first to carry out silicon base wafer thinning, and is polished this silicon chip upper and lower surface；
Step (2), the silicon chip upper and lower surface after step (1) is processed carry out precipitation of silica, form oxide layer；Then define Go out silicon via regions, pass sequentially through anisotropic corrosion silica；
Step (3), in the silicon via regions defining, utilize Bosch technique etching silicon wafer, form through hole；
The blocked up oxide layer of step (4), removal silicon chip upper and lower surface, until certain thickness；Sidewall in step (3) through hole simultaneously Form certain thickness oxide layer；
Step (5), use copper electric plating method carry out copper filling to through hole, fill through hole full；
Step (6), use bosch technique hollow out groove structure in copper vias periphery silicon base；
Step (7), process the silicon chip metal layer at top that obtains according to the layout described in claim 1 in above-mentioned steps (6), carry out Metal wire connects；
Step (8), separately taking a new silicon chip, layout layer carries out metal wire connection according to the layout described in claim 1 again；
Step (9), add solder joint in the layer of layout again of step (8) the silicon chip position corresponding with step (7) silicon chip silicon through hole, Finally two pieces of silicon chips are fitted up and down.
8. manufacture craft as claimed in claim 7, it is characterised in that it is blocked up that step (4) specifically removes silicon chip upper and lower surface Oxide layer, until its thickness reaches 0.5 μm；Sidewall in step (3) through hole forms the oxide layer that thickness is 0.5 μm simultaneously.
9. manufacture craft as claimed in claim 7, it is characterised in that step (6) specifically uses bosch technique at copper vias Periphery silicon base hollows out groove structure, and the silicon base thickness around copper is 10 μm.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0920036A1 (en) * 1997-11-28 1999-06-02 STMicroelectronics SA Integrated circuit transformer
CN101142638A (en) * 2005-08-04 2008-03-12 加利福尼亚大学董事 Interleaved three-dimensional on-chip differential inductors and transformers
JP2011096778A (en) * 2009-10-28 2011-05-12 Seiko Epson Corp Wiring structure of spiral coil and integrated circuit device
CN103824840A (en) * 2012-11-16 2014-05-28 南京理工大学 Solenoid type difference inductor based on silicon through hole
US20160163450A1 (en) * 2014-07-18 2016-06-09 Qualcomm Incorporated Superposed structure 3d orthogonal through substrate inductor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0920036A1 (en) * 1997-11-28 1999-06-02 STMicroelectronics SA Integrated circuit transformer
CN101142638A (en) * 2005-08-04 2008-03-12 加利福尼亚大学董事 Interleaved three-dimensional on-chip differential inductors and transformers
JP2011096778A (en) * 2009-10-28 2011-05-12 Seiko Epson Corp Wiring structure of spiral coil and integrated circuit device
CN103824840A (en) * 2012-11-16 2014-05-28 南京理工大学 Solenoid type difference inductor based on silicon through hole
US20160163450A1 (en) * 2014-07-18 2016-06-09 Qualcomm Incorporated Superposed structure 3d orthogonal through substrate inductor

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