CN106449580B - A kind of wafer bonding structure - Google Patents
A kind of wafer bonding structure Download PDFInfo
- Publication number
- CN106449580B CN106449580B CN201611082157.9A CN201611082157A CN106449580B CN 106449580 B CN106449580 B CN 106449580B CN 201611082157 A CN201611082157 A CN 201611082157A CN 106449580 B CN106449580 B CN 106449580B
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- China
- Prior art keywords
- wafer
- bond wire
- metal layer
- bonding structure
- step shape
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Abstract
The present invention provides a kind of wafer bonding structures, comprising: the upper wafer and lower wafer being bonded together by bond wire；The edge of the upper wafer and lower wafer is respectively provided with a step shape, and the step shape of the upper wafer and lower wafer is away from each other and symmetrical relative to the bond wire；The metal layer of the step and upper wafer side, lower wafer side, bond wire side is covered, the metal layer cross section is in C font.Technical solution of the present invention, the warpage at bonding structure edge is prevented using the C font metal layer on periphery in wafer bonding structure, and the rigidity of metal layer can inhibit the stress generated due to bonding.
Description
Technical field
The present invention relates to a kind of semiconductor package part, espespecially a kind of wafer bonding structure.
Background technique
Existing wafer bonding usually carries out indirect key by two Silicon Wafer Direct Bondings or by a bond wire
Close, but no matter which kind of bonding pattern, require to be subjected to a high-temperature process, thus can generate certain internal stress.
As shown in Figure 1, upper wafer 1 and lower wafer 2 carry out bonding together to form bonding structure by intermediate bond wire 3, but
It is that can form warp zone 4 in marginal position, which is due to the stress between wafer and between wafer and bond wire
It is unfavorable for subsequent use.The warpage and cracking for how preventing bonding edge are this field urgent problems to be solved.
Summary of the invention
Based on the problems in above-mentioned wafer bonding is solved, the present invention provides a kind of wafer bonding structures, comprising: passes through key
The upper wafer and lower wafer that alloy category is bonded together；The edge of the upper wafer and lower wafer is respectively provided with a step shape,
The step shape of the upper wafer and lower wafer is away from each other and symmetrical relative to the bond wire；Cover the step and upper
The metal layer of wafer side, lower wafer side, bond wire side, the metal layer cross section are in C font.
According to an embodiment of the invention, the metal layer is identical as the material of the bond wire.
According to an embodiment of the invention, the material of the metal layer and the bond wire is copper.
According to an embodiment of the invention, the upper wafer and lower wafer are Silicon Wafer.
According to an embodiment of the invention, further comprising at crystal round fringes position through the upper wafer and lower wafer
And multiple equally distributed metal throuth holes of bond wire.
According to an embodiment of the invention, the material of the metal throuth hole is identical as the bond wire.
According to an embodiment of the invention, the metal throuth hole is located at the interior of the step shape of the upper wafer and lower wafer
Side.
According to an embodiment of the invention, the metal throuth hole is located at the step shape of the upper wafer and lower wafer, from
Expose at the step shape.
Technical solution of the present invention prevents bonding structure edge using the C font metal layer on periphery in wafer bonding structure
Warpage, the rigidity of metal layer can inhibit due to bonding generate stress；Further, through the metal throuth hole of the wafer
Connect up and down two wafers, offset the stress of edge warping, and facilitate the heat dissipation of marginal position, due to metal color with
Wafer color is different (relatively deep), and metal throuth hole can be used as alignment mark use.
Detailed description of the invention
Fig. 1 is the sectional view of existing wafer bonding structure；
Fig. 2 is the sectional view of the wafer bonding structure of first embodiment of the invention；
Fig. 3 is the sectional view of the wafer bonding structure of second embodiment of the invention；
Fig. 4 is the sectional view of the wafer bonding structure of second embodiment of the invention；
Fig. 5 is the sectional view of the wafer bonding structure of second embodiment of the invention.
Specific embodiment
Referring to fig. 2, the present invention provides a kind of wafer bonding structures, comprising: is bonded together by bond wire 3 upper
Wafer 1 and lower wafer 2；The edge of the upper wafer 1 and lower wafer 2 is respectively provided with a step shape 5,6, upper 1 He of wafer
The step shape 5,6 of lower wafer 2 is away from each other and symmetrical relative to the bond wire 3；Cover the step shape 5,6 and on
The metal layer 7 of 1 side of wafer, 2 side of lower wafer, 3 side of bond wire, 7 section of metal layer are in C font.The metal
Layer 7 is identical as the material of the bond wire 3, it is preferred that the material of the metal layer and the bond wire is copper.It is described
Upper wafer and lower wafer are Silicon Wafer.
Embodiment shown in Fig. 3 comprising at crystal round fringes position through the upper wafer 1 and lower wafer 2 and
Multiple equally distributed metal throuth holes 8 of bond wire 3 are other identical as example shown in Fig. 2.
Fig. 4 and Fig. 5 is the combination of Fig. 2 and Fig. 3, and C font metal layer 7 is applied in combination with metal throuth hole 8.Shown in Fig. 4
Embodiment, the metal throuth hole 8 is located at the inside of the step shape 5,6 of the upper wafer 1 and lower wafer 2.Reality shown in fig. 5
Example is applied, the metal throuth hole 8 is located at the step shape 5 of the upper wafer 1 and lower wafer 2, reveals from the step shape 5
Out.Wherein, the material of the metal throuth hole 8 is identical as the bond wire 3.
Finally, it should be noted that obviously, the above embodiment is merely an example for clearly illustrating the present invention, and simultaneously
The non-restriction to embodiment.For those of ordinary skill in the art, it can also do on the basis of the above description
Other various forms of variations or variation out.There is no necessity and possibility to exhaust all the enbodiments.And thus drawn
The obvious changes or variations that Shen goes out are still in the protection scope of this invention.
Claims (5)
1. a kind of wafer bonding structure, comprising: the upper wafer and lower wafer being bonded together by bond wire；The upper wafer
Be respectively provided with a step shape with the edge of lower wafer, the step shape of the upper wafer and lower wafer be away from each other and relative to
The bond wire is symmetrical；Cover the metal layer of the step and upper wafer side, lower wafer side, bond wire side, institute
Metal layer cross section is stated in C font；It further comprise at crystal round fringes position through the upper wafer and lower wafer and key
Multiple equally distributed metal throuth holes that alloy belongs to；The metal throuth hole be located at the upper wafer and lower wafer compared to described
The inside of step shape or the metal throuth hole are located at the step shape of the upper wafer and lower wafer, from the step
Expose at shape.
2. wafer bonding structure according to claim 1, which is characterized in that the material of the metal layer and the bond wire
Matter is identical.
3. wafer bonding structure according to claim 2, which is characterized in that the material of the metal layer and the bond wire
Matter is copper.
4. wafer bonding structure according to claim 1, which is characterized in that the upper wafer and lower wafer are silicon wafer
Circle.
5. wafer bonding structure according to claim 1, which is characterized in that the material of the metal throuth hole is bonded with described
Metal phase is same.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611082157.9A CN106449580B (en) | 2016-11-30 | 2016-11-30 | A kind of wafer bonding structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611082157.9A CN106449580B (en) | 2016-11-30 | 2016-11-30 | A kind of wafer bonding structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106449580A CN106449580A (en) | 2017-02-22 |
| CN106449580B true CN106449580B (en) | 2019-04-26 |
Family
ID=58222693
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611082157.9A Expired - Fee Related CN106449580B (en) | 2016-11-30 | 2016-11-30 | A kind of wafer bonding structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106449580B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112018002A (en) * | 2020-08-25 | 2020-12-01 | 武汉新芯集成电路制造有限公司 | Wafer bonding equipment and wafer bonding method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103021983A (en) * | 2012-11-22 | 2013-04-03 | 北京工业大学 | Wafer level chip size package and manufacturing method thereof |
| CN203165886U (en) * | 2013-01-14 | 2013-08-28 | 武汉新芯集成电路制造有限公司 | Image sensor structure |
| CN105070668A (en) * | 2015-08-06 | 2015-11-18 | 武汉新芯集成电路制造有限公司 | Wafer-level chip packaging method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103426732B (en) * | 2012-05-18 | 2015-12-02 | 上海丽恒光微电子科技有限公司 | The method of low-temperature wafer bonding and the structure formed by the method |
-
2016
- 2016-11-30 CN CN201611082157.9A patent/CN106449580B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103021983A (en) * | 2012-11-22 | 2013-04-03 | 北京工业大学 | Wafer level chip size package and manufacturing method thereof |
| CN203165886U (en) * | 2013-01-14 | 2013-08-28 | 武汉新芯集成电路制造有限公司 | Image sensor structure |
| CN105070668A (en) * | 2015-08-06 | 2015-11-18 | 武汉新芯集成电路制造有限公司 | Wafer-level chip packaging method |
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| Publication number | Publication date |
|---|---|
| CN106449580A (en) | 2017-02-22 |
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Effective date of registration: 20190401 Address after: 312500 Chenjiawu No. 27, Fangquan Village, Xiaojiang Town, Xinchang County, Shaoxing City, Zhejiang Province (Residence Declaration) Applicant after: Xinchang Fengtian Intelligent Technology Co., Ltd. Address before: 226300 window of science and technology, No. 266, New Century Avenue, Nantong hi tech Zone, Nantong, Jiangsu Applicant before: Nantong Voight Optoelectronics Technology Co., Ltd. |
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| CF01 | Termination of patent right due to non-payment of annual fee |