CN106447594A - Image processing device and method - Google Patents
Image processing device and method Download PDFInfo
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- CN106447594A CN106447594A CN201610678348.5A CN201610678348A CN106447594A CN 106447594 A CN106447594 A CN 106447594A CN 201610678348 A CN201610678348 A CN 201610678348A CN 106447594 A CN106447594 A CN 106447594A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2200/00—Indexing scheme for image data processing or generation, in general
- G06T2200/28—Indexing scheme for image data processing or generation, in general involving image processing hardware
Abstract
An image processing method is executed by an image processing device receiving images, and comprises the steps of firstly receiving the real-time serial data coming from images and generating the temporary storage serial data according to the real-time serial data, then transforming the temporary storage serial data and the real-time serial data into the first parallel output data and the second parallel output data respectively, and then carrying out the convolution operation with a template to generate a convolution value according to the first and second parallel output data, and then carrying out the additive operation with the convolution value according to the b-th pixel value of the second parallel output data to generate the b-th pixel value of a plurality of pixel values of a new image. According to the present invention, the image processing device only stores the temporary storage serial data while the horizontal boundary and the vertical boundary are detected simultaneously, thereby reducing the hardware storage area.
Description
Technical field
The invention relates to a kind of devices and methods therefor, particularly relate to a kind of reduce hardware required when processing image and hold
The image processing apparatus of amount and method thereof.
Background technology
Existing image processing module has the excessive disappearance of hardware storage area, for example following 2 points of chief reason：
1. at least need three buffers：Existing image processing module is in order to detect the limit of the image with multiple pixel value
Boundary, at least needs the template using 3 × 3 could detect vertical boundary and horizontal boundary simultaneously, and as depicted in figs. 1 and 2, Fig. 1 is a left side
The template that right two row's coefficient weights are not zero, in order to detecting horizontal boundary, and Fig. 2 is the mould that upper and lower two row's coefficient weights are not zero
Plate, in order to detecting vertical boundary, but whether detects horizontal boundary and still detects vertical boundary, and image processing module is required for storage
The three row pixel values depositing image could use the template of 3 × 3 to do computing, and therefore, image processing module at least needs three to delay
Rush device and store three row pixel values, so that hardware storage area is excessive.
2. the storage area of every buffer is bigger：Every buffer of existing image processing module needs to store the every of image
The R value (Red) of each pixel of one row, G value (Green) and B value (Blue), therefore, every buffer needs have bigger storage
Deposit space.
Content of the invention
Therefore, the first object of the present invention, is i.e. providing a kind of image processing method that can reduce hardware storage area.
Then, image processing method of the present invention, is performed by image processing apparatus, and image processing apparatus comprises image procossing mould
Block, image processing module includes receiving the buffer of image, receives image and electrically connect the transformation from serial to parallel output list of buffer
Unit, and the processing unit of electrical connection transformation from serial to parallel output unit, wherein, image includes M row pixel column, each row pixel column bag
Including N number of pixel value, and 2 M, 3 N, and M, N is positive integer, and image processing method comprises step (A), step (B), step
, and step (D) (C).
Step (A)：Transformation from serial to parallel output unit receives the temporary serial data from buffer, temporary serial data packet
Including the nth pixel value of m row pixel column of serial arrangement to p-th pixel value, transformation from serial to parallel output unit is by temporary string
Row data are converted into the first parallel output data, and the first parallel output data includes n-th of the m row pixel column of parallel arranged
Pixel value is to p-th pixel value, wherein, and 2 p-n, p N, 1 m M-1,1 n N-2, and p, m, n be positive integer.
Step (B)：Transformation from serial to parallel output unit receives the real-time serial data of self imaging, and real-time serial data include
The nth pixel value of (m+1) row pixel column of serial arrangement is to p-th pixel value, and transformation from serial to parallel output unit will be in real time
Serial data is converted into the second parallel output data, and the second parallel output data includes (m+1) row pixel column of parallel arranged
Nth pixel value to p-th pixel value.
Step (C)：Processing unit receive from transformation from serial to parallel output unit the first parallel output data and second simultaneously
Row output data, and the first parallel output data and the second parallel output data are carried out convolution algorithm with a template and produce volume
Product value, wherein, template includes two row coefficient row, and each row coefficient arranges has (p-n+1) individual coefficient weights, and two row coefficients row
Wherein n-th of the m row pixel column of (p-n+1) individual coefficient weights corresponding first parallel output data respectively of row coefficient row
Pixel value is to p-th pixel value, and (p-n+1) individual coefficient weights correspondence respectively of wherein another row coefficient row of two row coefficient row
The nth pixel value of (m+1) row pixel column of the second parallel output data is to p-th pixel value.
Step (D)：Processing unit carries out add operation according to b-th pixel value and the convolution value of the second parallel output data
Producing b-th pixel value of (m+1) row pixel column of new image, wherein, n b p, b are positive integer.
Therefore, the second object of the present invention, is i.e. providing a kind of image processing apparatus that can reduce hardware storage area.
Then, image processing apparatus of the present invention comprises image processing module, and image processing module receives image, and image includes
M row pixel column, each row pixel column includes that N number of pixel value, wherein, 2 M, 3 N, and M, N are positive integer, image processing module
Comprise buffer, transformation from serial to parallel output unit, and processing unit.
Buffer is converted into temporary serial data in order to received in sequence the real-time serial data storing self imaging, real
When serial data include the nth pixel value of m row pixel column of serial arrangement to p-th pixel value, and the of serial arrangement
(m+1) the nth pixel value of row pixel column is to p-th pixel value, and temporary serial data includes the m row pixel of serial arrangement
The nth pixel value of row is to p-th pixel value, wherein, and 2 p-n, p N, 1 m M-1,1 n N-2, and p, m, n are for just
Integer.
Transformation from serial to parallel output unit electrical connection buffer, to receive the temporary serial data of buffer, keeps in serial data
Including the nth pixel value of the m row pixel column of serial arrangement is to p-th pixel value, also receive the real-time serial of self imaging
Data, real-time serial data include the nth pixel value of (m+1) row pixel column of serial arrangement to p-th pixel value, serial
Turn parallel output unit and temporary serial data and real-time serial data are converted into the first parallel output data and second simultaneously respectively
Row output data.
Processing unit electrical connection transformation from serial to parallel output unit is to receive the first parallel output data and the second parallel output
Data, and the first parallel output data and the second parallel output data are carried out convolution algorithm with a template and produce convolution value,
B-th pixel value and convolution value further according to the second parallel output data carry out (m+1) row that add operation produces new image
B-th pixel value of pixel column, wherein, template includes two row coefficient row, and each row coefficient row have (p-n+1) individual coefficient power
Weight, and (p-n+1) individual coefficient weights corresponding first parallel output data respectively of wherein row coefficient row of two row coefficients row
The nth pixel value of m row pixel column is to p-th pixel value, and (p-n+1) of wherein another row coefficient row of two row coefficient row
The nth pixel value of individual coefficient weights (m+1) row pixel column of corresponding second parallel output data respectively is to p-th pixel
Value, wherein, n b p, b are positive integer.
Brief description
Other the feature of the present invention and effect, clearly will present, wherein in reference to graphic embodiment：
Fig. 1 is schematic diagram, and 3 × 3 templates of the detecting horizontal boundary of conventional images processing module are described；
Fig. 2 is schematic diagram, and 3 × 3 templates of the detecting vertical boundary of conventional images processing module are described；
Fig. 3 is block diagram, and the first embodiment of image processing method of the present invention is described；
Fig. 4 is schematic diagram, and the image processing module of the first embodiment of image processing method of the present invention is described；
Fig. 5 is flow chart, and the flow chart of the first embodiment of image processing method of the present invention is described；
Fig. 6 is schematic diagram, and the video conversion of the first embodiment of image processing method of the present invention is described；
Fig. 7 is schematic diagram, and the temporary serial stored by buffer of the first embodiment of image processing method of the present invention is described；
Fig. 8 is schematic diagram, and the first stage of the first embodiment of image processing method of the present invention is described；
Fig. 9 is schematic diagram, and the second stage of the first embodiment of image processing method of the present invention is described；
Figure 10 is schematic diagram, illustrates that the existing numerical value of m is added 1 as next number by the first embodiment of image processing method of the present invention
Value, and perform the first stage；
Figure 11 is schematic diagram, and the new image of the first embodiment of image processing method of the present invention is described；
Figure 12 is flow chart, illustrate image processing method of the present invention the second embodiment step (A) before step (A1) extremely
(A6) flow chart；
Figure 13 is schematic diagram, and the phase III of the second embodiment of image processing method of the present invention is described；
Figure 14 is schematic diagram, and the fourth stage of the second embodiment of image processing method of the present invention is described；And
Figure 15 is schematic diagram, and the new image of the second embodiment of image processing method of the present invention is described.
Illustrate
1 image processing apparatus
11 images
The L value of the pixel of L1 ~ L36 image
2 gamut conversion unit
21 raw videos
The pixel of O1 ~ O36 raw video
The R value of the pixel of R1 ~ R36 raw video
The G value of the pixel of G1 ~ G36 raw video
The B value of the pixel of B1 ~ B36 raw video
3 image processing modules.
Detailed description of the invention
Refering to Fig. 3, the first embodiment of image processing apparatus 1 of the present invention, image processing apparatus 1 comprises a gamut conversion unit
2, and the image processing module 3 of electrical connection gamut conversion unit 2.
Image processing module 3 electrically connects gamut conversion unit 2, and comprises buffer the 31st, transformation from serial to parallel output unit 32,
And processing unit 37.
Buffer 31 is electrically connected between gamut conversion unit 2 and transformation from serial to parallel output unit 32.
Referring to Fig. 4, transformation from serial to parallel output unit 32 electrically connects buffer the 31st, gamut conversion unit 2 and processes single simultaneously
Between unit 37, and receiving first frequency signal Ck1 and second frequency signal Ck2, transformation from serial to parallel output unit 32 includes first
Flip-flop the 33rd, the second flip-flop the 34th, the 3rd flip-flop 35, and the 4th flip-flop 36, wherein, the first flip-flop is the 33rd, second positive and negative
Device the 34th, the 3rd flip-flop 35 and the 4th flip-flop 36 are D-type flip-flop (Flip-flop, FF).
First flip-flop 33 has electrical connection gamut conversion unit 2 receiving input, the output of real-time serial, and connects
Receiving the frequency input of first frequency signal Ck1, when first frequency signal Ck1 transfers rising edge to, the first flip-flop 33 is to it
Pixel value sampling received by input, and it is sent to its output.
Second flip-flop 34 has electrical connection buffer 31 receiving input, an output of temporary serial, and receives
The frequency input of second frequency signal Ck2, when second frequency signal Ck2 transfers rising edge to, the second flip-flop 34 is defeated to it
Enter the received pixel value sampling of end, and be sent to its output.
3rd flip-flop 35 has the input of the output of electrical connection the second flip-flop 34, electrically connects processing unit 37
Output, and receive the frequency input of second frequency signal Ck2, when second frequency signal Ck2 transfers rising edge to, the 3rd just
Pixel value sampling received by its input for the anti-device 35, and it is sent to its output.
4th flip-flop 36 has the input of the output of electrical connection the first flip-flop 33, electrically connects processing unit 37
Output, and receive the frequency input of first frequency signal Ck1, when first frequency signal Ck1 transfers rising edge to, the 4th just
Pixel value sampling received by its input for the anti-device 36, and it is sent to its output.
Processing unit 37 electrically connects transformation from serial to parallel output unit 32, and includes an arithmetic unit 38, and an adder
39.
Arithmetic unit 38 stores template, and electrically connect the first flip-flop 33 to the 4th flip-flop 36 etc. input and the 3rd just
Anti-device 35 and the 4th flip-flop 36 etc. output.
Adder 39 electrically connects the output of arithmetic unit 38 and the first flip-flop 33.
Refering to Fig. 5, image processing apparatus 1 performs image processing method, and image processing method comprises the steps of：
Refer to Fig. 3 and Fig. 6, step (A0) simultaneously：Gamut conversion unit 2 receives raw video 21, and by raw video more than 21
Rgb value R1 ~ R36, G1 ~ G36, B1 ~ B36 of individual pixel O1 ~ O36 is converted into multiple pixel value L1 ~ L36, respectively wherein, etc. pixel
Value L1 ~ L36 collectively constitutes image 11.
Thinner portion illustrates, gamut conversion unit 2 receives the RGB color territory of raw video 21, and RGB color territory is converted into HSL
Colour gamut, so-called RGB color territory for the color pixel based on red (Red), green (Green) and blue (Blue) three primary colors,
And HSL colour gamut be form and aspect (Hue), saturation degree (Saturation) and brightness (Lightness/Luminance) based on color
Pixel.
It is to say, gamut conversion unit 2 by the rgb value R1 of the multiple pixels O1 ~ O36 of raw video 21 ~ R36, G1 ~
G36, B1 ~ B36 is converted into multiple HSL value respectively, and multiple L value (brightness) L1 ~ L36 of the HSL value such as storage and form image 11,
Image 11 includes M row pixel column, and each row pixel column includes N number of pixel, and each pixel has a pixel value (brightness), also
That is, image includes M × N number of pixel value, and wherein, M × N number of pixel value L1 ~ L36 is the brightness of M × N number of pixel, wherein, 2
M, 3 N, and M, N be positive integer.
In addition, it is noted that the raw video 21 of Fig. 6 and image 11 etc. pixel value R1 ~ R36, G1 ~ G36, B1 ~
The numerical value of the pixels such as the numerical value of B36, L1 ~ L36 is only indicated for convenience of description, not actual, and at the present embodiment, image 11
With six row pixel columns (M=6), and each row pixel column is as a example by six pixel values (N=6).
Step (A1)：Buffer 31 received in sequence the real-time serial data storing self imaging 11, and by real-time serial
Data are converted into temporary serial data, and wherein, real-time serial data include the nth pixel of the m row pixel column of serial arrangement
Value is to p-th pixel value, wherein, and 2 p-n, p N, 1 m M-1,1 n N-2, and p, m, n be positive integer.
The buffer 31 defining the present embodiment at this has the storage area storing seven pixel values, and template has six
(2 × 3) coefficient number, but it is not limited to this, can set according to actual demand.In step (A1), buffer 31 received in sequence includes
The real-time serial data of pixel value L1 ~ L3, and the pixel value L1 ~ L3 of real-time serial data is temporarily stored into buffer 31, and conduct
Temporary serial data.
Need to remark additionally, image processing apparatus 1 is when step (A1), before the unfilled pixel of buffer, the
One frequency signal Ck1 is maintained at low level, and the first flip-flop 33 of transformation from serial to parallel output unit 32 will not be to comprising pixel value
The real-time serial of L1 ~ L3 is sampled, and second frequency signal Ck2 is maintained at low level again, transformation from serial to parallel output unit 32
Temporary transient serial from buffer 31 will not be sampled by the second flip-flop 34, and arithmetic unit 38 be not received entirely six
Before pixel value L1 ~ L6, also will not carry out convolution algorithm with template.
Refering to Fig. 7, be image processing apparatus 1 repeated execution of steps (A1) when, buffer 31 received in sequence and store from
The real-time serial data of image 11, and real-time serial data are converted into illustrating of temporary serial data, until at image
The buffer 31 of reason device 1 completes all pixel values L1 ~ L6 of the first row pixel column of the real-time serial data of image 11, then enter
To step (A).
Step (A)：Transformation from serial to parallel output unit 32 receives the temporary serial data from buffer 31, temporary serial number
To p-th pixel value, transformation from serial to parallel output unit 32 according to the nth pixel value of the m row pixel column including serial arrangement
Temporary serial data is converted into the first parallel output data, and the first parallel output data includes the m row pixel column of parallel arranged
Nth pixel value to p-th pixel value.
Step (B)：Transformation from serial to parallel output unit 32 receives the real-time serial data of self imaging 11, real-time serial data
Including the nth pixel value of (m+1) row pixel column of serial arrangement is to p-th pixel value, transformation from serial to parallel output unit 32
Real-time serial data are converted into the second parallel output data, and the second parallel output data includes (m+1) row of parallel arranged
The nth pixel value of pixel column is to p-th pixel value.As temporary serial data includes pixel value L1 ~ L3, real-time serial packet
Include pixel value L7 ~ L9, then the first parallel output data i.e. includes pixel value L1 ~ L3, and the second parallel output data i.e. includes pixel
Value L7 ~ L9.
Step (I)：Buffer 31 received in sequence and store real-time serial m+1 row pixel column nth pixel value extremely
P-th pixel value.For example, real-time serial data are pixel value L7 ~ L9, then what buffer 31 stored is then real-time serial data
Pixel value L7 ~ L9.
Step (C)：Processing unit 37 receives the first parallel output data and from transformation from serial to parallel output unit 32
Two parallel output data, and the first parallel output data and the second parallel output data are carried out convolution algorithm with template and produce
Convolution value Δ.
Before the explanation for step (A) to the thinner portion of step (C), it is noted that step (A) and step (B) institute
N-th of the m row pixel column of serial data is kept in the operation of the transformation from serial to parallel output unit 32 stated for received in sequence simultaneously
Pixel value is to the nth pixel value of p-th pixel value and (m+1) row pixel column of real-time serial to p-th pixel value.
The start of the explanation step (A) in thinner portion to step (C) is more carried out at this with first stage T1 and second stage T2：
<First stage T1>
Refering to Fig. 8, when first frequency signal Ck1 transfers rising edge to, the pixel value L7 to real-time serial for first flip-flop 33 takes
Sample and the input being sent to the 4th flip-flop 36, when first frequency signal Ck2 transfers rising edge to, the second flip-flop 34 to come
Sample and be sent to the input of the 3rd flip-flop 35 from the pixel value L1 of the temporary serial of buffer, buffer 31 receives and stores up
Deposit the pixel value L7 of real-time serial.
At the same time, the pixel value L8 of real-time serial is sent to the input of the first flip-flop 33, from the picture of buffer
Element value L2 is sent to the input of the second flip-flop 34, for next of first frequency signal Ck1 and second frequency signal CK2
During individual rising edge sampled.
Therefore, at first stage T1, the first parallel output data received by arithmetic unit 38 and the second parallel output number
According to only including two first pixel value L1, L7 and two second pixel value L2, L8, therefore, arithmetic unit 38 cannot be with template
Carry out convolution algorithm so that adder 39 is only capable of receiving first pixel value L7 (b of the output from the first flip-flop 33
Equal to 1), so, first pixel value of the secondary series pixel column of the new image 4 of adder 39 output can be equal to first picture
Element value L7 (referring to Figure 11).
<Second stage T2>
Refering to Fig. 9, when first frequency signal Ck1 transfers rising edge to, pixel value L7 is sampled and is sent to by the 4th flip-flop 36
Arithmetic unit 38, the pixel value L8 to real-time serial for first flip-flop 33 samples and is sent to the input of the 4th flip-flop 36, the
When two frequency signal Ck2 transfer rising edge to, the pixel value L1 to temporary serial for the 3rd flip-flop 35 samples and is sent to arithmetic unit
38, the pixel value L2 to the temporary serial from buffer of the second flip-flop 34 samples and is sent to the defeated of the 3rd flip-flop 35
Entering end, buffer 31 receives and stores the pixel value L8 of real-time serial.
At the same time, the pixel value L9 of real-time serial is sent to the input of the first flip-flop 33, from the picture of buffer
Element value L3 is sent to the input of the second flip-flop 34, to prepare under first frequency signal Ck1 and second frequency signal CK2
One rising edge is sampled.
Therefore, in this second stage T2, the first parallel output data of arithmetic unit 38 reception and the second parallel output data
Include pixel value L1, L2, L3 and pixel value L7, L8, L9 respectively, say, that what arithmetic unit 38 received waits total of pixel value
Number is equal to the coefficient number (a is equal to 6) of template, therefore, it can enter step (C).
The arithmetic unit 38 of processing unit 37 carries out convolution algorithm with template according to six pixel value L1 ~ L3, L7 ~ L9 and produces
Convolution value Δ.
Need to it should be noted that the arithmetic unit 38 of processing unit 37 is that the convolution algorithm formula using (formula 1) is rolled up
Product value Δ.
Convolution value Δ(formula 1)
Wherein, represent the grade pixel value received by arithmetic unit 38 with parameter X1 to X6, and parameter G is corresponding b-th pixel value
The coefficient weights of template, the coefficient number of template is equal to the number waiting pixel value received by arithmetic unit 38, and corresponding b
The coefficient weights of the template of individual pixel value can be higher, in addition, it is noted that the designing points of the coefficient weights of template is all
The coefficient weights of coefficient is added and is equal to zero, therefore, the coefficient weights of G for-[(-1)+(-1)+...+(-1)+(-1)+(-1)] }.
Refering to Fig. 9, second stage T2, second of output output second parallel output data of the first flip-flop 33
Pixel value L8, therefore with second pixel value L8 for main conversion pixel, say, that the template of corresponding second pixel value L8
The value of coefficient weights should be relatively big, with for this example, G as a example by 5 (G={-[(-1)+(-1)+(-1)+(-1)+(-1)] }=
5), therefore, the convolution value Δ of this first embodiment present stage is as shown in (formula 2).
Convolution value Δ
(formula 2)
Additionally explanation, template includes two row coefficient row, and each row coefficient row have three (p-n+1=3-1+1=3) individual coefficient power
Weight, and three coefficient weights ([-1 ,-1 ,-1]) corresponding first parallel output respectively of wherein row coefficient row of two row coefficients row
First pixel value (n=1) of the first row pixel column of data is to the 3rd pixel value (p=3), and two row coefficient row is wherein another
The of the secondary series pixel column of three coefficient weights of one row coefficient row ([-1,5 ,-1]) corresponding second parallel output data respectively
One pixel value (n=1) is to the 3rd pixel value (p=3).
Step (D)：Processing unit 37 carries out addition according to b-th pixel value and the convolution value Δ of the second parallel output data
Computing produces b-th pixel value of (m+1) row pixel column of new image 4, and wherein, n b p, b are positive integer.
The adder 39 of processing unit 37 is according to second pixel value L8 of the second parallel output data (b is equal to 2) and volume
Product value Δ carries out second pixel value M8 (referring to Figure 11) that add operation produces the secondary series pixel column of new image 4.
Step (E)：Processing unit 37 judges whether the existing numerical value of p is equal to N, if so, then completes (the m+ of new image 4
1) image procossing of row pixel column, if it is not, then enter step (F).
The processor of processing unit 37 judges only to receive first pixel of first row pixel column and secondary series pixel column
Value is to the 3rd pixel value, and therefore, processing unit 37 judges that the existing numerical value (p=3) of p is not equal to N (N=6), and does not also complete the
Six pixel values of two row pixel columns, enter step (F).
Step (F)：The existing numerical value of n is added 1 as next numerical value by processing unit 37, and the existing numerical value of p adds 1 as next
Numerical value, returns to step (A).
The existing numerical value of n is added 1 (n=1+1) by processing unit 37, and the existing numerical value of p adds 1 (P=3+1), and repeats
Step (A) is to step (E), and follow-up start is same as described above, does not repeats them here, until the processing unit 37 of step (E) judges p
Existing numerical value be equal to N (N=6), then complete the image procossing of the secondary series pixel column of new image 4, and enter step (G).
Step (G)：Processing unit 37 judges whether the existing numerical value of m is equal to（M-1）, if so, then complete the figure of new image 4
As processing, if it is not, then enter step (H).
Step (H)：Existing for m numerical value is added 1 as next numerical value by processing unit 37, and next numerical value of n is equal to 1, returns to
Step (A).
The processor of processing unit 37 judges that the existing numerical value of m is only equal to 2, is not yet equal to (M-1) (M=6), i.e. at expression
Reason unit 37 is only completed the image procossing of the 3rd row pixel column of new image 4, does not also complete the image procossing of six row pixel columns, enters
To step (H) the existing numerical value of m added 1 (m=2+1) as next numerical value, and next numerical value of n is equal to 1, and returns to step (A)
Transformation from serial to parallel output unit 32 continues to the temporary serial (referring to Figure 10) from buffer 31, and wherein, temporary serial is
First pixel value (n=1) of secondary series pixel column is to the 3rd pixel value (p=3) L7 ~ L9, and follow-up start is same as described above,
This repeats no more, until the processor of step (G) judges that the existing numerical value of m is equal to M-1 (M=6), then completes the image of new image 4
Process.
Additionally explanation is that the coefficient weights of the template of above-described embodiment can alsoThis kenel presents, this
When the coefficient weights of G be 3 (G={-[(-1)+(-1)+(-1)] }), but be not limited, can be according to actual state designed, designed.
Refering to Figure 12, the second embodiment of image processing apparatus of the present invention is similar to first embodiment, and difference is,
Also comprise step (A1) before the step (A) of the image processing method performed by the second embodiment to step (A6), and with step
(A1) replaces the step (A1) of first embodiment to step (A6), and the arithmetic unit 38 of processing unit 37 also stores another template,
Another template has three (1 × 3) coefficient number, and is used for processing at the image of the first row pixel column (m is equal to 1) of image 11
Reason.
Step (A1)：Transformation from serial to parallel output unit 32 receives the real-time serial of self imaging 11, and real-time serial includes string
The nth pixel value of the m row pixel column of row arrangement is to q-th pixel value, and transformation from serial to parallel output unit 32 is by real-time serial
Being converted into the 3rd parallel output data, the 3rd parallel output data includes the nth pixel value of the m row pixel column of parallel arranged
To q-th pixel value, wherein, 2+n q N, and q is positive integer.
Step (A6)：Buffer 31 received in sequence simultaneously stores the nth pixel value of m row pixel column of real-time serial to
Q pixel value.
Step (A2)：Processing unit 37 receives the 3rd parallel output data from transformation from serial to parallel output unit 32, and
3rd parallel output data and another template being carried out convolution algorithm and producing another convolution value Δ 1, wherein, another template includes one
Row coefficient arranges, and each row coefficient row have (q-n+1) individual coefficient weights, and (q-n+1) individual coefficient weights of row coefficient row is respectively
The nth pixel value of the m row pixel column of corresponding 3rd parallel output data is to q-th pixel value.
Step (A3)：Processing unit 37 is carried out according to b-th pixel value and the another convolution value Δ 1 of the 3rd parallel output data
Add operation produces b-th pixel value of the m row pixel column of new image 4.
At this for step (A1), step (A6), step (A2) and step (A3) with phase III T3 and fourth stage T4
It is illustrated.
<Phase III T3>
Refering to Figure 13, when first frequency signal Ck1 transfers rising edge to, the first flip-flop 33 included by real-time serial first
First pixel value L1 (n is equal to 1) of row pixel column (m is equal to 1) samples and is sent to the input of the 4th flip-flop 36, now
Second frequency signal Ck2 still maintain low level not change, therefore, the second flip-flop 34 can't be to from buffer 31
Temporary serial is sampled, and buffer 31 receives and store first pixel value L1 of the first row pixel column of real-time serial.
At the same time, the pixel value L2 of real-time serial is sent to the input of the first flip-flop 33, to prepare in the first frequency
The next rising edge of rate signal Ck1 is sampled.
Therefore, at this phase III T3, arithmetic unit 38 receives the 3rd parallel output data and only includes first pixel value
Second pixel value L2 of the first row pixel column of L1 and real-time serial, therefore arithmetic unit 38 cannot carry out convolution with another template
Computing so that adder 39 is only capable of receiving first pixel value L1 (b is equal to 1) of the output from the first flip-flop 33,
So, first pixel value of the first row pixel column of the new image 4 of adder 39 output can be equal to first of image 11
Pixel value L1 (refers to Figure 15).
<Fourth stage T4>
Refering to Figure 14, when first frequency signal Ck1 transfers rising edge to, first pixel to real-time serial for the 4th flip-flop 36
Value L1 samples and is sent to arithmetic unit 38, the first flip-flop 33 to real-time serial second pixel value of first row pixel column
L2 samples and is sent to the input of the 4th flip-flop 36, and second frequency signal Ck2 now still maintains low level not change,
Therefore, the temporary serial from buffer 31 can't be sampled by the second flip-flop 34, and buffer 31 receives and stores
Second pixel value L2 of the first row pixel column of real-time serial.
At the same time, to be sent to first positive and negative for the 3rd the pixel value L3 (p be equal to 3) of the first row pixel column of real-time serial
The input of device 33, sampled with the next rising edge preparing in first frequency signal Ck1.
Therefore, in this fourth stage T4, arithmetic unit 38 receive the 3rd parallel output data be by first pixel value L1,
Second pixel value L2 and the 3rd pixel value L3 is formed, say, that the total number waiting pixel value that arithmetic unit 38 receives
(first pixel value L1, second pixel value L2 and the 3rd pixel value L3) be equal to another template coefficient number (a is equal to
3), therefore, the arithmetic unit 38 of processing unit 37 can (first pixel value be to the 3rd pixel according to the 3rd parallel output data
Value L1 ~ L3) and another template carry out convolution algorithm and produce another convolution value Δ 1.
It is noted that the coefficient weights of another template of this second embodiment is respectively, therefore, the coefficient weights of G is 2
(G={-[(-1)+(-1)] }), so the another convolution value Δ 1 of step (A2) is as shown in (formula 3).
Another convolution value Δ 1(formula 3)
Step (A3)：Processing unit 37 carries out addition according to b-th pixel value and the another convolution value Δ 1 of the 3rd parallel output data
Computing produces b-th pixel value of the m row pixel column of new image 4.
The adder 39 of processing unit 37 is according to second pixel value L2 (b=2) of the 3rd parallel output data and another volume
Product value Δ 1 carries out second pixel value M2 (referring to Fig. 3 and Fig. 4) that add operation produces the first row pixel column of new image 4.
Step (A4)：Processing unit 37 judges whether the existing numerical value of q is equal to N, if so, then completes the m row of new image 4
The image procossing of pixel column simultaneously enters step (A), if it is not, then enter step (A5).
Processing unit 37 judges that the existing numerical value (q=3) of q is not equal to N (N=6), and does not also complete the six of first row pixel column
Individual pixel value, enters step (A5).
Step (A5)：The existing numerical value of n is added 1 as next numerical value by processing unit 37, the existing numerical value of q add 1 as under
One numerical value, returns to step (A1).
The existing numerical value of n is added 1 (n=1+1) by processing unit 37, and the existing numerical value of q adds 1 (q=3+1), and returns to step
(A1) repeating, follow-up start is same as described above, does not repeats them here, until the processing unit 37 of step (A4) judges q's
Existing numerical value is equal to N (N=6), the then image procossing of the first row pixel column of complete new image 4, and enters step (A) and continue to repeat
Perform the action of first embodiment.
In sum, above-described embodiment has following two advantages：
1. only need buffer 31：Image processing module 3 only needs buffer 31 to store n-th of m row pixel column of image 11
Pixel value is stored in the m row picture of buffer 31 to p-th pixel value, recycling transformation from serial to parallel output unit 32 received in sequence
N number of pixel value of element row, and simultaneously sequentially the nth pixel value of (m+1) row pixel column of real-time reception image 11 to p-th
Pixel value, and according to the nth pixel value of received m row pixel column to p-th pixel value, (m+1) row pixel column
Nth pixel value carry out convolution algorithm to p-th pixel value and template and produce new image 4, thereby reach to detect water simultaneously
Flat border and effect of vertical boundary, can make again new image 4 reach the sharpened effect of certain level and be applicable to driver
Or touch chip (touch IC) (driver).
2. the storage area of buffer 31 reduces：Due to the technological means of color gamut conversion, the buffer of image processing apparatus 1
The 31 L values (brightness) only storing each pixel, and every buffer 31 of existing image processing module 3 stores each pixel mostly
R value (red), G value (green) and B value (blue), it is clear that the storage required for buffer 31 of image processing apparatus 1 of the present invention
The buffer depositing the more existing image processing module in space decreases the space of about 2/3rds.
Therefore, image processing method of the present invention can realize detecting horizontal boundary in the way of reducing hardware storage area simultaneously
And vertical boundary, sharpened effect of certain level can be reached again, and really reach the purpose of the present invention.
Only as described above, only embodiments of the invention, when can not with this limit the present invention implement scope, all
It is that the simple equivalence made according to scope of the present invention patent and patent specification content changes and modifies, all still belong to the present invention
In the range of patent covers.
Claims (10)
1. an image processing method, is performed by image processing apparatus, and this image processing apparatus comprises image processing module, image
Processing module includes receiving the buffer of image, receives image and electrically connect the transformation from serial to parallel output unit of buffer, and electricity
Connecting the processing unit of transformation from serial to parallel output unit, wherein, image includes M row pixel column, and each row pixel column includes N number of picture
Element is worth, and 2 M, 3 N, and M, N are positive integer, and image processing method comprises：
Transformation from serial to parallel output unit receives the temporary serial data from buffer, and temporary serial data includes serial arrangement
Temporary serial data is converted into by the nth pixel value of m row pixel column to p-th pixel value, transformation from serial to parallel output unit
First parallel output data, the first parallel output data includes the nth pixel value of the m row pixel column of parallel arranged to pth
Individual pixel value, wherein, 2 p-n, p N, 1 m M-1,1 n N-2, and p, m, n be positive integer；
Transformation from serial to parallel output unit receives the real-time serial data of self imaging, and real-time serial data include the of serial arrangement
(m+1) the nth pixel value of row pixel column is to p-th pixel value, and real-time serial is converted into by transformation from serial to parallel output unit
Two parallel output data, the second parallel output data includes the nth pixel value of (m+1) row pixel column of parallel arranged to
P pixel value；
Processing unit receives the first parallel output data and the second parallel output data from transformation from serial to parallel output unit, and
First parallel output data and the second parallel output data are carried out convolution algorithm with a template and produce convolution value, wherein, mould
Plate includes two row coefficient row, and each row coefficient row have (p-n+1) individual coefficient weights, and a wherein row coefficient of two row coefficients row
The nth pixel value of (p-n+1) individual coefficient weights of row m row pixel column of corresponding first parallel output data respectively is to pth
Individual pixel value, and (p-n+1) individual coefficient weights correspondence second respectively of wherein another row coefficient row of two row coefficient row is defeated parallel
Go out the nth pixel value of (m+1) row pixel column of data to p-th pixel value；
Processing unit carries out add operation produce new image according to b-th pixel value and the convolution value of the second parallel output data
B-th pixel value of (m+1) row pixel column, wherein, n b p.
2. image processing method as claimed in claim 1, also comprises:
Processing unit judges whether the existing numerical value of p is equal to N, if so, then completes the image of (m+1) row pixel column of new image
Process, if it is not, then enter step (F),
The existing numerical value of n is added 1 as next numerical value by processing unit, and the existing numerical value of p adds 1 as next numerical value, returns to step
(A).
3. image processing method as claimed in claim 2, wherein, when the existing numerical value that step (E) judges p is equal to N, step
(E) also comprise after:
Processing unit judges whether the existing numerical value of m is equal to（M-1）, if so, then complete the image procossing of new image, if it is not, then
Enter step (H),
Existing for m numerical value is added 1 as next numerical value by processing unit, and next numerical value of n is equal to 1, returns to step (A).
4. image processing method as claimed in claim 1, wherein, also comprises between step (B) and step (C):
Buffer received in sequence simultaneously stores the nth pixel value of m+1 row pixel column of real-time serial data to p-th pixel
Value.
5. image processing method as claimed in claim 1, wherein, also comprises before step (A):
(A1) buffer received in sequence the real-time serial data storing image, and real-time serial data are converted into temporary serial
Data, wherein, real-time serial data include the nth pixel value of the m row pixel column of serial arrangement to p-th pixel value.
6. image processing method as claimed in claim 1, wherein, also comprises before step (A):
(A1) transformation from serial to parallel output unit receives the real-time serial data of self imaging, and real-time serial data include serial arrangement
The nth pixel value of m row pixel column to q-th pixel value, real-time serial data are changed by transformation from serial to parallel output unit
Becoming the 3rd parallel output data, the 3rd parallel output data includes the nth pixel value of the m row pixel column of parallel arranged to
Q pixel value, wherein, 2+n q N, and q is positive integer,
(A2) processing unit receives the 3rd parallel output data from transformation from serial to parallel output unit, and by the 3rd parallel output
Data and another template carry out convolution algorithm and produce another convolution value, wherein, another template be used for making image sharpened it
Processing and detecting simultaneously horizontal boundary, and include row coefficient row, each row coefficient row have (q-n+1) individual coefficient weights,
And the nth pixel of (q-n+1) individual coefficient weights of row coefficient row m row pixel column of corresponding 3rd parallel output data respectively
It is worth to q-th pixel value,
(A3) processing unit carries out add operation produce new according to b-th pixel value and the another convolution value of the 3rd parallel output data
B-th pixel value of the m row pixel column of image,
(A4) processing unit judges whether the existing numerical value of q is equal to N, if so, then completes the image of the m row pixel column of new image
Process and enter step (A), if it is not, then enter step (A5),
(A5) the existing numerical value of n is added 1 as next numerical value by processing unit, and the existing numerical value of q adds 1 as next numerical value, returns to
Step (A1).
7. image processing method as claimed in claim 6, wherein, also comprises between step (A1) and step (A2):
(A6) buffer received in sequence store the nth pixel value of m row pixel column of real-time serial to q-th pixel value.
8. an image processing apparatus, comprises image processing module, and image processing module receives image, and image includes M row pixel
Row, each row pixel column includes that N number of pixel value, wherein, 2 M, 3 N, and M, N are positive integer, and image processing module comprises:
Buffer, is converted into temporary serial in order to received in sequence the real-time serial storing self imaging, and real-time serial includes
The nth pixel value of the m row pixel column of serial arrangement is to p-th pixel value, and (m+1) row pixel column of serial arrangement
Nth pixel value is to p-th pixel value, and temporary serial includes the nth pixel value of the m row pixel column of serial arrangement to the
P pixel value, wherein, 2 p-n, p N, 1 m M-1,1 n N-2, and p, m, n be positive integer；
Transformation from serial to parallel output unit, electrical connection buffer is to receive the temporary serial of buffer, and temporary serial includes that serial is arranged
The nth pixel value of the m row pixel column of row, to p-th pixel value, also receives the real-time serial of self imaging, real-time serial bag
The nth pixel value of (m+1) the row pixel column including serial arrangement is incited somebody to action temporarily to p-th pixel value, transformation from serial to parallel output unit
Deposit serial and real-time serial is converted into the first parallel output data and the second parallel output data respectively；
Processing unit, electrical connection transformation from serial to parallel output unit is to receive the first parallel output data and the second parallel output number
According to, and the first parallel output data and the second parallel output data are carried out convolution algorithm with a template and produce convolution value, then
B-th pixel value according to the second parallel output data and convolution value carry out (m+1) row picture that add operation produces new image
B-th pixel value of element row, wherein, template includes two row coefficient row, and each row coefficient row have (p-n+1) individual coefficient weights,
And two m of (p-n+1) individual coefficient weights respectively corresponding first parallel output data of wherein row coefficient row of row coefficient row
The nth pixel value of row pixel column is to p-th pixel value, and (p-n+1) of wherein another row coefficient row of two row coefficient row is individual
The nth pixel value of coefficient weights respectively (m+1) row pixel column of corresponding second parallel output data to p-th pixel value,
Wherein, n b p, b are positive integer.
9. image processing apparatus as claimed in claim 8, wherein, transformation from serial to parallel output unit includes:
First flip-flop, has an input, an output, and a frequency input, the input of the first flip-flop
Carry out the real-time serial of self imaging for received in sequence, and the frequency input of the first flip-flop be used for receiving first frequency signal,
When first frequency signal transfers rising edge to, pixel value sampling received by its input for first flip-flop, and be sent to
Its output,
Second flip-flop, has an input, an output, and a frequency input, the input of the second flip-flop
Electrical connection buffer is being used for receiving temporary serial, and the frequency input of the second flip-flop is used for receiving second frequency signal,
When second frequency signal transfers rising edge to, pixel value sampling received by its input for second flip-flop, and be sent to
Its output,
3rd flip-flop, has an input, an output, and a frequency input, the input of the 3rd flip-flop
Electrically connect the output of the second flip-flop, the output electrical connection processing unit of the 3rd flip-flop, and the frequency of the 3rd flip-flop
The frequency input of input electrical connection the second flip-flop is to be used for receiving second frequency signal, when second frequency signal transfers to
When rising edge, pixel value sampling received by its input for the 3rd flip-flop, and it is sent to its output,
4th flip-flop, has an input, an output, and a frequency input, the output of the 3rd flip-flop
Electrical connection processing unit, the output of input electrical connection first flip-flop of the 4th flip-flop, and the frequency of the 4th flip-flop
The frequency input of input electrical connection the first flip-flop is to be used for receiving first frequency signal, when first frequency signal transfers to
When rising edge, pixel value sampling received by its input for the 4th flip-flop, and it is sent to its output.
10. image processing apparatus as claimed in claim 8, wherein, processing unit includes:
One arithmetic unit, stores template, and electrically connects transformation from serial to parallel output unit to receive the first parallel output data and the
Two parallel output data, and carry out convolution algorithm according to the first parallel output data, the second parallel output data and template and produce
Raw convolution value, wherein, template is used for doing sharpened process to image and can detect horizontal boundary and vertical boundary simultaneously, and wraps
Including two row coefficient row, each row coefficient arranges has (p-n+1) individual coefficient weights, and wherein row coefficient row of two row coefficients row
(p-n+1) the nth pixel value of the individual coefficient weights m row pixel column of corresponding first parallel output data respectively is to p-th picture
Element value, and (p-n+1) individual coefficient weights corresponding second parallel output number respectively of wherein another row coefficient row of two row coefficient row
According to the nth pixel value of (m+1) row pixel column to p-th pixel value, and
One adder, electrical connection transformation from serial to parallel output unit and arithmetic unit are to receive the of the second parallel output data respectively
B pixel value and convolution value, and carry out add operation to produce the multiple row pixel of new image according to b-th pixel value and convolution value
One of them pixel value of multiple pixel values of wherein row of row, wherein, n b p.
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