CN106443180A - Self-adaptive high-precision frequency measuring method for gate and measuring device - Google Patents
Self-adaptive high-precision frequency measuring method for gate and measuring device Download PDFInfo
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- CN106443180A CN106443180A CN201610981945.5A CN201610981945A CN106443180A CN 106443180 A CN106443180 A CN 106443180A CN 201610981945 A CN201610981945 A CN 201610981945A CN 106443180 A CN106443180 A CN 106443180A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
- G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
- G01R23/10—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage by converting frequency into a train of pulses, which are then counted, i.e. converting the signal into a square wave
Abstract
The invention discloses a self-adaptive high-precision frequency measuring method for a gate. The method comprises the steps that analog signals enter a signal conditioning device through the signal input end and are converted into digital signals through the signal conditioning device, and the digital signals are transmitted to a programmable logic device FPGA; a flipping operation is conducted on a two-divided-frequency register by taking the input signals as a clock, an edge detector is driven by a system clock to detect the flipping state of the register, and counting of edge signals can be equivalent to counting of the input signals; when it is detected that the count of the system clock is larger than the data refreshing frequency and a value in an edge signal counter is larger than or equal to 1, a measuring controller updates the value of the edge signal counter and a value of a system clock counter to a measuring output register by taking the edge signals as enable signals of the measuring controller and resets the edge signal counter and the system clock counter to make preparations for next measurement. According to the method, the measuring precision can be improved to the maximum limit, and the total-range measuring precision is completely same.
Description
Technical field
The present invention relates to detection field, particularly to a kind of measurement valve adaptive High Precision Frequency method, and
Implement the measurement apparatus of this measurement valve adaptive High Precision Frequency method.
Background technology
In prior art, based on the frequency measurement of wide scope, such as frequency, by 0.1Hz to 200MHz, frequency measurement is divided into
High band frequency measurement, low-frequency range survey week.But the certainty of measurement at separation is inconsistent, due to the difference of reconnaissance, there is possibility high
Frequency range or low-frequency range high precision.
The certainty of measurement of this metering system also has room for promotion.
And there is blind area in this metering system, the signal measurement of certain section of time interval less than.
In addition, the measurement that user sets pounds the door, time or measurement refresh time are unreasonable, lead to measurement result to be random value.
The PLDs such as FPGA, CPLD are that digital signal is processed, and have been several during hence into FPGA
Word signal.The temporal resolution of PLD is determined by system clock, usually hundreds of megahertz, if measurement
The frequency of signal is it is clear that the temporal resolution of PLD FPGA in the order of magnitude of million, 10,000,000,100,000,000 even more highs
It is far from being enough, the common practice in order to improve certainty of measurement is to measure repeatedly to average.
Due to design measurement frequency by 0.1Hz to 200MHz, do the average time change scope of n times be N* [5ns,
10s], time span is very big, not using meaning, so universal implementation is measurement signal in certain measurement pounds the door the time
Periodicity.But this scheme has two defects：First is not integer in the pound the door number of times of interior appearance of current time, such as 10.5
In the individual cycle, error now is just than larger；The threshold value of the second setting is less than normal than actual signal, then do not detect correct signal frequency
Rate.
Content of the invention
It is an object of the invention to, for the problems referred to above, provide a kind of measurement adaptive High Precision Frequency of gate
Method.
The present invention also aims to, a kind of enforcement aforementioned measurement gate adaptive High Precision Frequency method is provided
Measurement apparatus.
The technical scheme that the present invention is adopted for achieving the above object is：
A kind of measurement gate adaptive High Precision Frequency method, it comprises the following steps：
(1), setting signal regulating device, PLD FPGA, control device, power supply and display interactive component,
This signal regulating device connect signal input part, this signal regulating device, power supply and control device respectively with this FPGA
Device FPGA connects, and this control device is connected with display interactive component；
(2) analogue signal passes through signal input part entering signal conditioning device, is converted to numeral through signal regulating device
Signal is simultaneously delivered to PLD FPGA；
(3) digital signal enters PLD FPGA, one two divided-frequency is deposited with this input signal for clock
Device does turning operation, and the signal intensity cycle of this two divided-frequency depositor is the half of input signal, change upset frequency with defeated
Enter signal consistent, the then rollover states of marginal detector detected register under the driving of system clock, edge signal is each
Export a clock high level along marginal detector, can equivalent count input signal to the counting of edge signal；
(4) using edge signal as the enable signal of Mersure Controler, Mersure Controler detects system clock and counts greatly
When numerical value is more than or equal to 1 in Refresh Data frequency and in margin signal enumerator, during by edge signal enumerator with system
The value of clock enumerator updates in measurement output register, and reset edge event counter and system clock counter simultaneously is
Next time, measurement was prepared.
It is further comprising the steps of：
(5) it is less than measurement thresholding without signal input or signal frequency, the count value of system clock counter can surpass
Cross the measurement overflow value in operational factor, now measurement result is set to overflow value reset edge event counter and system simultaneously
Clock counter, prepares for measurement next time；To user, measurement overflow status points out that signal amplitude or frequency are less than measurement thresholding
Or signal disconnects.
When this PLD FPGA includes two divided-frequency depositor, marginal detector, edge signal enumerator, system
Clock, Mersure Controler, system clock counter, this two divided-frequency depositor, marginal detector, edge signal enumerator, measurement are defeated
Go out depositor to be sequentially connected, this two divided-frequency depositor, marginal detector, system clock counter, Mersure Controler respectively with this
System clock connects, and this marginal detector is connected with this Mersure Controler, and this system clock counter is deposited with this measurement output
Device connects, and this Mersure Controler is connected with this system clock counter, edge signal enumerator respectively.
This signal regulating device is connected with this Mersure Controler, two divided-frequency depositor respectively；This measurement output register with
This control device connects.
Due to measuring the numerical value self-refresh obtaining, the performance of the uncontrolled device of refreshing frequency and the impact reading delay,
So the frequency of edge signal is not above the frequency of system clock, for the accuracy measuring, the system clock of 250MHz is surveyed
Not above 240MHz, solution is to carry out N times to input signal to divide to amount signal, by the signal input to two points after frequency dividing
Frequency depositor, the measurement result calculating is multiplied by N times.Can connect in the system clock of 250MHz and PLD FPGA
Under the incoming frequency being subject to, the input signal of 200～800MHz is measured, certainty of measurement with do not divide measurement and be consistent.
A kind of measurement apparatus implementing aforementioned measurement gate adaptive High Precision Frequency method, it includes signal and adjusts
Reason device, PLD FPGA, control device, power supply and display interactive component, this signal regulating device connects signal
Input, this signal regulating device, power supply and control device are connected with this PLD FPGA respectively, this control device
It is connected with display interactive component.
When this PLD FPGA includes two divided-frequency depositor, marginal detector, edge signal enumerator, system
Clock, Mersure Controler, system clock counter, this two divided-frequency depositor, marginal detector, edge signal enumerator, measurement are defeated
Go out depositor to be sequentially connected, this two divided-frequency depositor, marginal detector, system clock counter, Mersure Controler respectively with this
System clock connects, and this marginal detector is connected with this Mersure Controler, and this system clock counter is deposited with this measurement output
Device connects, and this Mersure Controler is connected with this system clock counter, edge signal enumerator respectively.
This signal regulating device is connected with this Mersure Controler, two divided-frequency depositor respectively.
This measurement output register is connected with this control device.
Beneficial effects of the present invention are：The present invention can improve certainty of measurement to greatest extent, and gamut certainty of measurement is complete
Identical.Measurement gate time is adjustable, increases timeout threshold, can reflect signal off-state.The continuous self-refresh of measured value, does not survey
Amount dead band.Arbitrarily setting measurement gate time, implementation method can self-adapting signal, and obtain right value.By frequency measurement and survey week two
Plant function to unite two into one, reduce PLD resource overhead and design complexities.
Below in conjunction with the accompanying drawings with embodiment, the present invention is further described.
Brief description
Fig. 1 is the structured flowchart of the present invention.
Specific embodiment
Embodiment：As shown in figure 1, a kind of present invention measurement gate adaptive High Precision Frequency method, it includes
Following steps：
(1), setting signal regulating device, PLD FPGA, control device, power supply and display interactive component,
This signal regulating device connect signal input part, this signal regulating device, power supply and control device respectively with this FPGA
Device FPGA connects, and this control device is connected with display interactive component；
(2) analogue signal passes through signal input part entering signal conditioning device, is converted to numeral through signal regulating device
Signal is simultaneously delivered to PLD FPGA；
(3) digital signal enters PLD FPGA, one two divided-frequency is deposited with this input signal for clock
Device does turning operation, and the signal intensity cycle of this two divided-frequency depositor is the half of input signal, change upset frequency with defeated
Enter signal consistent, the then rollover states of marginal detector detected register under the driving of system clock, edge signal is each
Export a clock high level along marginal detector, can equivalent count input signal to the counting of edge signal；
(4) using edge signal as the enable signal of Mersure Controler, Mersure Controler detects system clock and counts greatly
When numerical value is more than or equal to 1 in Refresh Data frequency and in margin signal enumerator, during by edge signal enumerator with system
The value of clock enumerator updates in measurement output register, and reset edge event counter and system clock counter simultaneously is
Next time, measurement was prepared.
It is further comprising the steps of：
(5) it is less than measurement thresholding without signal input or signal frequency, the count value of system clock counter can surpass
Cross the measurement overflow value in operational factor, now measurement result is set to overflow value reset edge event counter and system simultaneously
Clock counter, prepares for measurement next time；To user, measurement overflow status points out that signal amplitude or frequency are less than measurement thresholding
Or signal disconnects.
When this PLD FPGA includes two divided-frequency depositor, marginal detector, edge signal enumerator, system
Clock, Mersure Controler, system clock counter, this two divided-frequency depositor, marginal detector, edge signal enumerator, measurement are defeated
Go out depositor to be sequentially connected, this two divided-frequency depositor, marginal detector, system clock counter, Mersure Controler respectively with this
System clock connects, and this marginal detector is connected with this Mersure Controler, and this system clock counter is deposited with this measurement output
Device connects, and this Mersure Controler is connected with this system clock counter, edge signal enumerator respectively.
This signal regulating device is connected with this Mersure Controler, two divided-frequency depositor respectively；This measurement output register with
This control device connects.
Due to measuring the numerical value self-refresh obtaining, the performance of the uncontrolled device of refreshing frequency and the impact reading delay,
So the frequency of edge signal is not above the frequency of system clock, for the accuracy measuring, the system clock of 250MHz is surveyed
Not above 240MHz, solution is to carry out N times to input signal to divide to amount signal, by the signal input to two points after frequency dividing
Frequency depositor, the measurement result calculating is multiplied by N times.Can connect in the system clock of 250MHz and PLD FPGA
Under the incoming frequency being subject to, the input signal of 200～800MHz is measured, certainty of measurement with do not divide measurement and be consistent.
A kind of measurement apparatus implementing aforementioned measurement gate adaptive High Precision Frequency method, it includes signal and adjusts
Reason device, PLD FPGA, control device, power supply and display interactive component, this signal regulating device connects signal
Input, this signal regulating device, power supply and control device are connected with this PLD FPGA respectively, this control device
It is connected with display interactive component.
When this PLD FPGA includes two divided-frequency depositor, marginal detector, edge signal enumerator, system
Clock, Mersure Controler, system clock counter, this two divided-frequency depositor, marginal detector, edge signal enumerator, measurement are defeated
Go out depositor to be sequentially connected, this two divided-frequency depositor, marginal detector, system clock counter, Mersure Controler respectively with this
System clock connects, and this marginal detector is connected with this Mersure Controler, and this system clock counter is deposited with this measurement output
Device connects, and this Mersure Controler is connected with this system clock counter, edge signal enumerator respectively.
This signal regulating device is connected with this Mersure Controler, two divided-frequency depositor respectively.
This measurement output register is connected with this control device.
The present invention is applied to a function in signal source, for the impact to measurement result for the removal system clock, with
Lower data is the measured value to output signal of the present invention for the cymometer.
The present invention can improve certainty of measurement to greatest extent, and gamut certainty of measurement is identical.Measurement gate time can
Adjust, increase timeout threshold, signal off-state can be reflected.The continuous self-refresh of measured value, does not have blind area.Arbitrarily setting measurement
Gate time, implementation method can self-adapting signal, and obtain right value.Frequency measurement is united two into one with surveying all two kinds of functions, reduces
PLD resource overhead and design complexities.
The above, be only presently preferred embodiments of the present invention, and not the present invention is made with any pro forma restriction.Appoint
What those of ordinary skill in the art, without departing under technical solution of the present invention ambit, can be utilized the side of the disclosure above
Method and technology contents make many possible variations and modification to technical solution of the present invention, or the equivalent reality being revised as equivalent variations
Apply example.Therefore every content without departing from technical solution of the present invention, the equivalent change made according to the shape of the present invention, construction and principle
Change, all should be covered by protection scope of the present invention.
Claims (9)
1. a kind of measurement gate adaptive High Precision Frequency method is it is characterised in that it comprises the following steps：
(1), setting signal regulating device, PLD FPGA, control device, power supply and display interactive component, this letter
Number conditioning device connects signal input part, this signal regulating device, power supply and control device respectively with this PLD
FPGA connects, and this control device is connected with display interactive component；
(2) analogue signal passes through signal input part entering signal conditioning device, is converted to digital signal through signal regulating device
And it is delivered to PLD FPGA；
(3) digital signal enters PLD FPGA, one two divided-frequency depositor is done with this input signal for clock
Turning operation, the signal intensity cycle of this two divided-frequency depositor is the half of input signal, and the frequency of change upset and input are believed
Number consistent, then rollover states of marginal detector detected register under the driving of system clock, each edgewise of edge signal
Export a clock high level along detector, can equivalent count input signal to the counting of edge signal；
(4) using edge signal as the enable signal of Mersure Controler, Mersure Controler detects system clock and counts more than number
When numerical value is more than or equal to 1 according to refreshing frequency and in margin signal enumerator, by edge signal enumerator and system clock meter
The value of number device updates in measurement output register, and reset edge event counter and system clock counter simultaneously, for next time
Measurement is prepared.
2. measure gate adaptive High Precision Frequency method according to claim 1 it is characterised in that it also includes
Following steps：
(5) it is less than measurement thresholding without signal input or signal frequency, the count value of system clock counter can exceed fortune
Measurement result is now set to overflow value reset edge event counter and system clock simultaneously by the measurement overflow value in line parameter
Enumerator, prepares for measurement next time；To user, measurement overflow status points out that signal amplitude or frequency are less than measurement thresholding or letter
Number disconnect.
3. measure gate adaptive High Precision Frequency method according to claim 1 it is characterised in that this is programmable
Logical device FPGA includes two divided-frequency depositor, marginal detector, edge signal enumerator, system clock, Mersure Controler, is
System clock counter, this two divided-frequency depositor, marginal detector, edge signal enumerator, measurement output register are sequentially connected,
This two divided-frequency depositor, marginal detector, system clock counter, Mersure Controler are connected with this system clock respectively, this side
It is connected along detector with this Mersure Controler, this system clock counter is connected with this measurement output register, this measurement controls
Device is connected with this system clock counter, edge signal enumerator respectively.
4. measure gate adaptive High Precision Frequency method according to claim 3 it is characterised in that this signal is adjusted
Reason device is connected with this Mersure Controler, two divided-frequency depositor respectively；This measurement output register is connected with this control device.
5. according to claim 1 measurement gate adaptive High Precision Frequency method it is characterised in that due to measurement
The numerical value self-refresh obtaining, the performance of the uncontrolled device of refreshing frequency and the impact reading delay, so the frequency of edge signal
Rate not above the frequency of system clock, for the accuracy measuring, the system clock measurement signal of 250MHz not above
240MHz, solution is to carry out N times to input signal to divide, and by the signal input after frequency dividing to two divided-frequency depositor, calculates
The measurement result going out is multiplied by N times.The receptible incoming frequency of system clock and PLD FPGA institute in 250MHz
Under, the input signal of 200～800MHz is measured, certainty of measurement with do not divide measurement and be consistent.
6. a kind of measurement apparatus implementing measurement gate adaptive High Precision Frequency method described in claim 1, it is special
Levy and be：It includes signal regulating device, PLD FPGA, control device, power supply and display interactive component, this letter
Number conditioning device connects signal input part, this signal regulating device, power supply and control device respectively with this PLD
FPGA connects, and this control device is connected with display interactive component.
7. according to claim 6 measurement apparatus it is characterised in that this PLD FPGA includes two divided-frequency and deposits
Device, marginal detector, edge signal enumerator, system clock, Mersure Controler, system clock counter, this two divided-frequency is deposited
Device, marginal detector, edge signal enumerator, measurement output register are sequentially connected, this two divided-frequency depositor, Edge check
Device, system clock counter, Mersure Controler are connected with this system clock respectively, and this marginal detector is with this Mersure Controler even
Connect, this system clock counter is connected with this measurement output register, this Mersure Controler respectively with this system clock counter,
Edge signal enumerator connects.
8. according to claim 7 measurement apparatus it is characterised in that this signal regulating device respectively with this Mersure Controler,
Two divided-frequency depositor connects.
9. according to claim 7 measurement apparatus it is characterised in that this measurement output register is connected with this control device.
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| CN201610981945.5A CN106443180B (en) | 2016-11-09 | 2016-11-09 | High-precision frequency measuring method and device for measuring self-adaption of gate |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018188228A1 (en) * | 2017-04-13 | 2018-10-18 | 中国电子科技集团公司第二十四研究所 | High-precision frequency measuring system and method |
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| US5920216A (en) * | 1997-04-03 | 1999-07-06 | Advanced Micro Devices, Inc. | Method and system for generating digital clock signals of programmable frequency employing programmable delay lines |
| JP2014002105A (en) * | 2012-06-20 | 2014-01-09 | Yokogawa Electric Corp | Physical quantity measurement device, physical quantity measurement method |
| CN103837741A (en) * | 2014-03-12 | 2014-06-04 | 河南科技大学 | Equal-precision frequency testing system based on FPGA and design method thereof |
| CN203929885U (en) * | 2014-03-12 | 2014-11-05 | 河南科技大学 | Based on FPGA etc. precision frequency testing system |
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2016
- 2016-11-09 CN CN201610981945.5A patent/CN106443180B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5920216A (en) * | 1997-04-03 | 1999-07-06 | Advanced Micro Devices, Inc. | Method and system for generating digital clock signals of programmable frequency employing programmable delay lines |
| JP2014002105A (en) * | 2012-06-20 | 2014-01-09 | Yokogawa Electric Corp | Physical quantity measurement device, physical quantity measurement method |
| CN103837741A (en) * | 2014-03-12 | 2014-06-04 | 河南科技大学 | Equal-precision frequency testing system based on FPGA and design method thereof |
| CN203929885U (en) * | 2014-03-12 | 2014-11-05 | 河南科技大学 | Based on FPGA etc. precision frequency testing system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018188228A1 (en) * | 2017-04-13 | 2018-10-18 | 中国电子科技集团公司第二十四研究所 | High-precision frequency measuring system and method |
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