CN106411316B - A kind of look-up table process mapping method - Google Patents
A kind of look-up table process mapping method Download PDFInfo
- Publication number
- CN106411316B CN106411316B CN201610805256.9A CN201610805256A CN106411316B CN 106411316 B CN106411316 B CN 106411316B CN 201610805256 A CN201610805256 A CN 201610805256A CN 106411316 B CN106411316 B CN 106411316B
- Authority
- CN
- China
- Prior art keywords
- logic
- ring
- look
- combinational
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
- H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
Abstract
The invention discloses a kind of look-up table process mapping methods, which comprises when determining logic circuit, there are one end circuit connections when combinational logic ring, disconnected between the first logic gate and the second logic gate that constitute combinational logic ring in logic circuit；It is inserted into external input in the first input end that the first logic gate is disconnected, is exported outside the second output terminal insertion that the second logic gate is disconnected；Look-up table mapping is carried out to the logic circuit after open combinations logic box；Restore the combinational logic ring in logic circuit, and deletes external input and external output.There are one end circuit connections when combinational logic ring, first having in disconnection composition combinational logic ring between the first logic gate and the second logic gate in determining logic circuit, and are disconnecting place, are inserted into external input respectively and outside exports.Then lookup mapping is carried out to the logic circuit after open combinations logic box.Look-up table mapping is carried out to the logic circuit comprising combinational logic ring in this way, realizing.
Description
Technical field
The present invention relates to electronic technology field more particularly to a kind of look-up table process mapping methods.
Background technique
((Field-Programmable Gate Array, abbreviation FPGA) is a kind of with rich to field programmable gate array
The logical device of rich hardware resource, powerful parallel processing capability and flexible configurability.These features make FPGA in data
Many fields such as processing, communication, network are more and more widely used.As FPGA is using more and more extensive, for
Requirement on devices on fpga chip is also higher and higher.It is become increasingly complex using the design of fpga chip, what combinational logic ring occurred
Also more and more frequently, therefore, the requirement to the complex optimum ability of FPGA is higher and higher for frequency.Traditional Technology Mapping process
In, it is that handled logic circuit can be abstracted as a directed acyclic graph by the premise that logic gates is mapped as look-up table.And
In the actual process, combinational logic ring is frequently present in logic circuit, specific as shown in Figure 1, these combinational logic rings go out
It is existing, unnecessary trouble is brought to look-up table mapping, therefore, finds a kind of logic electricity being capable of handling comprising combinational logic ring
The method on road equivalent can be abstracted as directed acyclic graph, be a problem to be solved.
Summary of the invention
To solve the above-mentioned problems, the present invention provides a kind of look-up table process mapping method.
In a first aspect, the present invention provides a kind of look-up table process mapping methods, which comprises
When determining logic circuit, there are when combinational logic ring, disconnect the first logic that combinational logic ring is constituted in logic circuit
One end circuit connection between door and the second logic gate；
It is inserted into external input in the first input end that the first logic gate is disconnected, and is disconnected in the second logic gate
The external output of second output terminal insertion of connection, wherein external input and external output are equivalent to the first defeated of the first logic gate
Enter the output of the input at end or the second output terminal of the second logic gate；
Look-up table mapping is carried out to the logic circuit after open combinations logic box；
Restore the combinational logic ring in logic circuit, and deletes external input and external output.
Preferably, one end between the first logic gate and the second logic gate that constitute combinational logic ring in logic circuit is disconnected
Before circuit connection, this method further include: traversal logic circuit searches the combinational logic ring in logic circuit.
Look-up table process mapping method provided by the invention, there are when combinational logic ring in determining logic circuit, first
One end connection constituted in combinational logic ring between the first logic gate and the second logic gate is disconnected, and is disconnecting place, point
It Cha Ru not external input and external output.Then lookup mapping is carried out to the logic circuit after open combinations logic box.By this
Method realizes and carries out look-up table mapping to the logic circuit comprising combinational logic ring.
Detailed description of the invention
Fig. 1 is one in the prior art, and there are the logic circuit structure schematic diagrames of combinational logic ring；
A kind of Fig. 2 look-up table process mapping method flow diagram provided in an embodiment of the present invention；
Fig. 3 is the combinational logic ring in disconnection logic circuit provided in an embodiment of the present invention, and is inserted into external input and outer
The logical construction schematic diagram of portion's output；
Fig. 4 present invention implements to provide, and on the basis of logic circuit shown in Fig. 1, adds respectively in input/output port
Logic circuit structure schematic diagram after entering buffer；
Fig. 5 is the look-up table result schematic diagram obtained after look-up table provided in an embodiment of the present invention maps；
Fig. 6 is deletion external input provided in an embodiment of the present invention output, the look-up table result after restoring combinational logic ring
Schematic diagram.
Specific embodiment
Below by drawings and examples, technical scheme of the present invention will be described in further detail.
A kind of Fig. 2 look-up table process mapping method flow diagram 200 provided in an embodiment of the present invention.As shown in the figure 2, it should
Method includes:
Step 210, when determining logic circuit, there are when combinational logic ring, disconnect composition combinational logic ring in logic circuit
One end circuit connection between first logic gate and the second logic gate.
Specifically, one as shown in Figure 1 deposits there are the logic circuit structure schematic diagram of combinational logic ring when having determined
In combinational logic ring, one end circuit connection between the first logic gate and the second logic gate that constitute in combinational logic ring is broken
It opens.
Step 220, it is inserted into external input in the first input end that the first logic gate is disconnected, and in the second logic
The external output of second output terminal insertion that door is disconnected.
Specifically, external input PI_A is inserted into the first input end that the first logic gate is disconnected, in the second logic
Door is disconnected the external output PO_A of second output terminal insertion of link, specifically as shown in Figure 3.
Reader should be understood that PI_A here and PO_A in fact there is no any practical significance, just hope that explanation will combination
Connection electricity between a terminal circuit in logic box, i.e. the input terminal b of "AND" logic gate A2 and the output end of "AND" logic gate A3
Road disconnects, then the b input terminal of A2 needs to connect an input bus, and the output end of A3 also needs one output of connection always
Line.And the input of external input terminals PI_A and the output of external output end PO_A are exactly equivalent to the b input terminal of logic gate A2
The output of the output end of input or logic gate A3.At this point, logic box has been eliminated, the mapping process of look-up table can be completed
?.Specifically as described in step 230.
Step 230, look-up table mapping is carried out to the logic circuit after open combinations logic box.
Specifically, specific as shown in figure 5, the logic gate A0 and A2 in Fig. 3 are mapped to look-up table (Look-Up- here
Table, abbreviation LUT) on LUT1, and logic gate A0, A1 and A3 are mapped on look-up table LUT2.
Detailed process includes:
Because the logic gate A0 and A2 in Fig. 3 are mapped in the look-up table LUT1 in Fig. 5, logic gate A0 and A2 include altogether
Three input terminals, input terminal D and input terminal C and third input terminal PI_A, three for being respectively mapped to look-up table LUT1 are defeated
Enter end, and output end Q is mapped to the output end of LUT1；
Logic gate A0, A1 and A3 in Fig. 3 are mapped on look-up table LUT2, input included by logic gate A0, A1 and A3
End is input terminal D, and the end input terminal C and Q, output end is NQ and PI_O.
It certainly, is herein only that logic circuit is specifically mapped to the example of look-up table for one, but logic
Circuit can be mapped as different look-up tables according to different combinations, other mapping modes are similar with this example, repeat no more.And
Specifically how according to the look-up table after the determining mapping of a logic circuit, then determined according to the mask value of look-up table, i.e., first
According to the input value in logic circuit, the truth table of a logic circuit output valve is obtained.And this truth table is exactly look-up table
Corresponding mask value.When the input value difference of logic circuit, different output valves can be determined.So according to this output valve
To determine corresponding look-up table.
Certainly, open combinations logic box be exactly in order to realize the mapping of logic circuit to look-up table, complete mapping after,
There is still a need for restore combinational logic ring present in original logic circuit.Therefore, this method further includes step 240.
Step 240, restore combinational logic ring, and delete external input and external output.
Specifically as shown in fig. 6, restoring the combinational logic ring in logic circuit, and delete external input and external output.
Optionally, one between the first logic gate and the second logic gate of combinational logic ring is constituted in disconnecting logic circuit
Before terminal circuit connection, this method further include: step 205, traverse logic circuit, search combinational logic ring.
Detailed process are as follows:
In present specification, only it is illustrated by taking logic circuit shown in FIG. 1 as an example, other logic circuits are similar, this
In repeat no more.
Firstly, it is necessary to explanation, the method for searching combinational logic ring is the typical method in graph theory, each " logic device
A node in part " (hereinafter referring both to block or block unit) all corresponding diagrams (figure in graph theory).Therefore for table
It states conveniently, for the interface of input and output, we insert a buffer respectively, and meaning is exactly that interface is converted into one
Equivalent block, so that the element of search and the team that joins the team out is all block, it can be a figure by problem equivalent conversion
The problem of search.
Therefore, step a initially enters output port difference Buffer insertion bufferblock in logic circuit.Specifically
As shown in Figure 4.Fig. 4 be it is provided in an embodiment of the present invention, on the basis of logic circuit shown in Fig. 1, respectively in input/output terminal
Logic circuit structure schematic diagram after mouth addition buffer.
Firstly, because being that all logic gates are all added to the queue of first in first out searching the thought of combinational logic ring
In A, the block unit of the input and output of each logic gate is then searched, the logic where determining some block unit
Door, when being labeled twice in search procedure, then the logic gate where illustrating the block unit may belong to composition combinational logic
One logic gate of ring.And combinational logic ring is found in order to preferably realize, it is inserted into respectively in input port D and C-terminal
Input buffer, such as it is respectively designated as IBUF0 and IBUF1, and it is inserted into output caching respectively at the end output port Q and NQ
Device, and it is named as OBUF0 and OBUF1.
OBUF0 and OBUF1 are added in fifo queue A, and IBUF0 and IBUF1 are labeled as by step b
checked.The thought for searching combinational logic ring is to find input terminal from output end, so needing IBUF0 and IBUF1 first
Labeled as checked, in order to determine the terminal searched.
It should be understood that label mentioned here be indicate the node and the node fully enter node all
Inspection is completed and determination is not included in any combination logic box, and when fully entering for node all has been labeled as
When checked, then illustrate that the node can be marked as checked.
And hereinafter, it will make referrals to a certain node and be marked as checking, and checking indicate the node (
Logic gate is referred specifically in Fig. 4) and fully entering for the node be visited before node, but even cannot
Enough determine the node whether in combinational logic ring.It and is that one is marked as there are the necessary and sufficient condition of combinational logic ring
The node of checking is accessed again.
Step c takes out buffer OBUF0 according to the principle of first in first out first from fifo queue A, wherein
The block unit of OBUF0 does not have any label, the label Checking including being accessed or examined
Mark checked.So, it is labeled to determine whether the block unit of its input terminal AND gate A2 has first, determines A2's
Block unit also without any label, so, not can determine that OBUF0, can not be by it with the presence or absence of combinational logic ring temporarily
Block unit be labeled as checked, its block unit can only first be marked and be.And A2 is put into queue
In A.
Step d takes out OBUF1 from queue A, similar, and the block unit of OBUF1 did not did any label, and
The input of OBUF1 is AND gate A3, and the block unit of A3 was also without any label was done, then can not temporarily determine
OBUF1 whether there is combinational logic ring, can only temporarily be marked as checking.And OBUF1 is taken out from queue A, and will
Its input A3 is added in queue A.
Step e takes out A2 from queue A because A2 did not do any label, determine its input be AND gate A0 and
AND gate A3.A0 and A3 did not did any processing equally, so, A2 is temporarily labeled as checking, and take out from queue A
A2, and A0 and A3 are added in queue.
Step f, because that include in queue at this time is A3, A0 and A3, here, in order to preferably distinguish, by queue
The A3 being once added is named as A3 (1), and the A3 that second is added is named as A3 (2).According to the sequence of first in, first out, need to take
(1) A3 out, because A3 (1) did not did any processing equally at this time, determine that its input is respectively AND gate A1 and AND gate
A2, because A1 did not do any processing, and A2 is also only labeled as checking, rather than checked, so, equally not
It can determine that whether A3 (1) belongs to the logic gate constituted in combinational logic ring, can only temporarily be marked as checking, and
It is taken out from queue, A1 and A2 are added in queue.
Step g takes out A0 from queue A according to first in first out sequence, because A0 was never done any label,
Determine that its input is IBUF0 and IBUF1, because having distinguished labeled IBUF0 and IBUF1 before is checked, it is possible to
It determines that A0 is not belonging to constitute a logic gate in combinational logic ring, checked can be marked as, it is taken from queue
Out.
Step h takes out A3 (2) from queue, because, before by its labeled checking, and at this time once more
It is removed, then illustrates that A3 (2) belongs to the logic gate constituted in combinational logic ring.I.e. there are combinational logics in the logic circuit
Ring.It is finished at this point, searching.
In order to more convenient reader understanding, make additional remarks again to A3 (1) and A3 (2) here: in above-mentioned steps
In, A3 occurs twice altogether in the queue, and occurring A3 for the first time is that and can be named as A3 (1) in step d, and second
A3 occur is to be denoted as A3 (2) in step e.
So, restore that above all logic gates are added sequence in queue A and should be:
OBF01 and OBF02, A2, A3 (1), A0 and A3 (2).It is patrolled so determining that A0 is not belonging to constitute to combine in step g
After the logic gate for collecting ring, then being taken out the logic gate handled should be (2) A3 according to the sequence of first in first out.
A3 is retrieved in step h.And judges that A3 is labeled checking in the queue, and this time taken
Out, then illustrate that A3 belongs to the logic gate constituted in combinational logic ring.Needed in the logic circuit there are combinational logic ring
The processing of next step is carried out, i.e. elimination combinational logic ring, completes the mapping of look-up table.Specific the step of eliminating combinational logic ring, is
Through being discussed in detail in step 210~220.
In addition, reader should understand that, above-mentioned the lifted lookup combinational logic ring in a specific logic circuit is eliminated
Combinational logic ring completes look-up table mapping, and restores the process of combinational logic ring, only a specific embodiment.
Combinational logic ring is searched in other logic circuits, is eliminated the completion look-up table mapping of combinational logic ring and is restored combinational logic ring
Process with above described in mode it is similar, which is not described herein again.
In addition it is also necessary to explanation, the method for above stating the lookup combinational logic ring of introduction, when it is applied to a tool
When in the logic circuit of body, a combinational logic ring can only be inquired every time.Corresponding, the method for eliminating combinational logic ring is also same
Sample is that every execution is primary, eliminates a combinational logic ring.Therefore, when in a logic circuit there are when multiple combinational logic rings,
It then needs to repeat above-mentioned steps.Until confirm do not have in logic circuit combinational logic ring there are until, and eliminating
After combinational logic ring, then the IBUF of insertion and OBUF removed from logic circuit.
Look-up table process mapping method provided by the invention, there are when combinational logic ring in determining logic circuit, first
It disconnects and constitutes one end circuit connection between the first logic gate and the second logic gate in combinational logic ring in logic circuit, and
Place is disconnected, is inserted into external input and external output respectively.Then the logic circuit after open combinations logic box is looked into
Look for mapping.Look-up table mapping is carried out to the logic circuit comprising combinational logic ring in this way, realizing.
Professional should further appreciate that, described in conjunction with the examples disclosed in the embodiments of the present disclosure
Unit and algorithm steps, can be realized with electronic hardware, computer software, or a combination of the two, hard in order to clearly demonstrate
The interchangeability of part and software generally describes each exemplary composition and step according to function in the above description.
These functions are implemented in hardware or software actually, the specific application and design constraint depending on technical solution.
Professional technician can use different methods to achieve the described function each specific application, but this realization
It should not be considered as beyond the scope of the present invention.
The step of method described in conjunction with the examples disclosed in this document or algorithm, can be executed with hardware, processor
The combination of software module or the two is implemented.Software module can be placed in random access memory (RAM), memory, read-only memory
(ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technical field
In any other form of storage medium well known to interior.
Above-described specific embodiment has carried out further the purpose of the present invention, technical scheme and beneficial effects
It is described in detail, it should be understood that being not intended to limit the present invention the foregoing is merely a specific embodiment of the invention
Protection scope, all within the spirits and principles of the present invention, any modification, equivalent substitution, improvement and etc. done should all include
Within protection scope of the present invention.
Claims (1)
1. a kind of look-up table process mapping method, which is characterized in that the described method includes:
Logic circuit is traversed, the combinational logic ring in the logic circuit is searched；
When determining that logic circuit there are when combinational logic ring, disconnects and constitute the first of the combinational logic ring in the logic circuit
One end circuit connection between logic gate and the second logic gate；
It is inserted into external input in the first input end that first logic gate is disconnected, and in the second logic gate quilt
The external output of second output terminal insertion disconnected, wherein the external input and the external output are equivalent to described the
The output of the second output terminal of the input of the first input end of one logic gate or second logic gate；
Look-up table mapping is carried out to the logic circuit after open combinations logic box；
Restore the combinational logic ring in the logic circuit, and deletes the external input and the external output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610805256.9A CN106411316B (en) | 2016-09-06 | 2016-09-06 | A kind of look-up table process mapping method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610805256.9A CN106411316B (en) | 2016-09-06 | 2016-09-06 | A kind of look-up table process mapping method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106411316A CN106411316A (en) | 2017-02-15 |
| CN106411316B true CN106411316B (en) | 2019-03-05 |
Family
ID=57998761
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610805256.9A Active CN106411316B (en) | 2016-09-06 | 2016-09-06 | A kind of look-up table process mapping method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106411316B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112784511B (en) * | 2019-11-11 | 2023-09-22 | 杭州起盈科技有限公司 | Automatic dismantling method for combinational logic loop |
| CN117250480B (en) * | 2023-11-08 | 2024-02-23 | 英诺达(成都)电子科技有限公司 | Loop detection method, device, equipment and storage medium of combinational logic circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101771408A (en) * | 2010-01-05 | 2010-07-07 | 中国人民解放军信息工程大学 | FPGA hardware element generating method and device |
| US8896344B1 (en) * | 2013-01-04 | 2014-11-25 | Altera Corporation | Heterogeneous programmable device and configuration software adapted therefor |
-
2016
- 2016-09-06 CN CN201610805256.9A patent/CN106411316B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101771408A (en) * | 2010-01-05 | 2010-07-07 | 中国人民解放军信息工程大学 | FPGA hardware element generating method and device |
| US8896344B1 (en) * | 2013-01-04 | 2014-11-25 | Altera Corporation | Heterogeneous programmable device and configuration software adapted therefor |
Non-Patent Citations (2)
| Title |
|---|
| "LUT-based FPGA technology mapping using permissible functions";Takayuki Suyama等;《Proceedings of 9th International Conference on VLSI Design》;20020806;215-218 |
| 可编程逻辑核关键技术研究;谢小东;《中国博士学位论文全文数据库 信息科技辑》;20120615(第06期);13-27 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106411316A (en) | 2017-02-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106411316B (en) | A kind of look-up table process mapping method | |
| US7957384B2 (en) | Multiple virtual local area network databases in a switch with a relational lookup engine | |
| Panda et al. | Cap for networks | |
| CN108228646B (en) | Method and electronic device for accessing data | |
| Lian et al. | Existence of positive solutions for Sturm–Liouville boundary value problems on the half-line | |
| CN104702444A (en) | Method and device for handling ERPS (Ethernet Ring Protection Switching) protocol message | |
| US10048893B2 (en) | Clock/power-domain crossing circuit with asynchronous FIFO and independent transmitter and receiver sides | |
| CN105488237A (en) | Enable signal optimizing method for register based on FPGA (Field Programmable Gate Array) | |
| JP2012165033A (en) | Automotive control system and electronic control unit | |
| Sachs et al. | On Constructive Methods in the Theory of Colour-Critical Graphs: Dedicated To Dr. Tibor Gallai on the Occasion of his 75Th Birthday. | |
| CN104301186A (en) | Method and system for testing correctness of routing forwarding table | |
| CN107463340A (en) | The data-storage system of computer | |
| AU2021339989B2 (en) | Tri-color bitmap array for garbage collection | |
| Roy | Diagnosis and fault equivalence in combinational circuits | |
| Jiang | Multiple positive solutions to singular boundary value problems for superlinear second order ODEs | |
| CN105939204B (en) | Multi-protocols cooperating Interface status method and device | |
| Dickman et al. | 𝑆-sets and 𝑆-perfect mappings | |
| Li et al. | Positive radial solutions for elliptic equations with nonlinear gradient terms on an exterior domain | |
| CN112822242A (en) | Point-to-point network and node communication method and device thereof | |
| CN104330978A (en) | Long-distance JTAG signal transmission device, simulation system and method thereof | |
| Liu et al. | Dirichlet (p, q)-equations with gradient dependent and locally defined reaction | |
| Fang et al. | Automated Field-based Decomposition to Accelerate Model Checking FPGA-based TCP/IP | |
| US20210243159A1 (en) | Persistent device identifier driven compromised device quarantine | |
| CN112751946B (en) | Tunnel establishment method, device, equipment and computer readable storage medium | |
| CN113391986B (en) | Log collection management method and system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20190104 Address after: 901-903, 9th Floor, Satellite Building, 63 Zhichun Road, Haidian District, Beijing Applicant after: Jing Wei Qi Li (Beijing) Technology Co., Ltd. Address before: 100080 Beijing Haidian A62, East of Building No. 27, Haidian Avenue, 4th Floor, A District, Haidian District Applicant before: Beijing deep science and Technology Co., Ltd. |
|
| TA01 | Transfer of patent application right | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |