CN106409741B

CN106409741B - Position measurement based on visible wafer notch

Info

Publication number: CN106409741B
Application number: CN201610613778.9A
Authority: CN
Inventors: 古斯塔沃·G·弗兰肯; 布兰登·森; 彼得·陶拉德; 陈卓智; 理查德·K·莱昂斯; 克里斯汀·迪皮特罗; 克里斯多夫·M·巴特利特
Original assignee: Lam Research Corp
Current assignee: Lam Research Corp
Priority date: 2015-07-30
Filing date: 2016-07-29
Publication date: 2022-04-19
Anticipated expiration: 2036-07-29
Also published as: CN114914184A; KR20170015209A; CN106409741A; KR102662003B1

Abstract

The invention relates to a position measurement based on a visible wafer notch. A wafer alignment system includes an image capture device that captures an image of a wafer positioned on a susceptor. An image analysis module analyzes the image to detect an edge of the wafer and a notch formed at the edge of the wafer and calculates a first edge position and a second edge position corresponding to the edge of the wafer based on a position of the notch. The offset calculation module calculates an angular offset of the wafer based on the first edge position and the second edge position. The system control module controls transfer of the wafer from the susceptor to the processing unit based on the angular offset.

Description

Position measurement based on visible wafer notch

Cross Reference to Related Applications

This application is related to U.S. patent application No.14/813,895, attorney docket No. 3645-1US, filed on 30/7/2015. The entire disclosure of the above-referenced application is incorporated herein by reference.

Technical Field

The present invention relates to substrate processing systems, and more particularly, to a system and method for positioning a semiconductor wafer in a substrate processing system.

Background

The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

A substrate processing system may be used to perform etching and/or other processing of a substrate, such as a semiconductor wafer. Exemplary processes that may be performed on the substrate include, but are not limited to, Plasma Enhanced Chemical Vapor Deposition (PECVD) processes, Chemically Enhanced Plasma Vapor Deposition (CEPVD) processes, physical sputtering vapor deposition (PVD) processes, ion implantation processes, and/or other etching (e.g., chemical etching, plasma etching, reactive ion etching, etc.), deposition and cleaning processes. The substrate may be disposed on a wafer processing pedestal, such as a pedestal in a process chamber of a substrate processing system. By way of example only, during etching, a gas mixture comprising one or more precursors is introduced into the processing chamber and a plasma is energized to etch the substrate.

A load lock (e.g., an inbound load lock or an outbound load lock) or other transfer tool may be used to transfer the semiconductor wafer from an atmospheric environment to a vacuum environment (i.e., from outside the processing chamber to inside the processing chamber) and vice versa. The load lock itself may comprise a vacuum chamber containing a pedestal. The wafer is disposed on (and transferred to and from) the susceptor. For example, the wafer may be transferred from the susceptor to a plating processing unit or other processing unit of a processing chamber in a substrate processing system for deposition, etching, and the like. The susceptor lifts the wafer onto and off of a robot (e.g., an end effector of the robot) that is used to transfer the wafer between the load lock and the processing unit.

Disclosure of Invention

A wafer alignment system includes an image capture device that captures an image of a wafer positioned on a susceptor. An image analysis module analyzes the image to detect an edge of the wafer and a notch formed at the edge of the wafer and calculates a first edge position and a second edge position corresponding to the edge of the wafer based on a position of the notch. The offset calculation module calculates an angular offset of the wafer based on the first edge position and the second edge position. The system control module controls transfer of the wafer from the susceptor to the processing unit based on the angular offset.

A wafer alignment method includes: capturing an image of a wafer positioned on a susceptor; analyzing the image to detect an edge of the wafer and a notch formed at the edge of the wafer; calculating first and second edge positions corresponding to the edge of the wafer based on the positions of the notches; calculating an angular offset of the wafer based on the first position and the second edge position; and controlling transfer of the wafer from the susceptor to a processing unit based on the angular offset.

In particular, some aspects of the invention may be set forth as follows:

1. a wafer alignment system, comprising:

an image capture device that captures an image of a wafer positioned on the susceptor;

an image analysis module that analyzes the image to detect an edge of the wafer and a notch formed at the edge of the wafer, and calculates a first edge position and a second edge position corresponding to the edge of the wafer based on a position of the notch;

an offset calculation module that calculates an angular offset of the wafer based on the first edge position and the second edge position; and

a system control module that controls transfer of the wafer from the pedestal to a processing unit based on the angular offset.

2. The wafer alignment system of clause 1, wherein the first edge position and the second edge position are a predetermined distance from the position of the notch.

3. The wafer alignment system of clause 1, wherein to calculate the angular offset, the offset calculation module compares the first edge position and the second edge position to a third edge position and a fourth edge position.

4. The wafer alignment system of clause 3, wherein the angular offset corresponds to a difference between the first edge position and the third edge position and a difference between the second edge position and the fourth edge position.

5. The wafer alignment system of clause 3, wherein the third edge location and the fourth edge location correspond to an edge of a test wafer.

6. The wafer alignment system of clause 5, wherein the image analysis module calculates the third edge position and the fourth edge position using images taken while the test wafer is disposed at the reference position on the susceptor.

7. The wafer alignment system of clause 5, wherein the first edge location, the second edge location, the third edge location, and the fourth edge location each correspond to coordinates within a field of view of the image capture device.

8. The wafer alignment system of clause 5, further comprising a light source disposed on a side of the wafer opposite the image capture device, wherein the light source is disposed to project light through the wafer toward the image capture device.

9. The wafer alignment system of clause 8, wherein the light source is arranged to illuminate a field of view of the image capture device.

10. A wafer alignment method, comprising:

capturing an image of a wafer positioned on a susceptor;

analyzing the image to detect an edge of the wafer and a notch formed at the edge of the wafer;

calculating a first edge position and a second edge position corresponding to the edge of the wafer based on the position of the notch;

calculating an angular offset of the wafer based on the first edge position and the second edge position; and

controlling transfer of the wafer from the susceptor to a processing unit based on the angular offset.

12. The wafer alignment method of clause 11, wherein the first edge position and the second edge position are a predetermined distance from the position of the notch.

13. The wafer alignment method of clause 11, wherein calculating the angular offset comprises comparing the first and second edge positions to third and fourth edge positions.

14. The wafer alignment method of clause 13, wherein the angular offset corresponds to a difference between the first edge position and the third edge position and a difference between the second edge position and the fourth edge position.

15. The wafer alignment method of clause 13, wherein the third edge location and the fourth edge location correspond to edges of a test wafer.

16. The wafer alignment method of clause 15, further comprising calculating the third edge location and the fourth edge location using images taken while the test wafer is disposed at the reference location on the susceptor.

17. The wafer alignment method of clause 15, wherein the first edge location, the second edge location, the third edge location, and the fourth edge location each correspond to coordinates within a field of view of the image capture device.

18. The wafer alignment method of clause 15, further comprising projecting light through the wafer toward the image capture device using a light source disposed on a side of the wafer opposite the image capture device.

19. The wafer alignment method of clause 18, wherein the light source is arranged to illuminate a field of view of the image capture device.

20. The wafer alignment method of clause 11, further comprising adjusting a loading position of the processing unit based on the angular offset before the wafer is transferred to the processing unit.

Further scope of applicability of the present invention will become apparent from the detailed description, claims and drawings. The detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

Drawings

The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein:

FIG. 1 is a functional block diagram of an exemplary substrate processing system according to the principles of the present invention;

FIG. 2A is a functional block diagram of one example of a substrate processing tool according to the principles of the present invention;

FIG. 2B is an exemplary load lock;

FIG. 3A is an exemplary load lock and camera according to the principles of the present invention;

FIG. 3B is another view of an exemplary load lock and camera in accordance with the principles of the present invention;

FIG. 3C is an exemplary image of a wafer captured in accordance with the principles of the present invention;

FIG. 4 illustrates steps of an exemplary wafer alignment method in accordance with the principles of the present invention;

FIG. 5 is a functional block diagram of an exemplary wafer alignment system according to the principles of the present invention;

FIG. 6A is an exemplary calibration image of a test wafer according to the principles of the present invention;

FIG. 6B is an exemplary image of a misaligned wafer according to the principles of the present invention; and

FIG. 6C is an exemplary comparison of an image of an misaligned wafer with a calibration image in accordance with the principles of the present invention;

in the drawings, reference numbers may be repeated among the figures to indicate similar and/or identical elements.

Detailed Description

A semiconductor wafer (e.g., a 300mm wafer) is positioned on the pedestal of the load lock to be transferred into and out of the process chamber. The wafer is aligned on the susceptor to enable the wafer to be accurately captured and/or transferred using a robot or other tool. Alignment of the wafer is achieved using notches formed at the outer edge of the wafer. Various types of wafer aligners may be used to detect the position of the notch relative to the susceptor as the wafer is rotated (e.g., using a spin chuck comprising the susceptor). For example, the sensor may detect the notch as the wafer is slowly rotated using the chuck. The notch position and wafer offset are calculated based on the detected notch and provided to the robot.

In accordance with the principles of the present invention, a system and method for wafer alignment provides an image capture device (e.g., a camera) to capture an image of a stationary wafer on a susceptor. In particular, the camera captures an image of the edge of the wafer including the notch. An image analysis module analyzes the captured image to locate a notch location and an edge location of the wafer relative to the notch. The offset calculation module calculates an angular offset of the wafer relative to a desired position using the position of the notch and the edge position of the wafer. For example, the desired position may correspond to a calibrated reference position.

Referring now to fig. 1, one example of a substrate processing system 100 for etching using an RF plasma is shown. Substrate processing system 100 includes a process chamber 102, process chamber 102 enclosing other components of substrate processing chamber 102 and containing an RF plasma. The substrate processing chamber 102 includes an upper electrode 104 and a pedestal 106 including a lower electrode 107. The edge coupling ring 103 is supported by a pedestal 106 and is disposed around a substrate 108. One or more actuators 105 may be used to move the edge coupling ring 103. During operation, the substrate 108 is disposed on the pedestal 106 between the upper electrode 104 and the lower electrode 107.

For example only, the upper electrode 104 may include a showerhead 109, and the showerhead 109 introduces and distributes process gas. The showerhead 109 can include a stem that includes one end that is coupled to the top surface of the process chamber. The base portion is generally cylindrical and extends radially outward from the other end of the stem portion at a location spaced from the top surface of the process chamber. The surface or faceplate of the pedestal portion of the showerhead facing the substrate includes a plurality of holes through which the process gas or purge gas flows. Alternatively, the upper electrode 104 may comprise a conductive plate, and the process gas may be introduced in another manner. The lower electrode 107 may be disposed in a non-conductive base. Alternatively, the pedestal 106 may comprise an electrostatic chuck comprising a conductive plate that acts as the lower electrode 107.

An RF generation system 110 generates and outputs an RF voltage to one of the upper electrode 104 and the lower electrode 107. The other of the upper electrode 104 and the lower electrode 107 may be dc grounded, ac grounded, or floating. By way of example only, the RF generation system 110 may include an RF voltage generator that generates an RF voltage that is supplied by the matching and distribution network 112 to the upper electrode 104 and the lower electrode 107. In other examples, the plasma may be induced or generated remotely.

The gas delivery system 130 includes one or more gas sources 132-1, 132-2. The gas source supplies one or more precursors and mixtures thereof. The gas source may also provide a purge gas. Vaporized precursors may also be used. Gas source 132 is connected to manifold 140 by valves 134-1, 134-2, and 134-N (collectively valves 134) and mass flow controllers 136-1, 136-2, and 136-N (collectively mass flow controllers 136). The output of the manifold 140 is fed to the process chamber 102. By way of example only, the output of the manifold 140 is fed to the showerhead 109.

The heater 142 may be connected to a heater coil (not shown) disposed in the susceptor 106. The heater 142 may be used to control the temperature of the susceptor 106 and substrate 108. A valve 150 and pump 152 may be used to pump the reactants from the process chamber 102. The controller 160 can be used to control components of the substrate processing system 100. The controller 160 may also be used to control the actuator 105 to adjust the position of one or more portions of the edge coupling loop 103.

The robot 170 may be used to transfer substrates to and from the susceptor 106. For example, in accordance with the principles of the present invention, the robot 170 may transfer substrates between the susceptor 106 and the load lock 172.

Referring now to fig. 2A, a non-limiting exemplary substrate processing tool 200 (e.g., as provided within substrate processing system 100) includes a transport transfer chamber 220 and a plurality of reactors, each having one or more substrate processing chambers. Substrates 225 enter the substrate processing tool 200 from a pod and/or cassette 223, such as a Front Opening Unified Pod (FOUP). The robot 224 includes one or more end effectors to handle the substrate 225. The pressure of the transfer chamber 220 may be at atmospheric pressure. Alternatively, the transport tote 220 can be under vacuum pressure (with ports acting as slot valves).

The robot 224 moves the substrate 225 from the pod and/or cassette to the load lock 230. For example, the substrate 225 enters the load lock 230 through the port 232 (or isolation valve) and rests on the load lock pedestal 233. The port 232 to the transport loadlock 220 is closed and the load lock 230 is evacuated to the appropriate pressure for transfer. The port 234 is then opened and a substrate is placed by another robot 236 (also having one or more end effectors) in the process transfer chamber 235 through one of the ports 237-1, 237-2, 237-3 (collectively referred to as ports 237) corresponding to the selected reactors 240-1, 240-2, and 240-3 (collectively referred to as reactors 240). Although the load lock 230 is shown with multiple seats and associated ports, in some embodiments, the load lock 230 may include only a single seat and corresponding port. By way of example only, another exemplary load lock structure is shown in FIG. 2B.

A substrate index mechanism 242 may be used to further position the substrate relative to the substrate processing chamber. In some examples, indexing mechanism 242 includes a rotating shaft 244 and a heat transfer plate 246.

In some examples, at least one of the process chambers or stations of the reactor 240 is capable of performing semiconductor processing operations, such as material deposition or etching, sequentially or simultaneously with other stations. In some examples, at least one or more of the stations may perform radio frequency based semiconductor processing operations.

The substrate is moved from one station to the next in the reactor 240 using a substrate index mechanism 242. By way of example only, one or more of the stations of the reactor 240 may be capable of performing RF plasma deposition, etching, or other process steps, depending on the particular implementation of the substrate processing tool 200. In use, the substrate is moved to one or more of the reactors 240, processed, and then returned. As can be appreciated, reducing the handling time per substrate will improve production efficiency and throughput.

In accordance with the principles of the present invention,

robots

224 and 236 transfer substrates to and from load lock 230 under the direction of a controller (e.g., controller 160 as shown in FIG. 1). In particular, each substrate (i.e., wafer) includes a notch to facilitate determining the position (e.g., alignment) of the wafer relative to the base 233 of the load lock 230. Accurate determination of wafer position, in turn, facilitates accurate capture, retrieval, and transfer of wafers (e.g., capture of wafers by robot 236 for transfer from load lock 230 to reactor 240).

Referring now to fig. 3A, 3B, and 3C, an exemplary load lock 300 and camera 304 are arranged to detect the position of a wafer 308 in accordance with the principles of the present invention. Although the structure of the load lock 300 corresponds to the exemplary load lock shown in FIG. 2B, the load lock 300 may have a structure similar to the load lock 230 of FIG. 2A or any other structure. The wafer 308 is disposed on a pedestal 312 (e.g., a cold pedestal) within the load lock 300 (e.g., as placed by a robot or other suitable tool). The camera 304 is positioned (e.g., with the lens of the camera 304 facing upward) to capture an image of a portion of the wafer 308. For example, the camera 304 captures an image of the edge 314 of the wafer 308 (e.g., through a hole that includes a quartz or other type of window 316). The edge of the wafer 308 may be backlit (e.g., using an LED or other light source 320 projected through another window 324 past the edge of the wafer 308 and down toward the camera 304) to illuminate the field of view 328 of the camera 304, as shown in fig. 3C.

As shown in fig. 3C, an exemplary image 332 captured by the camera 304 includes the edge 314 of the wafer 308 within the field of view 328 of the camera 304. The camera 304 (and/or the controller 160 as shown in fig. 1, or other devices or modules as described in more detail below) analyzes the captured image 332 to locate the edge 314 of the wafer 308 and a notch 336 formed on the edge 314 of the wafer 308. For example, the camera 304 may be configured to identify and locate the notch 336 by detecting the curvature of the notch 336 (i.e., the notch profile).

The field of view 328 of the camera 304 may be fixed (i.e., constant) relative to the coordinate system. For example, the coordinate system may correspond to a plurality of X, Y locations within the field of view 328, where the 0, 0 location 340 corresponds to a center point of the field of view 328. The camera 304 positions the target locator box 344 according to the detected position of the notch 336. For example, the target locator box 344 may be calibrated to lock at a location X, Y centered on the detected notch 336 (e.g., according to the detected notch profile). The

edge locator boxes

348 and 352 are positioned at X1, Y1 and X2, Y2, respectively, relative to the X, Y position of the target locator box 344. In other words, based on the X, Y position of the target locator box 344 and the known curvature of the wafer 308 (e.g., based on the known diameter of the wafer 308), the positions X1, Y1 and X2, Y2 are positioned along the edge 314 of the wafer 308 (in the opposite direction) at a fixed distance from the X, Y position of the target locator box 344. For example only, the

edge locator boxes

348 and 352 may be positioned as far away from the target locator box 344 as possible while still within the field of view 328 to maximize accuracy.

For example, during initial calibration using a test wafer that is optimally (e.g., within a desired tolerance) positioned, the target positioner box 344 may be drawn around the notch of the test wafer. In other words, the test wafer is positioned such that the notch of the test wafer is located as closely as possible to correspond to the 0, 0 position of the field of view 328 of the camera 304. In this manner, during calibration, the X, Y location of the target locator box 344 directly corresponds to the location of the notch of the test wafer. The X3, Y3 and X4, Y4 positions of the

edge locator boxes

348 and 352 are selected to be a fixed distance along the edge of the test wafer from the X, Y position and within the field of view 328 of the camera 304 when the target locator box 344 is positioned accordingly. For example, for a test wafer, X3, Y3 may correspond to (X-A), (Y + B), and X4, Y4 may correspond to (X + C), (Y-D).

With the target locator box 344 applied to the notch 336 of the wafer 308, the camera 304 positions the

edge locator boxes

348 and 352 at the same distance from the target locator box 344 as the positions (X-A), (Y + B), and (X + C), (Y-D) are from the target locator box 344 for the test wafer. However, the position of the edge locator frames 348 and 352 can be adjusted to be located along the edge 314 of the wafer 308. In other words, misalignment (e.g., lateral offset and/or angular offset) of the wafer 308 may cause the edge 314 of the wafer 308 to follow a different path than the edge of the test wafer. Thus, when the edge locator frames 348 and 352 are positioned at the same distance from the target locator frame 344, the actual corresponding X1, Y1 and X2, Y2 positions of the wafer 308 may be offset relative to the X3, Y3 and X4, Y4 positions of the test wafer.

The X1, Y1, and X2, Y2 positions of the wafer 308 may be calculated based on the known distances from the X, Y position detected by the camera 304 and the edge 314 of the wafer 308. Camera 304 compares the X1, Y1 and X2, Y2 positions with the X3, Y3 and X4, Y4 positions, respectively, and thus calculates the lateral and angular offsets of wafer 308 compared to the test wafer. A correction value is calculated based on the lateral offset and the angular offset and used to adjust the position of the wafer 308 accordingly.

Referring now to fig. 4, an exemplary wafer alignment method 400 in accordance with the principles of the present invention begins at 404. The method 400 is implemented using the various components of fig. 1-3C as described below. At 408, the wafer is positioned on a load lock (e.g., load lock 300 of FIG. 3A). The wafer may be transferred to the load lock using a robot 224 under the control of the controller 160. For example, the wafer is positioned on a cooling susceptor in a raised (upward) position. At 412, the controller or control module (e.g., controller 160) provides instructions to a camera (e.g., camera 304 of fig. 3B) to make a measurement of the position of the wafer. For example, the controller 160 may implement system software or firmware that generates and sends messages to the camera 304. For example only, the message may correspond to an ethernet message.

At 416, the camera 304 captures an image of the wafer (e.g., an edge of the wafer including the notch) as described above in fig. 3C. At 420, the camera 304 processes and analyzes the image to detect and locate notches and the edge of the wafer, including implementing (annotating) the target locator box 344 and

edge locator boxes

348 and 352. At 424, the camera 304 calculates an angular offset and/or a lateral offset of the wafer (e.g., based on the positions of the target locator box 344 and the edge locator boxes 348 and 352). At 428, the camera 304 provides the calculated angular offset and/or lateral offset (e.g., via an ethernet message) to the controller 160.

Although described as being performed by camera 304, one or more of 420, 424, and 428 may be performed by controller 160 or other components. For example, the camera 304 may capture an image but then provide the image to the controller 160 to analyze and calculate the offset, or the camera may capture and analyze the image and provide the positions of the target locator box 344 and the

edge locator boxes

348 and 352 to the controller 160 to calculate the offset.

At 432, the plating robot (e.g., robot 236) retrieves the wafer from the load lock 300. For example, the cooling pedestal of the load lock 300 may be lowered before the robot 236 retrieves the wafer. At 436, the loading position of the processing unit (e.g., a plating unit of a destination chamber of the wafer) is adjusted based on the calculated angular offset and/or lateral offset. For example, the controller 160 controls (e.g., implements system software/firmware) the loading position of the processing unit to compensate for the expected angular offset calculated by the camera 304 or the controller 160. At 440, the robot 236 transfers the wafer to a processing unit. The method 400 ends at 444.

Referring now to fig. 5, a simplified exemplary wafer alignment system 500 is shown in accordance with the principles of the invention. The wafer alignment system includes a camera 504 and a controller 508 (corresponding to camera 304 and controller 160, for example only). The camera 504 includes an image capture module 512 and optionally includes an image analysis module 516 and an offset calculation module 520. The image capture module 512 controls the capture of images of the wafer (e.g., the edge and notch of the wafer) as described in fig. 1-4. For example, the image capture module 512 is responsive to commands from the controller 508 to initiate capture of an image of a wafer when the wafer is placed on the load lock.

The image capture module 512 provides the captured image to an image analysis module 516. As shown, the image analysis module 516 may be located in the camera 504, the controller 508, or another controller or module of the system 500. The image analysis module 516 analyzes the image to detect the edge and notch of the wafer and calculates the position of the target locator box 344 and the

edge locator boxes

348 and 352. The image analysis module 516 provides the calculated position to the offset calculation module 520, and the offset calculation module 520 calculates an angular offset (and/or a lateral offset) using the calculated position and the calculated reference position (i.e., calibration position). As shown, the offset calculation module 520 may be located within the camera 504, the controller 508, or another controller or module of the system 500.

The calculated offset (or offsets) is provided to a system control module 524 of the controller 508. Although shown as a single module, the system control module 524 may represent one or more modules associated with the control of a substrate processing system, such as the control of an electroplating robot, the control of a load position of a processing unit, and the like. For purposes of this embodiment, the system control module 524 controls the plating robot to retrieve the wafer from the load lock, adjusts the load position (i.e., the rotational direction) of the processing unit based on the calculated offset, and controls the robot to place the wafer on the processing unit. In an embodiment, additional aligners or other components (e.g., of the front end module) may be controlled to align the notches before the wafer is placed into the load lock.

Referring now to fig. 6A, 6B, and 6C, exemplary calibration images of a test wafer, exemplary images of a misaligned wafer, and exemplary comparisons of the calibration images and the images of the misaligned wafer are shown, respectively. Fig. 6A shows a test wafer 600 having a notch 604. Notch 604 is aligned with axis 608 (e.g., relative to a center point of test wafer 600, which may correspond to a center point 612 of the susceptor for a calibrated test wafer). The image includes calculated positions a and B (i.e., calibration positions) corresponding to, for example, X2, Y2 and X3, Y3, as described in the above embodiments.

In contrast, the image of wafer 620 as shown in fig. 6B has notch 624 aligned with axis 628 (e.g., relative to center point 632 of wafer 620). Wafer 620 is not properly aligned on the susceptor and, therefore, axis 628 rotates relative to axis 608 of test wafer 600. The image includes calculated positions C and D, which correspond to, for example, X1, Y1 and X2, Y2, as described above in the embodiments.

Fig. 6C shows an image of wafer 620 overlaid on an image of calibrated test wafer 600, showing the angular offset a3 between

axes

608 and 628. The system and method of the present invention, as described above in fig. 1-5, calculates the angular offset a3 based on a comparison between the calibrated positions a and B of the test wafer 600 and the calculated positions C and D of the wafer 620.

The foregoing description is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. The broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent upon a study of the drawings, the specification, and the following claims. As used herein, at least one of the phrases A, B and C should be construed to refer to logic (a OR B OR C) using a non-exclusive logic OR (OR), and should not be construed to refer to "at least one of a, at least one of B, and at least one of C". It should be understood that one or more steps of a method may be performed in a different order (or simultaneously) without altering the principles of the present invention.

In this application, including the definitions below, the term "controller" may be substituted for the term "circuit". The term "controller" may refer to, be part of, or include the following: an Application Specific Integrated Circuit (ASIC); digital, analog, or mixed analog/digital discrete circuits; digital, analog, or mixed analog/digital integrated circuits; a combinational logic circuit; a Field Programmable Gate Array (FPGA); processor circuitry (shared, dedicated, or combined) to execute code; memory circuitry (shared, dedicated, or combined) that stores code executed by the processor circuitry; other suitable hardware components that provide the described functionality; or a combination of some or all of the above, such as in a system on a chip.

The controller may include one or more interface circuits. In some examples, the interface circuit may include a wired or wireless interface to a Local Area Network (LAN), the internet, a Wide Area Network (WAN), or a combination thereof. The functionality of any given controller of the present invention may be distributed among multiple controllers connected via interface circuits. For example, multiple controllers may allow load balancing. In a further example, a server (also referred to as remote, or cloud) controller may perform certain functions on behalf of a client controller.

The term code, as used above, may include software, firmware, and/or microcode, and may refer to programs, routines, functions, classes, data structures, and/or objects. The term shared processor circuit includes a single processor circuit that executes some or all of the code from multiple controllers. The term combinational processor circuit includes a processor circuit that executes some or all code from one or more controllers in combination with additional processor circuits. References to multiple processor circuits include multiple processor circuits on a discrete die, multiple processor circuits on a single die, multiple cores of a single processor circuit, multiple threads of a single processor circuit, or a combination of the foregoing. The term shared memory circuit includes a single memory circuit that stores some or all of the code from multiple controllers. The term combinational memory circuit includes a memory circuit that stores some or all of the code from one or more controllers in combination with additional memory.

The term memory circuit is a subset of the term computer readable medium. The term computer-readable medium, as used herein, does not include transitory electrical or electromagnetic signals propagating through a medium (e.g., on a carrier wave); thus, the term computer-readable medium may be considered tangible and non-transitory. Non-limiting examples of non-transitory tangible computer-readable media are non-volatile memory circuits (e.g., flash memory circuits, erasable programmable read-only memory circuits, or masked read-only memory circuits), volatile memory circuits (e.g., static random access memory circuits or dynamic random access memory circuits), magnetic storage media (e.g., analog or digital tapes or hard drives), and optical storage media (e.g., CDs, DVDs, or blu-ray discs).

The apparatus and methods described in this application may be partially or completely implemented by a special purpose computer, which is created by configuring a general purpose computer to perform one or more specific functions embodied in a computer program. The functional blocks and flow diagram elements described above serve as software specifications that can be translated into a computer program by the routine work of a skilled technician or programmer.

The computer program includes processor-executable instructions stored on at least one non-transitory, tangible computer-readable medium. The computer program may also comprise or rely on stored data. The computer programs may include a basic input/output system (BIOS) that interacts with the hardware of the special purpose computer, a device driver that interacts with specific apparatus of the special purpose computer, one or more operating systems, user applications, background services, background applications, and the like.

The computer program may include: (i) description text to be parsed, such as HTML (hypertext markup language) or XML (extensible markup language), (ii) assembly code, (iii) object code generated from source code by a compiler, (iv) source code for execution by an interpreter, (v) source code for editing and execution by a just-in-time compiler, and so on. By way of example only, source code may be written using syntax from a language including: C. c + +, C #, Objective-C, Haskell, Go, SQL, R, Lisp,

Fortran、Perl、Pascal、Curl、OCaml、

HTML5, Ada, ASP (dynamic Server Web Page), PHP, Scala, Eiffel, Smalltalk, Erlang, Ruby, HawIth, and,

Visual

Lua, and

the elements recited in the claims are not intended to mean plus function elements in the meaning of 35u.s.c. § 112(f), unless the element is explicitly stated using the phrase "means for …", or in the case of the method claims, using the phrases "operation for …" or "step for …".

In some implementations, the controller is part of a system, which may be part of the above example. Such systems may include semiconductor processing equipment including one or more processing tools, one or more chambers, one or more platforms for processing, and/or specific processing components (wafer susceptors, gas flow systems, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of semiconductor wafers or substrates. The electronic device may be referred to as a "controller," which may control various elements or subcomponents of one or more systems. Depending on the process requirements and/or type of system, the controller can be programmed to control any of the processes disclosed herein, including controlling process gas delivery, temperature settings (e.g., heating and/or cooling), pressure settings, vacuum settings, power settings, Radio Frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer in and out of tools and other transfer tools, and/or load locks connected or interfaced with specific systems.

Broadly speaking, a controller may be defined as an electronic device having various integrated circuits, logic, memory, and/or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, and so forth. An integrated circuit may include a chip in firmware that stores program instructions, a Digital Signal Processor (DSP), a chip defined as an Application Specific Integrated Circuit (ASIC), and/or one or more microprocessors or microcontrollers executing program instructions (e.g., software). The program instructions may be in the form of various separate settings (or program files) that define the operating parameters for performing specific processes on or for a semiconductor wafer or system, which are transmitted to the controller. In some embodiments, the operating parameter may be part of a recipe defined by a process engineer for completing one or more processing steps during the preparation of one or more layer(s), material(s), metal(s), oxide(s), silicon dioxide, surface(s), circuitry and/or die(s) of a wafer.

In some implementations, the controller may be part of or coupled to a computer that is integrated with, coupled to, or otherwise connected to the system via a network, or a combination thereof. For example, the controller may be in the "cloud" or be all or part of a fab host system, which may allow remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of the manufacturing operation, check the history of past manufacturing operations, check trends or performance criteria for multiple manufacturing operations, change parameters of the current process, set processing steps to follow the current process or start a new process. In some examples, a remote computer (e.g., a server) may provide the process recipe to the system over a network, which may include a local network or the internet. The remote computer may include a user interface capable of inputting or programming parameters and/or settings that are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify parameters for each process step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus, as described above, a controller may be distributed, for example, by including one or more discrete controllers that are connected together by a network and work toward a common goal (e.g., the processes and controls described herein). An example of a distributed controller for these purposes may be one or more integrated circuits on a chamber that communicate with one or more remote integrated circuits (e.g., at the platform level or as part of a remote computer) that are incorporated to control a process on the chamber.

Exemplary systems may include, without limitation, a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a Physical Vapor Deposition (PVD) chamber or module, a Chemical Vapor Deposition (CVD) chamber or module, an Atomic Layer Deposition (ALD) chamber or module, an Atomic Layer Etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing system that may be associated with or used in the preparation and/or fabrication of semiconductor wafers.

As described above, depending on the process step or steps to be performed by the tool, the controller may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, tools located throughout the factory, a mainframe, another controller, or tools used in the handling of containers of wafers to and from tool locations and/or load ports in a semiconductor manufacturing facility.

Claims

1. A wafer alignment system, comprising:

an image capturing device that captures an image of a wafer positioned on the susceptor;

an image analysis module that analyzes the image to detect an edge of the wafer in the image and a notch formed at the edge of the wafer in the image, and calculates a first edge position and a second edge position corresponding to the edge of the wafer based on a position of the notch;

2. The wafer alignment system of claim 1, wherein the first and second edge positions are a predetermined distance from a location of the notch.

3. The wafer alignment system of claim 1, wherein to calculate the angular offset, the offset calculation module compares the first and second edge positions to third and fourth edge positions.

4. The wafer alignment system of claim 3, wherein the angular offset corresponds to a difference between the first edge position and the third edge position and a difference between the second edge position and the fourth edge position.

5. The wafer alignment system of claim 3, wherein the third edge location and the fourth edge location correspond to an edge of a test wafer.

6. The wafer alignment system of claim 5, wherein the image analysis module calculates the third edge position and the fourth edge position using images taken while the test wafer is disposed at a reference position on the susceptor.

7. The wafer alignment system of claim 5, wherein the first edge location, the second edge location, the third edge location, and the fourth edge location each correspond to coordinates within a field of view of the image capture device.

8. The wafer alignment system of claim 5, further comprising a light source disposed on a side of the wafer opposite the image capture device, wherein the light source is disposed to project light through the wafer toward the image capture device.

9. The wafer alignment system of claim 8, wherein the light source is arranged to illuminate a field of view of the image capture device.

10. The wafer alignment system of claim 1, wherein the system control module adjusts a loading position of the processing unit based on the angular offset before the wafer is transferred to the processing unit.

11. A wafer alignment method, comprising:

capturing an image of a wafer positioned on a susceptor;

analyzing the image to detect an edge of the wafer in the image and a notch formed in the edge of the wafer in the image;

12. The wafer alignment method as claimed in claim 11, wherein the first edge position and the second edge position are a predetermined distance from a position of the notch.

13. The wafer alignment method of claim 11, wherein calculating the angular offset includes comparing the first and second edge positions to third and fourth edge positions.

14. The wafer alignment method of claim 13, wherein the angular offset corresponds to a difference between the first edge position and the third edge position and a difference between the second edge position and the fourth edge position.

15. The wafer alignment method as claimed in claim 13, wherein the third edge location and the fourth edge location correspond to an edge of a test wafer.

16. The wafer alignment method as claimed in claim 15, further comprising calculating the third edge position and the fourth edge position using an image taken while the test wafer is disposed at a reference position on the susceptor.

17. The wafer alignment method of claim 15, wherein the first edge location, the second edge location, the third edge location, and the fourth edge location each correspond to coordinates within a field of view of the image capture device.

18. The wafer alignment method as claimed in claim 15, further comprising projecting light through the wafer toward the image capture device using a light source disposed on a side of the wafer opposite the image capture device.

19. The wafer alignment method as claimed in claim 18, wherein the light source is arranged to illuminate a field of view of the image capture device.

20. The wafer alignment method of claim 11, further comprising adjusting a loading position of the processing unit based on the angular offset before the wafer is transferred to the processing unit.