CN106409211B - Grid drive circuit, array substrate and display device - Google Patents
Grid drive circuit, array substrate and display device Download PDFInfo
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- CN106409211B CN106409211B CN201611140481.1A CN201611140481A CN106409211B CN 106409211 B CN106409211 B CN 106409211B CN 201611140481 A CN201611140481 A CN 201611140481A CN 106409211 B CN106409211 B CN 106409211B
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- 239000003990 capacitor Substances 0.000 claims description 12
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- 239000010409 thin film Substances 0.000 abstract description 21
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The invention provides a gate drive circuit, an array substrate and a display device.A shift register transmits a clock signal of a first level input by a second clock signal end to an output end in a first time period and transmits a clock signal of a second level input by the second clock signal end to the output end in a second time period under the control of a signal input by an input end; the shift register transmits a pull-down signal of a second level to the output terminal for a second period and a third period under the control of a signal input from the first clock signal terminal; under the control of the signal input by the first reset terminal, the shift register stops transmitting the clock signal input by the second clock signal terminal to the output terminal in the third time interval, and based on the control, the potential of the gate line can be pulled down by the clock signal of the second level and the pull-down signal of the second level together in the second time interval, so that the rapid pull-down of the gate line can be ensured, and the turn-off capability of the thin film transistor of the pixel unit and the charging capability of the pixel unit can be improved.
Description
Technical field
The present invention relates to display equipment technical field, more specifically to a kind of gate driving circuit, array substrate and
Display device.
Background technique
A kind of existing display panel, including a plurality of grid line, multiple data lines, multiple pixel units, gate driving electricity
Road and data drive circuit.Wherein, gate driving circuit includes multiple shift registers, the output end of each shift register with
One grid line is connected, and data drive circuit is connected with multiple data lines.Gate driving circuit is used for a plurality of grid line successively
Scanning signal is exported, data drive circuit is used for data line output data driving signal, to drive pixel unit to carry out image
Display.
During progressively scanning pixel unit, the grid line that shift register is first connected to corresponding line pixel unit is defeated
Enter scanning signal, open the thin film transistor (TFT) of the row pixel unit, drives the row pixel unit to carry out the display of image, later
Close the thin film transistor (TFT) of the row pixel unit to grid line input pulldown signal to pull down the current potential of grid line.But
Be, existing shift register can not quick pull-down grid line current potential, so as to cause the pass of the thin film transistor (TFT) of pixel unit
Cutting capacity is poor, and then influences the charging ability and display effect of pixel unit.
Summary of the invention
In view of this, the present invention provides a kind of gate driving circuit, array substrate and display device, to solve existing skill
In art shift register can not quick pull-down grid line current potential, cause the turn-off capacity of pixel unit thin film transistor (TFT) poor
Problem.
To achieve the above object, the invention provides the following technical scheme:
A kind of gate driving circuit, including cascade 1st grade of shift register, to n-th grade of shift register, n is greater than 2
Integer；
Each shift register all includes input, output end, the first reset terminal, the first clock signal terminal and second
Clock signal terminal；
Under the control of the signal of input terminal input, the shift register is in the first period by the second clock
The clock signal transmission of first level of signal end input is to the output end, in the second period by the second clock signal end
The clock signal transmission of the second electrical level of input to the output end, first level is greater than the second electrical level；
Under the control of the signal of first clock signal terminal input, the shift register in second period and
The pulldown signal of second electrical level is transmitted to the output end by the third period；
Under the control of the signal of first reset terminal input, the shift register stops in the third period will
The clock signal transmission of second clock signal end input is to the output end.
A kind of array substrate, including a plurality of grid line and gate driving circuit；
The gate driving circuit is gate driving circuit as described above；
The 1st grade of shift register in the gate driving circuit to n-th grade of shift register output end respectively with institute
It states a plurality of grid line and corresponds and be connected.
A kind of display device, including array substrate as described above.
Compared with prior art, the technical scheme provided by the invention has the following advantages:
Gate driving circuit, array substrate and display device provided by the present invention, since shift register is at second
The clock signal transmission for the second electrical level that section inputs second clock signal end is to output end, when stopping second the third period
To output end, i.e., the first reset terminal of shift register receives resets the clock signal transmission of the second electrical level of clock signal end input
The clock signal transmission for the second electrical level that the time of signal and shift register input second clock signal end is to output end
There is time interval, therefore, shift register can pass through the clock signal of second electrical level and the in the second period between time
The current potential of the common pulldown gate line of the pulldown signal of two level, thereby may be ensured that the quick pull-down of grid line, and then can mention
The turn-off capacity of the thin film transistor (TFT) of high pixel unit and the charging ability of pixel unit.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of existing structural schematic diagram of gate driving circuit；
Fig. 2 is the signal timing diagram of shift register shown in FIG. 1；
Fig. 3 is a kind of structural schematic diagram of gate driving circuit provided in an embodiment of the present invention；
Fig. 4 is the signal timing diagram of shift register shown in Fig. 3；
Fig. 5 is the structural schematic diagram of another gate driving circuit provided in an embodiment of the present invention；
Fig. 6 is the structural schematic diagram of another gate driving circuit provided in an embodiment of the present invention；
Fig. 7 is the structural schematic diagram of another gate driving circuit provided in an embodiment of the present invention；
Fig. 8 is a kind of schematic diagram of internal structure of shift register in gate driving circuit provided in an embodiment of the present invention；
Fig. 9 is the signal timing diagram of shift register shown in Fig. 8；
Figure 10 is another internal structure signal of shift register in gate driving circuit provided in an embodiment of the present invention
Figure；
Figure 11 is a kind of planar structure schematic diagram of array substrate provided in an embodiment of the present invention.
Specific embodiment
As described in background, existing shift register can not quick pull-down grid line current potential, so as to cause picture
The turn-off capacity of the thin film transistor (TFT) of plain unit is poor, and then influences the charging ability and display effect of pixel unit.
With reference to Fig. 1, Fig. 1 is a kind of existing structural schematic diagram of gate driving circuit, which includes more
A cascade shift register.Wherein, in two adjacent shift registers, the first clock signal terminal of a shift register
CK is connected with the first clock cable CK1, second clock signal end CKB is connected with second clock signal wire CKB1, another shifting
First clock signal terminal CK of bit register is connected with third clock cable CK2, second clock signal end CKB and the 4th clock
Signal wire CKB2 is connected.
Also, the output end OUT of the 1st shift register M1 is connected with the input terminal SET of the 5th shift register M5,
The output end OUT of 5th shift register M5 is connected with the reset terminal RESET of the 1st shift register M1, and the 2nd displacement is posted
The output end OUT of storage M2 is connected with the input terminal SET of the 6th shift register M6, the output end of the 6th shift register M6
OUT is connected with the reset terminal RESET of the 2nd shift register M2, output end OUT and the 7th shifting of the 3rd shift register M3
The input terminal SET of bit register M7 is connected, and the output end OUT of the 7th shift register M7 and the 3rd shift register M3's answers
Position end RESET is connected, and so on.
With reference to Fig. 2, Fig. 2 is the signal timing diagram of shift register shown in FIG. 1, by taking the 1st shift register M1 as an example,
Under the control of the high level signal of input terminal SET input, the shift register is in the first period T1 by second clock signal end
Clock signal, that is, scanning signal of the high level of CKB input is transmitted to the grid line being connected with output end OUT, so that with the grid
The thin film transistor (TFT) of the connected pixel unit of line is opened, and the pixel unit is driven to carry out the display of image；It is defeated in reset terminal RESET
Under the control of the signal entered, shift register stops exporting low level to output end OUT in the second period T2 and third period T3
Clock signal；Under the control of the signal of the first clock signal terminal CK input, shift register is in the second period T2 and third
Low level pulldown signal is transmitted to output end OUT by period T3, and the current potential of the grid line is dragged down, and is made and the grid line phase
The thin film transistor (TFT) of pixel unit even is closed.
But due to shift register by low level clock signal transmission to output end OUT when, reset terminal RESET meeting
The reset signal for receiving the output end OUT output of the 5th shift register M5 simultaneously, controls the shift register and stops low electricity
Flat clock signal transmission is to output end OUT, i.e. the low level clock of reset signal and output that receives of shift register
Without time interval between signal, therefore, will lead to shift register can not quick pull-down grid line current potential, so as to cause pixel
The turn-off capacity of the thin film transistor (TFT) of unit is poor, and then influences the charging ability and display effect of pixel unit.
Based on this, the present invention provides a kind of gate driving circuits, to overcome the above problem of the existing technology, including
For cascade 1st grade of shift register to n-th grade of shift register, n is the integer greater than 2；
Shift register described in every level-one all includes input, output end, the first reset terminal, the first clock signal terminal and
Two clock signal terminals；
Under the control of the signal of input terminal input, the shift register is in the first period by the second clock
The clock signal transmission of first level of signal end input is to the output end, in the second period by the second clock signal end
The clock signal transmission of the second electrical level of input to the output end, first level is greater than the second electrical level；
Under the control of the signal of first clock signal terminal input, the shift register in second period and
The pulldown signal of second electrical level is transmitted to the output end by the third period；
Under the control of the signal of first reset terminal input, the shift register stops in the third period will
The clock signal transmission of second clock signal end input is to the output end.
In gate driving circuit provided by the invention, clock that shift register can pass through second electrical level in the second period
The current potential of the common pulldown gate line of the pulldown signal of signal and second electrical level, thereby may be ensured that the quick pull-down of grid line, into
And the turn-off capacity of the thin film transistor (TFT) of pixel unit and the charging ability of pixel unit can be improved.
It is core of the invention thought above, to keep the above objects, features and advantages of the present invention more obvious easily
Understand, specific embodiments of the present invention will be described in detail with reference to the accompanying drawing.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
Implemented using other than the one described here other way, those skilled in the art can be without prejudice to intension of the present invention
In the case of do similar popularization, therefore the present invention is not limited by the specific embodiments disclosed below.
Secondly, combination schematic diagram of the present invention is described in detail, when describing the embodiments of the present invention, for purposes of illustration only, table
Show that the sectional view of device architecture can disobey general proportion and make partial enlargement, and the schematic diagram is example, is not answered herein
Limit the scope of protection of the invention.In addition, the three-dimensional space of length, width and depth should be included in actual fabrication.
It is described in detail below by several embodiments.
The embodiment of the invention provides a kind of gate driving circuits, and with reference to Fig. 3, Fig. 3 is provided in an embodiment of the present invention one
The structural schematic diagram of kind gate driving circuit, the gate driving circuit include cascade 1st grade shift register M1 to n-th grades of shifting
Bit register Mn, the first clock cable CK1, second clock signal wire CKB1, third clock cable CK2 and the 4th clock letter
Number line CKB2, wherein n is the integer greater than 2.Also, every level-one shift register all include input terminal SET, output end OUT,
First reset terminal RESET, the first clock signal terminal CK and second clock signal end CKB.The output end of every level-one shift register
OUT is connected with a grid line.
With reference to Fig. 4, Fig. 4 is the signal timing diagram of shift register shown in Fig. 3, in the signal that input terminal SET is inputted
Under control, shift register sweeps the clock signal of second clock signal end CKB the first level inputted in the first period T1
It retouches signal and is transmitted to output end OUT and its connected grid line, opened with controlling the thin film transistor (TFT) being connected with the grid line, it should
After thin film transistor (TFT) is opened, the data line that is connected with the source electrode of the thin film transistor (TFT) by data signal transmission extremely with the film crystal
The connected pixel electrode of the drain electrode of pipe, to charge to the pixel electrode, the pixel unit where making the pixel electrode is carried out
The display of image.
Under the control of the signal of input terminal SET input, shift register is in the second period T2 by second clock signal end
For the clock signal transmission of the second electrical level of CKB input to output end OUT and its connected grid line, the first level is greater than the second electricity
Flat, optionally, the first level is high level, and second electrical level is low level.Also, in the signal of the first clock signal terminal CK input
Control under, the pulldown signal of second electrical level is transmitted to output end in the second period T2 and third period T3 by shift register
OUT and its connected grid line.The clock signal and second that second electrical level can be passed through in the second period due to shift register
Therefore the current potential of the common pulldown gate line of the pulldown signal of level can be made and the grid line with the current potential of quick pull-down grid line
Connected thin film transistor (TFT) is closed.After the thin film transistor (TFT) is closed, the data line being connected with the source electrode of the thin film transistor (TFT) stops
The pixel electrode charging being connected to the drain electrode with the thin film transistor (TFT).
Under the control of the signal of the first reset terminal RESET input, shift register stops in third period T3 by second
The clock signal transmission of clock signal terminal CKB input is to output end OUT and its connected grid line.Due to the first reset terminal
When RESET inputs reset signal, second clock signal end CKB is also in low potential, and therefore, output end OUT will not be exported accidentally
High level signal, that is, scanning signal thereby may be ensured that the progressive scan of each row pixel unit.
In the present embodiment, as shown in figure 3, the output end OUT and 2m+4 grades of shift registers of 2m grades of shift registers
Input terminal SET be connected, the output end of the first reset terminal RESET and 2m+5 grades of shift registers of 2m grades of shift registers
OUT is connected, and the output end OUT of 2m-1 grades of shift registers is connected with the input terminal SET of 2m+3 grades of shift registers, the
First reset terminal RESET of 2m-1 grades of shift registers is connected with the output end OUT of 2m+4 grades of shift registers, wherein 0 <
m≤(n-7)/2。
For example, the input terminal SET of output end OUT and the 5th grade of shift register M5 of m=1, the 1st grade of shift register M1
It is connected, the first reset terminal RESET of the 1st grade of shift register M1 is connected with the output end OUT of the 6th grade of shift register M6, and the 2nd
The output end OUT of grade shift register M2 is connected with the input terminal SET of the 6th grade of shift register M6, the 2nd grade of shift register M2
The first reset terminal RESET be connected with the output end OUT of the 7th grade of shift register M7；M=2,3rd level shift register M3's
Output end OUT is connected with the input terminal SET of the 7th grade of shift register M7, the first reset terminal of 3rd level shift register M3
RESET is connected with the output end OUT of the 8th grade of shift register M8, output end OUT and the 8th grade of shifting of the 4th grade of shift register M4
The input terminal SET of bit register M8 is connected, first reset terminal RESET and the 9th grade of shift register of the 4th grade of shift register M4
The output end OUT of M9 is connected, and so on.
Also, the input terminal of the output end OUT and the n-th -8 grades shift register Mn-8 of the n-th -4 grades shift register Mn-4
SET is connected, the output end OUT of first reset terminal RESET and the 1st grade of shift register M1 of the n-th -4 grades shift register Mn-4
It is connected, the output end OUT of the n-th -3 grades shift register Mn-3 is connected with the input terminal SET of the n-th -7 grades shift register Mn-7,
The first reset terminal RESET of the n-th -3 grades shift register Mn-3 is connected with the output end OUT of the 2nd grade of shift register M2, and n-th -
The output end OUT of 2 grades of shift register Mn-2 is connected with the input terminal SET of the n-th -6 grades shift register Mn-6, the n-th -2 grades shiftings
The first reset terminal RESET of bit register Mn-2 is connected with the output end OUT of 3rd level shift register M3, and (n-1)th grade of displacement is posted
The output end OUT of storage Mn-1 is connected with the input terminal SET of the n-th -5 grades shift register Mn-5, (n-1)th grade of shift register
The first reset terminal RESET of Mn-1 is connected with the output end OUT of the 4th grade of shift register M4, and n-th grade of shift register Mn's is defeated
Outlet OUT is connected with the input terminal SET of the n-th -4 grades shift register Mn-4, the first reset terminal of n-th grade of shift register Mn
RESET is connected with the output end OUT of the 5th grade of shift register M5.
In the present embodiment, by by the first reset terminal RESET and 2m+5 grades of shift LDs of 2m grades of shift registers
The output end OUT of device is connected, and the first reset terminal RESET of 2m-1 grades of shift registers is defeated with 2m+4 grades of shift registers
Outlet OUT is connected, and the first reset terminal RESET of Lai Shixian shift register receives the time of reset signal and shift register will
Second clock signal end CKB input second electrical level clock signal transmission between the time of output end OUT have the time between
Every allowing shift register total by the clock signal of second electrical level and the pulldown signal of second electrical level in the second period T2
With the current potential of pulldown gate line, with the current potential of rapidly pulldown gate line, certainly, the present invention is not limited to this.
It in another embodiment of the invention, is another gate driving provided in an embodiment of the present invention with reference to Fig. 5, Fig. 5
The structural schematic diagram of circuit, the input terminal SET phase of the output end OUT of 2m grades of shift registers and 2m+4 grades of shift registers
Even, the first reset terminal RESET of 2m grades of shift registers is connected with the output end OUT of 2m+6 grades of shift registers, 2m-
The output end OUT of 1 grade of shift register is connected with the input terminal SET of 2m+3 grades of shift registers, 2m-1 grades of shift LDs
First reset terminal RESET of device is connected with the output end OUT of 2m+5 grades of shift registers, wherein 0 < m≤(n-7)/2.
For example, the input terminal SET of output end OUT and the 5th grade of shift register M5 of m=1, the 1st grade of shift register M1
It is connected, the first reset terminal RESET of the 1st grade of shift register M1 is connected with the output end OUT of the 7th grade of shift register M7, and the 2nd
The output end OUT of grade shift register M2 is connected with the input terminal SET of the 6th grade of shift register M6, the 2nd grade of shift register M2
The first reset terminal RESET be connected with the output end OUT of the 8th grade of shift register M8；M=2,3rd level shift register M3's
Output end OUT is connected with the input terminal SET of the 7th grade of shift register M7, the first reset terminal of 3rd level shift register M3
RESET is connected output end OUT and the 8th grade of the 4th grade of shift register M4 shifting with the output end OUT of the 9th grade of shift register M9
The input terminal SET of bit register M8 is connected, first reset terminal RESET and the 10th grade of shift LD of the 4th grade of shift register M4
The output end OUT of device M10 is connected.
Also, the input terminal of the output end OUT and the n-th -9 grades shift register Mn-9 of the n-th -5 grades shift register Mn-5
SET is connected, the output end OUT of first reset terminal RESET and the 1st grade of shift register M1 of the n-th -5 grades shift register Mn-5
It is connected, the output end OUT of the n-th -4 grades shift register Mn-4 is connected with the input terminal SET of the n-th -8 grades shift register Mn-8,
The first reset terminal RESET of the n-th -4 grades shift register Mn-4 is connected with the output end OUT of the 2nd grade of shift register M2, and n-th -
The output end OUT of 3 grades of shift register Mn-3 is connected with the input terminal SET of the n-th -7 grades shift register Mn-7, the n-th -3 grades shiftings
The first reset terminal RESET of bit register Mn-3 is connected with the output end OUT of 3rd level shift register M3, and the n-th -2 grades displacements are posted
The output end OUT of storage Mn-2 is connected with the input terminal SET of the n-th -6 grades shift register Mn-6, the n-th -2 grades shift registers
The first reset terminal RESET of Mn-2 is connected with the output end OUT of the 4th grade of shift register M4, (n-1)th grade of shift register Mn-1
Output end OUT be connected with the input terminal SET of the n-th -5 grades shift register Mn-5, the first of (n-1)th grade of shift register Mn-1
Reset terminal RESET is connected with the output end OUT of the 5th grade of shift register M5, the output end OUT of n-th grade of shift register Mn with
The input terminal SET of the n-th -4 grades shift register Mn-4 is connected, the first reset terminal RESET and the 6th of n-th grade of shift register Mn
The output end OUT of grade shift register M6 is connected.
In the embodiment, by by the first reset terminal RESET and 2m+6 grades of shift LDs of 2m grades of shift registers
The output end OUT of device is connected, and the first reset terminal RESET of 2m-1 grades of shift registers is defeated with 2m+5 grades of shift registers
Outlet OUT is connected, and the first reset terminal RESET of Lai Shixian shift register receives the time of reset signal and shift register will
Second clock signal end CKB input second electrical level clock signal transmission between the time of output end OUT have the time between
Every allowing shift register total by the clock signal of second electrical level and the pulldown signal of second electrical level in the second period T2
With the current potential of pulldown gate line, with the current potential of rapidly pulldown gate line, certainly, the present invention is not limited to this.
It in another embodiment, is another gate driving circuit provided in an embodiment of the present invention with reference to Fig. 6, Fig. 6
The output end OUT of structural schematic diagram, 2m grades of shift registers is connected with the input terminal SET of 2m+4 grades of shift registers, the
First reset terminal RESET of 2m grades of shift registers is connected with the output end OUT of 2m+7 grades of shift registers, 2m-1 grades of shiftings
The output end OUT of bit register is connected with the input terminal SET of 2m+3 grades of shift registers, and the of 2m-1 grades of shift registers
One reset terminal RESET is connected with the output end OUT of 2m+6 grades of shift registers, wherein 0 < m≤(n-7)/2.
For example, the input terminal SET of output end OUT and the 5th grade of shift register M5 of m=1, the 1st grade of shift register M1
It is connected, the first reset terminal RESET of the 1st grade of shift register M1 is connected with the output end OUT of the 8th grade of shift register M8, and the 2nd
The output end OUT of grade shift register M2 is connected with the input terminal SET of the 6th grade of shift register M6, the 2nd grade of shift register M2
The first reset terminal RESET be connected with the output end OUT of the 9th grade of shift register M9；M=2,3rd level shift register M3's
Output end OUT is connected with the input terminal SET of the 7th grade of shift register M7, the first reset terminal of 3rd level shift register M3
RESET is connected with the output end OUT of the 10th grade of shift register M10, and output end OUT and the 8th grade of the 4th grade of shift register M4
The input terminal SET of shift register M8 is connected, and the first reset terminal RESET of the 4th grade of shift register M4 is posted with the 11st grade of displacement
The output end OUT of storage M11 is connected.
Also, the input of the output end OUT of the n-th -6 grades shift register Mn-6 and the (n-1)th 0 grades of shift register Mn-10
SET is held to be connected, the output end of first reset terminal RESET and the 1st grade of shift register M1 of the n-th -6 grades shift register Mn-6
OUT is connected, the input terminal SET phase of the output end OUT of the n-th -5 grades shift register Mn-5 and the n-th -9 grades shift register Mn-9
Even, the first reset terminal RESET of the n-th -5 grades shift register Mn-5 is connected with the output end OUT of the 2nd grade of shift register M2,
The output end OUT of the n-th -4 grades shift register Mn-4 is connected with the input terminal SET of the n-th -8 grades shift register Mn-8, and n-th -4
The first reset terminal RESET of grade shift register Mn-4 is connected with the output end OUT of 3rd level shift register M3, the n-th -3 grades shiftings
The output end OUT of bit register Mn-3 is connected with the input terminal SET of the n-th -7 grades shift register Mn-7, the n-th -3 grades shift LDs
The first reset terminal RESET of device Mn-3 is connected with the output end OUT of the 4th grade of shift register M4, the n-th -2 grades shift registers
The output end OUT of Mn-2 is connected with the input terminal SET of the n-th -6 grades shift register Mn-6, the n-th -2 grades shift register Mn-2's
First reset terminal RESET is connected with the output end OUT of the 5th grade of shift register M5, the output of (n-1)th grade of shift register Mn-1
End OUT is connected with the input terminal SET of the n-th -5 grades shift register Mn-5, the first reset terminal of (n-1)th grade of shift register Mn-1
RESET is connected with the output end OUT of the 6th grade of shift register M6, the output end OUT of n-th grade of shift register Mn and the n-th -4 grades
The input terminal SET of shift register Mn-4 is connected, and the first reset terminal RESET of n-th grade of shift register Mn is posted with the 7th grade of displacement
The output end OUT of storage M7 is connected.
In the embodiment, by by the first reset terminal RESET and 2m+7 grades of shift LDs of 2m grades of shift registers
The output end OUT of device is connected, and the first reset terminal RESET of 2m-1 grades of shift registers is defeated with 2m+6 grades of shift registers
Outlet OUT is connected, and the first reset terminal RESET of Lai Shixian shift register receives the time of reset signal and shift register will
Second clock signal end CKB input second electrical level clock signal transmission between the time of output end OUT have the time between
Every allowing shift register total by the clock signal of second electrical level and the pulldown signal of second electrical level in the second period T2
With the current potential of pulldown gate line, with the current potential of rapidly pulldown gate line, certainly, the present invention is not limited to this.
In addition, in Fig. 3, Fig. 5 and gate driving circuit shown in fig. 6, adjacent two in all odd level shift registers
Grade shift register the first clock signal terminal CK respectively with the first clock cable CK1 and second clock signal wire CKB1 phase
Even, in all odd level shift registers the second clock signal end CKB of adjacent two-stage shift register respectively with third clock
Signal wire CK2 and the 4th clock cable CKB2 is connected；Adjacent two-stage shift register in all even level shift registers
First clock signal terminal CK is connected with the first clock cable CK1 and second clock signal wire CKB1 respectively, and all even levels move
In bit register the second clock signal end CKB of adjacent two-stage shift register respectively with third clock cable CK2 and the 4th
Clock cable CKB2 is connected.
For example, adjacent two-stage shift register is the 1st grade of shift register M1 and the 3rd in all odd level shift registers
Grade shift register M3, the first clock signal terminal CK of the 1st grade of shift register M1 is connected with the first clock cable CK1, and the 3rd
The first clock signal terminal CK of grade shift register M3 is connected with second clock signal wire CKB1, the 1st grade of shift register M1's
Second clock signal end CKB is connected with third clock cable CK2, the second clock signal end CKB of 3rd level shift register M3
It is connected with the 4th clock cable CKB2.
Adjacent two-stage shift register is the 2nd grade of shift register M2 and the 4th grade of shifting in all even level shift registers
The first clock signal terminal CK of bit register M4, the 2nd grade of shift register M2 are connected with the first clock cable CK1, the 4th grade of shifting
The first clock signal terminal CK of bit register M4 is connected with second clock signal wire CKB1, and the second of the 2nd grade of shift register M2
Clock signal terminal CKB is connected with third clock cable CK2, the second clock signal end CKB and of the 4th grade of shift register M4
Four clock cable CKB2 are connected.
It in another embodiment, is another gate driving circuit provided in an embodiment of the present invention with reference to Fig. 7, Fig. 7
Structural schematic diagram, wherein the input terminal SET phase of the output end OUT of 2m grades of shift registers and 2m+2 grades of shift registers
Even, the first reset terminal RESET of 2m grades of shift registers is connected with the output end OUT of 2m+3 grades of shift registers, 2m-
The output end OUT of 1 grade of shift register is connected with the input terminal SET of 2m+1 grades of shift registers, 2m-1 grades of shift LDs
First reset terminal RESET of device is connected with the output end OUT of 2m+2 grades of shift registers, wherein 0 < m≤(n-3)/2.
For example, the input terminal SET of the output end OUT and 3rd level shift register M3 of m=1, the 1st grade of shift register M1
It is connected, the first reset terminal RESET of the 1st grade of shift register M1 is connected with the output end OUT of the 4th grade of shift register M4, and the 2nd
The output end OUT of grade shift register M2 is connected with the input terminal SET of the 4th grade of shift register M4, the 2nd grade of shift register M2
The first reset terminal RESET be connected with the output end OUT of the 5th grade of shift register M5.
Also, the output end OUT of the n-th -2 grades shift registers is connected with the input terminal SET of the n-th -4 grades shift registers,
First reset terminal RESET of the n-th -2 grades shift registers is connected with the output end OUT of the 1st grade of shift register, (n-1)th grade of shifting
The output end OUT of bit register is connected with the input terminal SET of the n-th -3 grades shift registers, and the first of (n-1)th grade of shift register
Reset terminal RESET is connected with the output end OUT of the 2nd grade of shift register, the output end OUT and n-th -2 of n-th grade of shift register
The input terminal SET of grade shift register is connected, the first reset terminal RESET and 3rd level shift register of n-th grade of shift register
Output end OUT be connected.
In addition, first clock signal terminal CK and first clock signal of the 1st grade of shift register to n-th grade of shift register
Line CK1 is connected, the second clock signal end CKB and second clock signal wire of the 1st grade of shift register to n-th grade of shift register
CKB1 is connected.
In gate driving circuit shown in Fig. 7, by by the first reset terminal RESET and of 2m grades of shift registers
The output end OUT of 2m+3 grades of shift registers is connected, the first reset terminal RESET of 2m-1 grades of shift registers and 2m+2 grades
The output end OUT of shift register is connected, and the first reset terminal RESET of Lai Shixian shift register receives the time of reset signal
With shift register by the time of the clock signal transmission of the second clock signal end CKB second electrical level inputted to output end OUT
Between there is time interval so that shift register passes through the clock signal of second electrical level and second electrical level in the second period T2
The current potential of the common pulldown gate line of pulldown signal, thereby may be ensured that the quick pull-down of grid line, and then pixel list can be improved
The turn-off capacity of the thin film transistor (TFT) of member and the charging ability of pixel unit.
Gate driving circuit shown in Fig. 7 and Fig. 3, Fig. 5 and gate driving circuit shown in fig. 6 the difference is that,
Gate driving circuit shown in Fig. 7 can only carry out positive along the direction of the 1st grade of shift register M1 to n-th grades of shift register Mn
Scanning, and Fig. 3, Fig. 5 and gate driving circuit shown in fig. 6 can not only be posted along the 1st grade of shift register M1 to n-th grades of displacement
The direction of storage Mn carries out forward scan, and can be along the direction of n-th grade of shift register Mn to the 1st grades of shift register M1
Carry out reverse scan.
Below with reference to shift register a kind of internal structure and signal timing diagram to the working principle of shift register into
Row explanation, with reference to Fig. 8 and Fig. 9, Fig. 8 is a kind of inside of shift register in gate driving circuit provided in an embodiment of the present invention
Structural schematic diagram, Fig. 9 is the signal timing diagram of shift register shown in Fig. 8, by taking the 1st grade of shift register M1 as an example, the shifting
Bit register includes first switch tube K1 to the 7th switching tube K7, first capacitor C1 and the second capacitor C2.
Wherein, the control terminal of first switch tube K1 is connected with the input terminal SET of shift register, and the of first switch tube K1
One end is connected with first voltage end VGH；
The control terminal of second switch K2 is connected with the first reset terminal RESET of shift register, second switch K2's
First end is connected with second voltage end VGL, and the second end of second switch K2 is connected with the second end of first switch tube K1；
The first end of third switching tube K3 is connected with second voltage end VGL, and the second end of third switching tube K3 is opened with second
The second end for closing pipe K2 is connected, and the control terminal of third switching tube K3 is connected with the second end of the 4th switching tube K4；
The control terminal of 4th switching tube K4 is connected with the second end of first switch tube K1, the first end of the 4th switching tube K4 with
Second voltage end VGL is connected, and the second end of the 4th switching tube K4 passes through the second clock of first capacitor C1 and shift register
Signal end CKB is connected；
The control terminal of 5th switching tube K5 is connected with the second end of first switch tube K1, the first end of the 5th switching tube K5 with
Second clock signal end CKB is connected, and the second end of the 5th switching tube K5 is connected with the output end OUT of shift register, and the 5th
The control terminal of switching tube K5 is connected by the second capacitor C2 with the second end of the 5th switching tube K5；
The control terminal of 6th switching tube K6 is connected with the second end of the 4th switching tube K4, the first end of the 6th switching tube K6 with
Second voltage end VGL is connected, and the second end of the 6th switching tube K6 is connected with output end OUT；
The control terminal of 7th switching tube K7 is connected with the first clock signal terminal CK of shift register, the 7th switching tube K7's
First end is connected with second voltage end VGL, and the second end of the 7th switching tube K7 is connected with output end OUT.
In the embodiment of the present invention, said so that first switch tube K1 to the 7th switching tube K7 is PMOS transistor as an example
Bright, still, the present invention is not limited to this.After the input terminal SET input high level signal of shift register, first switch tube K1
Conducting.
The VGH high level inputted in first voltage end is transmitted to node PU by the first period T1, first switch tube K1, and to
Two capacitor C2 charge, when the voltage of the second capacitor C2 reaches the cut-in voltage of the 5th switching tube K5, the 5th switching tube K5
It opens, by the clock signal transmission of the high level of second clock signal end CKB input to output end OUT, wherein in the second capacitor
In the charging process of C2, the bootstrap effect of the second capacitor C2 can make the current potential of node PU further be promoted.
Second period T2, the low level clock signal transmission that the 5th switching tube K5 inputs second clock signal end CKB
To output end OUT, meanwhile, the high level signal of the first clock signal terminal CK input controls the 7th transistor K7 and opens, by second
Low level signal, that is, pulldown signal of voltage end VGL output is transmitted to output end OUT, in low level clock signal and low level
Pulldown signal collective effect under, the current potential of grid line is by quick pull-down.
In third period T3, the first reset terminal RESET input high level signal of shift register, second switch K2 is led
It is logical, the low level of second voltage end VGL is transmitted to node PU, to pull down the grid potential of the 5th switching tube K5, so that the 5th
Switching tube K5 is closed.
When exporting low level clock signal to output end OUT due to the 5th switching tube K5, the first reset terminal RESET is also not
Reset signal is received, therefore, low level clock signal and pulldown signal can be exported to grid line by output end OUT, come
The current potential of quick pull-down grid line, and then the turn-off capacity of the thin film transistor (TFT) of pixel unit and filling for pixel unit can be improved
Electric energy power.Simultaneously as when the first reset terminal RESET inputs reset signal, second clock signal end CKB also in low potential,
Therefore, output end OUT will not accidentally export high level signal, that is, scanning signal, thereby may be ensured that each row pixel unit line by line
Scanning.
Certainly, the present invention is not limited to this, in other embodiments, mentions with reference to Figure 10, Figure 10 for the embodiment of the present invention
Another schematic diagram of internal structure of shift register in the gate driving circuit of confession, the shift register further include the second reset
Hold IN, the 8th switching tube K8 and the 9th switching tube K9；Wherein, the control terminal of the 8th switching tube K8 is connected with the second reset terminal IN,
The first end of 8th switching tube K8 is connected with second voltage end VGL, and the second end of the 8th switching tube K8 is with first switch tube K1's
Second end is connected；The control terminal of 9th switching tube K9 is connected with the second reset terminal IN, the first end and second of the 9th switching tube K9
Voltage end VGL is connected, and the second end of the 9th switching tube K9 is connected with output end OUT.
When the signal of the second reset terminal IN input is high level signal, the 8th switching tube K8 and the 9th switching tube K9 are led
It is logical, and the low level of second voltage end VGL is transmitted to node PU, to pull down the current potential of the 5th switching tube K5 grid, and will be low
Level is exported to the grid line being connected with output end OUT, is carried out with the current potential of grid and grid line to the 5th switching tube K5 clear
Zero.
In the present embodiment, by by the first reset terminal RESET and 2m+5 grades of shift LDs of 2m grades of shift registers
The output end OUT of device is connected, and the first reset terminal RESET of 2m-1 grades of shift registers is defeated with 2m+4 grades of shift registers
Outlet OUT is connected, the low level clock signal of Lai Shixian second clock signal end CKB output and the first reset terminal RESET input
Reset signal between time interval, certainly, the present invention is not limited to this.
The embodiment of the invention also provides a kind of array substrates, and with reference to Figure 11, Figure 11 is provided in an embodiment of the present invention one
The planar structure schematic diagram of kind of array substrate, the array substrate include the gate driving circuit that any of the above-described embodiment provides and more
1~Gn of gate lines G, wherein the 1st grade of shift register M1 to n-th grades of shift register Mn's in gate driving circuit is defeated
Outlet OUT is connected with a plurality of 1~Gn of gate lines G one-to-one correspondence respectively, to be scanned one by one to 1~Gn of gate lines G, so as to right
Pixel unit array is progressively scanned.Certainly, the array substrate in the present embodiment further includes multiple data lines, multiple pixel lists
The pixel unit array of member composition and driving chip etc., this will not be repeated here.
The embodiment of the invention also provides a kind of display device, which includes array base provided by the above embodiment
Plate.
Gate driving circuit, array substrate provided by the embodiment of the present invention and display device, since shift register exists
For the clock signal transmission for the second electrical level that second period inputted second clock signal end to output end, stopping in the third period will
The clock signal transmission of the second electrical level of second clock signal end input to output end, i.e. the first of shift register resets termination
The clock signal transmission of second electrical level that the time and shift register for receiving reset signal input second clock signal end is to defeated
There is time interval, therefore, shift register can be believed in the second period by the clock of second electrical level between the time of outlet
Number and second electrical level the common pulldown gate line of pulldown signal current potential, thereby may be ensured that the quick pull-down of grid line, in turn
The turn-off capacity of the thin film transistor (TFT) of pixel unit and the charging ability of pixel unit can be improved.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.To the upper of the disclosed embodiments
It states bright, enables those skilled in the art to implement or use the present invention.Various modifications to these embodiments are to ability
Will be apparent for the professional technician in domain, the general principles defined herein can not depart from it is of the invention
In the case where spirit or scope, realize in other embodiments.Therefore, the present invention be not intended to be limited to it is shown in this article these
Embodiment, and it is to fit to the widest scope consistent with the principles and novel features disclosed herein.
Claims (11)
1. a kind of gate driving circuit, which is characterized in that including cascade 1st grade of shift register to n-th grade of shift register,
N is the integer greater than 2；
Each shift register all includes input, output end, the first reset terminal, the first clock signal terminal and second clock
Signal end；
Under the control of the signal of input terminal input, the shift register is in the first period by the second clock signal
It holds the clock signal transmission of the first level of input to the output end, inputs the second clock signal end in the second period
Second electrical level clock signal transmission to the output end, first level is greater than the second electrical level；
Under the control of the signal of first clock signal terminal input, the shift register is in second period and third
The pulldown signal of second electrical level is transmitted to the output end by the period；
Under the control of the signal of first reset terminal input, the shift register stops in the third period will be described
The clock signal transmission of second clock signal end input is to the output end.
2. circuit according to claim 1, which is characterized in that the output end of 2m grades of shift registers and 2m+4 grades of shiftings
The input terminal of bit register is connected, the output end of the first reset terminal and 2m+5 grades of shift registers of 2m grades of shift registers
It is connected, the output end of 2m-1 grades of shift registers is connected with the input terminal of 2m+3 grades of shift registers, 2m-1 grades of displacements
First reset terminal of register is connected with the output end of 2m+4 grades of shift registers；
The output end of the n-th -4 grades shift registers is connected with the input terminal of the n-th -8 grades shift registers, the n-th -4 grades shift LDs
First reset terminal of device is connected with the output end of the 1st grade of shift register, the output end and n-th -7 of the n-th -3 grades shift registers
The input terminal of grade shift register is connected, the output of the first reset terminal and the 2nd grade of shift register of the n-th -3 grades shift registers
End is connected, and the output end of the n-th -2 grades shift registers is connected with the input terminal of the n-th -6 grades shift registers, and the n-th -2 grades displacements are posted
First reset terminal of storage is connected with the output end of 3rd level shift register, the output end and n-th-of (n-1)th grade of shift register
The input terminals of 5 grades of shift registers is connected, the first reset terminal of (n-1)th grade of shift register and the 4th grade of shift register M4's
Output end is connected, and the output end of n-th grade of shift register is connected with the input terminal of the n-th -4 grades shift registers, and n-th grade of displacement is posted
First reset terminal of storage is connected with the output end OUT of the 5th grade of shift register；
Wherein, 0 < m≤(n-7)/2.
3. circuit according to claim 1, which is characterized in that the output end of 2m grades of shift registers and 2m+4 grades of shiftings
The input terminal of bit register is connected, the output end of the first reset terminal and 2m+6 grades of shift registers of 2m grades of shift registers
It is connected, the output end of 2m-1 grades of shift registers is connected with the input terminal of 2m+3 grades of shift registers, 2m-1 grades of displacements
First reset terminal of register is connected with the output end of 2m+5 grades of shift registers；
The output end of the n-th -5 grades shift registers is connected with the input terminal of the n-th -9 grades shift registers, the n-th -5 grades shift LDs
First reset terminal of device is connected with the output end of the 1st grade of shift register, the output end and n-th -8 of the n-th -4 grades shift registers
The input terminal of grade shift register is connected, the output of the first reset terminal and the 2nd grade of shift register of the n-th -4 grades shift registers
End is connected, and the output end of the n-th -3 grades shift registers is connected with the input terminal of the n-th -7 grades shift registers, and the n-th -3 grades displacements are posted
First reset terminal of storage is connected with the output end of 3rd level shift register, the output end and n-th-of the n-th -2 grades shift registers
The input terminals of 6 grades of shift registers is connected, and the first reset terminal of the n-th -2 grades shift registers is defeated with the 4th grade of shift register
Outlet is connected, and the output end of (n-1)th grade of shift register is connected with the input terminal of the n-th -5 grades shift registers, (n-1)th grade of displacement
First reset terminal of register is connected with the output end of the 5th grade of shift register, the output end and n-th-of n-th grade of shift register
The input terminal of 4 grades of shift registers is connected, the output of the first reset terminal and the 6th grade of shift register of n-th grade of shift register
End is connected；
Wherein, 0 < m≤(n-7)/2.
4. circuit according to claim 1, which is characterized in that the output end of 2m grades of shift registers and 2m+4 grades of shiftings
The input terminal of bit register is connected, the output end of the first reset terminal and 2m+7 grades of shift registers of 2m grades of shift registers
It is connected, the output end of 2m-1 grades of shift registers is connected with the input terminal of 2m+3 grades of shift registers, 2m-1 grades of displacements
First reset terminal of register is connected with the output end of 2m+6 grades of shift registers；
The output end of the n-th -6 grades shift registers is connected with the input terminal of the (n-1)th 0 grades of shift registers, the n-th -6 grades shift LDs
First reset terminal of device is connected with the output end of the 1st grade of shift register, the output end and n-th -9 of the n-th -5 grades shift registers
The input terminal of grade shift register is connected, the output of the first reset terminal and the 2nd grade of shift register of the n-th -5 grades shift registers
End is connected, and the output end of the n-th -4 grades shift registers is connected with the input terminal of the n-th -8 grades shift registers, and the n-th -4 grades displacements are posted
First reset terminal of storage is connected with the output end of 3rd level shift register, the output end and n-th-of the n-th -3 grades shift registers
The input terminals of 7 grades of shift registers is connected, and the first reset terminal of the n-th -3 grades shift registers is defeated with the 4th grade of shift register
Outlet is connected, and the output end of the n-th -2 grades shift registers is connected with the input terminal of the n-th -6 grades shift registers, the n-th -2 grades displacements
First reset terminal of register is connected with the output end of the 5th grade of shift register, the output end and of (n-1)th grade of shift register
The input terminals of n-5 grades of shift registers is connected, the first reset terminal of (n-1)th grade of shift register and the 6th grade of shift register
Output end is connected, and the output end of n-th grade of shift register is connected with the input terminal of the n-th -4 grades shift registers, and n-th grade of displacement is posted
First reset terminal of storage is connected with the output end of the 7th grade of shift register；
Wherein, 0 < m≤(n-7)/2.
5. circuit according to any one of claims 1 to 4, which is characterized in that the gate driving circuit further includes first
Clock cable is to the 4th clock cable；
In all odd level shift registers the first clock signal terminal of adjacent two-stage shift register respectively with described first when
Clock signal wire is connected with second clock signal wire, in all odd level shift registers adjacent two-stage shift register second when
Clock signal end is connected with the third clock cable and the 4th clock cable respectively；
In all even level shift registers the first clock signal terminal of adjacent two-stage shift register respectively with described first when
Clock signal wire is connected with second clock signal wire, in all even level shift registers adjacent two-stage shift register second when
Clock signal end is connected with the third clock cable and the 4th clock cable respectively.
6. circuit according to claim 1, which is characterized in that the output end of 2m grades of shift registers and 2m+2 grades of shiftings
The input terminal of bit register is connected, the output end of the first reset terminal and 2m+3 grades of shift registers of 2m grades of shift registers
It is connected, the output end of 2m-1 grades of shift registers is connected with the input terminal of 2m+1 grades of shift registers, 2m-1 grades of displacements
First reset terminal of register is connected with the output end of 2m+2 grades of shift registers；
The output end of the n-th -2 grades shift registers is connected with the input terminal of the n-th -4 grades shift registers, the n-th -2 grades shift LDs
First reset terminal of device is connected with the output end of the 1st grade of shift register, the output end and n-th -3 of (n-1)th grade of shift register
The input terminal of grade shift register is connected, the output of the first reset terminal and the 2nd grade of shift register of (n-1)th grade of shift register
End is connected, and the output end of n-th grade of shift register is connected with the input terminal of the n-th -2 grades shift registers, n-th grade of shift register
The first reset terminal be connected with the output end of 3rd level shift register；
Wherein, 0 < m≤(n-3)/2.
7. circuit according to claim 6, which is characterized in that the gate driving circuit further includes the first clock cable
With second clock signal wire；
The 1st grade of shift register to n-th grade of shift register the first clock signal terminal and first clock cable
It is connected, the second clock signal end and the second clock signal wire of the 1st grade of shift register to n-th grade of shift register
It is connected.
8. circuit according to claim 1, which is characterized in that the 1st grade of shift register to n-th grade of shift register
In any one shift register all include first switch tube to the 7th switching tube, first capacitor and the second capacitor；
The control terminal of the first switch tube is connected with the input terminal of the shift register, the first end of the first switch tube
It is connected with first voltage end；
The control terminal of the second switch is connected with the first reset terminal of the shift register, and the of the second switch
One end is connected with second voltage end, and the second end of the second switch is connected with the second end of the first switch tube；
The first end of the third switching tube is connected with the second voltage end, the second end of the third switching tube and described the
The second end of two switching tubes is connected, and the control terminal of the third switching tube is connected with the second end of the 4th switching tube；
The control terminal of 4th switching tube is connected with the second end of the first switch tube, the first end of the 4th switching tube
It is connected with the second voltage end, and the second end of the 4th switching tube passes through the first capacitor and the shift register
Second clock signal end be connected；
The control terminal of 5th switching tube is connected with the second end of the first switch tube, the first end of the 5th switching tube
It is connected with the second clock signal end, the second end of the 5th switching tube is connected with the output end of the shift register,
And the control terminal of the 5th switching tube is connected by second capacitor with the second end of the 5th switching tube；
The control terminal of 6th switching tube is connected with the second end of the 4th switching tube, the first end of the 6th switching tube
It is connected with the second voltage end, the second end of the 6th switching tube is connected with the output end；
The control terminal of 7th switching tube is connected with the first clock signal terminal of the shift register, the 7th switching tube
First end be connected with the second voltage end, the second end of the 7th switching tube is connected with the output end.
9. circuit according to claim 8, which is characterized in that the shift register further includes the second reset terminal, the 8th
Switching tube and the 9th switching tube；
The control terminal of 8th switching tube is connected with second reset terminal, the first end of the 8th switching tube and described the
Two voltage ends are connected, and the second end of the 8th switching tube is connected with the output end；
The control terminal of 9th switching tube is connected with second reset terminal, the first end of the 9th switching tube and described the
Two voltage ends are connected, and the second end of the 9th switching tube is connected with the second end of the first switch tube.
10. a kind of array substrate, which is characterized in that including a plurality of grid line and gate driving circuit；
The gate driving circuit is the described in any item circuits of claim 1 to 9；
The 1st grade of shift register in the gate driving circuit to n-th grade of shift register output end respectively with it is described more
Grid line, which corresponds, to be connected.
11. a kind of display device, which is characterized in that including array substrate described in any one of claim 10.
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| CN109801577B (en) | 2017-11-16 | 2022-07-19 | 京东方科技集团股份有限公司 | Gate driving circuit, display device and driving method thereof |
| CN113257205B (en) * | 2021-05-18 | 2023-02-03 | 武汉华星光电技术有限公司 | Grid driving circuit and display panel |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102097132A (en) * | 2009-12-14 | 2011-06-15 | 群康科技(深圳)有限公司 | Shift register and liquid crystal panel driving circuit |
| CN103208263A (en) * | 2013-03-14 | 2013-07-17 | 京东方科技集团股份有限公司 | Shift register, display device, gate drive circuit and driving method |
| CN103400558A (en) * | 2013-07-31 | 2013-11-20 | 京东方科技集团股份有限公司 | Shift register unit and driving method, gate driving circuit as well as display device thereof |
| CN103474017A (en) * | 2013-09-12 | 2013-12-25 | 北京京东方光电科技有限公司 | Shift register unit, gate drive circuit and display device |
-
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102097132A (en) * | 2009-12-14 | 2011-06-15 | 群康科技(深圳)有限公司 | Shift register and liquid crystal panel driving circuit |
| CN103208263A (en) * | 2013-03-14 | 2013-07-17 | 京东方科技集团股份有限公司 | Shift register, display device, gate drive circuit and driving method |
| CN103400558A (en) * | 2013-07-31 | 2013-11-20 | 京东方科技集团股份有限公司 | Shift register unit and driving method, gate driving circuit as well as display device thereof |
| CN103474017A (en) * | 2013-09-12 | 2013-12-25 | 北京京东方光电科技有限公司 | Shift register unit, gate drive circuit and display device |
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