CN106385361A

CN106385361A - Circuit for realizing SATOP protocol

Info

Publication number: CN106385361A
Application number: CN201610808328.5A
Authority: CN
Inventors: 何传华; 蔡春潮; 周伟
Original assignee: Shen Ou Communication Equipment Co Ltd
Current assignee: Shen Ou Communication Equipment Co Ltd
Priority date: 2016-09-05
Filing date: 2016-09-05
Publication date: 2017-02-08

Abstract

The present invention relates to a circuit for realizing a SATOP protocol. The circuit employs direct current 5V and E1 input to realize the SATOP protocol output through fibers and the Ethernet. The circuit realizes the prefect fusion of the traditional E1 signals with the newest SATOP and data interaction free of obstacles. The circuit is compatible to the newest IP technology and can satisfy the IP multi-business development and future business development requirement. The circuit for realizing a SATOP protocol employs the industrial grade design to realize the circuit of the SATOP protocol, and the circuit is mature and stable in technology and low in cost, and can solve the difficulty that the E1 access signals are converted to SATOP signals transmission.

Description

A kind of circuit for realizing SATOP agreement

Technical field

The invention belongs to field of circuit technology is and in particular to a kind of circuit for realizing SATOP agreement.

Background technology

At present, the equipment using E1 technology is an indispensable important ring in composition communication chain, uses in the market The device category of E1 is various, and with scientific and technical development, China inevitably enters the process of digitized IPization, traditional E1 technology needs the scheme that must solve to access IP.Though solution is had on market, it is mostly with external special chip, or Realize too complicated, technology is abroad monopolized, and most client can not grasp autonomous core technology.

Content of the invention

In order to solve the above problems, the present invention is designed for realizing the circuit of SATOP agreement using technical grade, this circuit skill Art is mature and stable, low cost, data is regarded as the pure bit stream of given speed, and these bit streams are packaged into after packet in puppet Transmit on line.Solve the problems, such as user cost, and the difficult problem that core technology cannot be grasped using special chip.

The technical solution used in the present invention is：Using a kind of circuit hardware realizing SATOP agreement, based on E1 interface by IP Technological perfectionism combines, and this hardware circuit provides the input of E1 interface, using SATOP agreement incoming fiber optic or Ethernet, innovation hard Part circuit design and software design it is achieved that hardware circuit E1 signal to SATOP perfect transformation function.

The invention has the beneficial effects as follows：A kind of simple circuit is designed using technical grade and realizes SATOP, this circuit realiration tradition E1 signal being perfectly combined and clog-free data interaction to up-to-date SATOP.The compatible up-to-date IP technology of the design, Neng Gouman Sufficient IP multi-service development, meets the expansion of future traffic demand.The human oriented design of management service interface, by logining corresponding web page Line program upgrading can be entered and safeguard it is easy to operating and managing.

Brief description

Fig. 1 is the SATOP circuit operation principle schematic diagram of the present invention；

Fig. 2 is that the E1 of SATOP circuit accesses partial circuit schematic diagram ()；

Fig. 3 is that the E1 of SATOP circuit accesses partial circuit schematic diagram (two)；

Fig. 4 is Ethernet SATOP output par, c circuit theory diagrams ()；

Fig. 5 is Ethernet SATOP output par, c circuit theory diagrams (two)；

Fig. 6 is optical fiber SATOP output par, c circuit theory diagrams ()；

Fig. 7 is optical fiber SATOP) output par, c circuit theory diagrams (two).

Specific embodiment

With reference to the accompanying drawings and examples the present invention is described in detail.

As shown in figure 1, being SATOP circuit operation principle and method of work, the circuit for realizing SATOP agreement adopts SATOP agreement (RFC4553), which is indifferent to the concrete structure that TDM signal (E1 etc.) adopts, but data is regarded as given The pure bit stream of speed, these bit streams transmit after being packaged into packet in pseudo-wire.

When E1 terminal unit is connected this circuit, the TDM signal of E1 is gathered and according to SATOP protocol encapsulation through FPGA Become Ethernet SATOP frame, and via MII interface, E1 bit stream is packaged into by packet by optical fiber or Ethernet and upload in network Defeated.

SATOP circuit provides the copying for E1 etc. compared with the PDH circuit business of low rate, is used to solve non-structural Change, that is, the E1 business transmission of non-frame pattern.TDM business is all carried out after cutting and encapsulation by it as the data code flow of serial PW tunnel is transmitted.In the middle of each key element of previously described TDM artificial service, this agreement can provide TDM business saturating Pass the transmission with synchronous timing information, but due to TDM frame structure can not be identified, therefore in TDM frame structure and TDM frame The information such as signaling can not identify and process, and can only do simple transparent transmission.This agreement is solution PDH low speed in TDM circuit simulating scheme A kind of simplest mode of business transparent transmission, is issued as RFC official standard by IETF tissue earliest.

In this circuit arrangement, using MPLS pattern.MPLS pattern adopts MPLS label to encapsulate PWE3 message, is made using LSP Outer layer tunnel for PW.PW label is as the innermost layer label of MPLS label stack.MPLS label can have multilamellar, Ke Yishi simultaneously The nesting of existing PW outer layer tunnel, is easy to be applied in more massive network range.

Fig. 2,3 be SATOP circuit E1 access partial circuit schematic diagram.It is same that Fig. 3 amplifies access E1 by transformer isolation Transmission Bitstream signal TRING, TTIP of axis and reception Bitstream signal RRING, RTIP DS26LV32 through Fig. 2 74LVC240 isolation caching issues FPGA collection after amplifying, and FPGA collects the bitstream data in 32 time slots of E1, presses The standard agreement of SATOP carries out packing encapsulation, and bag is sent from light path MII or Ethernet MII.

Fig. 4,5 be Ethernet SATOP output par, c circuit theory diagrams.Fig. 4 Ethernet chip IP175 passes through TXD [3：0]、 TXCLK、RXD[3：0], the E1SATOP bag of the MII such as TXCLK interface FPGA, and bag is converted into serial differential signals.Fig. 5 Amplified by Ethernet transformer isolation, by E1 bit stream from Internet to physical layer conversion.Achieve E1 bit stream with SATOP Transmission on physical layer netting twine for the form.

Fig. 6,7 be optical fiber SATOP output par, c circuit theory diagrams.Fig. 6 fiber chip 88E3015 passes through TXD [3：0]、 TXCLK、RX[3：0], the E1SATOP bag of the MII such as TXCLK interface FPGA, and bag is converted into serial differential signals.Fig. 7 Differential signal is converted into by optical signal by optical-electric module, by E1 bit stream from Internet to physical layer conversion.Achieve E1 ratio The transmission in physical layer light path in the form of SATOP of special stream.

The circuit parameter being used for realizing SATOP agreement in the present invention is as shown in the table：

Obviously, those skilled in the art can carry out the various changes and modification essence without deviating from the present invention to the present invention God and scope.So, if these modifications to the present invention and modification belong to the model of the claims in the present invention and its equivalent technology Within enclosing, then the present invention is also intended to comprise these changes and modification.

Claims

1. a kind of circuit for realizing SATOP agreement it is characterised in that：

Described circuit passes through E1 interface and direct current 5V interface accesses, and the TDM signal of E1 is gathered and according to SATOP agreement through FPGA It is packaged into Ethernet SATOP frame, then via MII interface, E1 bit stream is packaged in network by packet by optical fiber or Ethernet Upper transmission.

2. the as claimed in claim 1 circuit being used for realizing SATOP agreement it is characterised in that：

Described encapsulation adopts MPLS pattern.

3. the as claimed in claim 2 circuit being used for realizing SATOP agreement it is characterised in that：

Described MPLS pattern adopts MPLS label package edge to pseudo wire emulation (PWE3) message at edge, using LSP as puppet The outer layer tunnel of line (PW).

4. the as claimed in claim 3 circuit being used for realizing SATOP agreement it is characterised in that：

The label of described pseudo-wire is as the innermost layer label of MPLS label stack.

5. the as claimed in claim 4 circuit being used for realizing SATOP agreement it is characterised in that：

Described MPLS label stack has multilamellar, to realize the nesting of PW outer layer tunnel.

6. the as claimed in claim 1 circuit being used for realizing SATOP agreement it is characterised in that：

In described circuit, amplify transmission Bitstream signal TRING, TTIP and the reception accessing E1 coaxial line by transformer isolation Bitstream signal RRING, RTIP, issue FPGA collection after amplifying through DS26LV32 and 74LVC240 isolation caching, FPGA gathers Bitstream data in 32 time slots of E1, carries out packing encapsulation by the standard agreement of SATOP, and bag from light path MII or Ethernet MII sends.

7. the as claimed in claim 6 circuit being used for realizing SATOP agreement it is characterised in that：

In the output par, c circuit of described Ethernet MII, Ethernet chip IP175 passes through the E1SATOP of MII interface FPGA Bag, and bag is converted into serial differential signals；Amplified by Ethernet transformer isolation, by E1 bit stream from Internet to physics Layer conversion is it is achieved that the transmission on physical layer netting twine in the form of SATOP of E1 bit stream.

8. the as claimed in claim 6 circuit being used for realizing SATOP agreement it is characterised in that：

In the output par, c circuit of described light path MII, fiber chip 88E3015 passes through the E1SATOP of MII interface FPGA Bag, and bag is converted into serial differential signals；Differential signal is converted into by optical signal by optical-electric module, by E1 bit stream from net Network layers are to physical layer conversion it is achieved that the transmission in physical layer light path in the form of SATOP of E1 bit stream.