CN106384604A - Electrically erasable programmable read-only memory - Google Patents
Electrically erasable programmable read-only memory Download PDFInfo
- Publication number
- CN106384604A CN106384604A CN201610885992.XA CN201610885992A CN106384604A CN 106384604 A CN106384604 A CN 106384604A CN 201610885992 A CN201610885992 A CN 201610885992A CN 106384604 A CN106384604 A CN 106384604A
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- CN
- China
- Prior art keywords
- wordline
- electrically erasable
- memory
- erasable read
- dummy cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
Abstract
The present invention provides an electrically erasable programmable read-only memory. The electrically erasable programmable read-only memory comprises: a valid memory cell and a dummy cell; and in the layout of the electrically erasable programmable read-only memory, the valid memory cell has a first word line, the dummy cell has a second word line, and the first word line and the second word line are isolated from each other without forming a connection. The technical advantages of the electrically erasable programmable read-only memory provided by the present invention are that the first word line of the valid memory cell and second word line of the dummy cell, are isolated from each other without forming the connection, so that the pull-down current will increase because the word line voltage can increase; the pull-down performance is not impaired during the cycle because the word line erase voltage cannot be increased to the word line of the dummy cell; and in addition, the source line voltage drop will become smaller because the pull-down current is larger.
Description
Technical field
The present invention relates to field of semiconductor manufacture and reservoir designs field, it is more particularly related to a kind of
Electrically Erasable Read Only Memory, i.e. EEPROM (Erasable programmable Read-Only Memory) storage
Device.
Background technology
Memorizer (Memory) is the memory device in computer system, for depositing program data.The master of memorizer
Want function to be storage program and various data, and can in computer running high speed, be automatically completed program or data
Access.
Wherein, EPROM EPROM (Erasable programmable Read-Only
Memory it is) that to remain to the computer memory chips of retention data after a kind of power-off be non-volatile (non-volatile) storage
Device.EPROM EPROM is typically made up of one group of floating transistor, is more often provided than in electronic circuit by one
Programmed respectively with the electronic device of voltage higher voltage.Once after the completion of programming, EPROM EPROM can only
Wiped with strong ultraviolet radiation.
Electrically Erasable Read Only Memory (Electrically-Erasable Programmable Read-Only
Memory, abbreviation EEPROM or E2PROM) it is a kind of semiconductor memory apparatus that can pass through electronically repeatedly manifolding, permissible
Wipe existing information, reprogramming on computers or on special equipment.Compared to EPROM EPROM, electricity
Erasable Programmable Read Only Memory EPROM EEPROM does not need to be irradiated with ultraviolet, is not required to take off it is possible to use specific voltage yet,
Come the information on chip of erasing, to write new data.
Fig. 1 schematically shows the laying out pattern of the Electrically Erasable Read Only Memory according to prior art.Tool
Body ground, as shown in figure 1, in the Electrically Erasable Read Only Memory according to prior art, efficient memory unit 11
The wordline of wordline and dummy cell 12 is joined together to form the annular wordline 13 for example shown in Fig. 1, and described effective storage
Device unit 11 and described dummy cell 12 share source electrode line 14.
And, Fig. 2 schematically shows the wordline layout version of the Electrically Erasable Read Only Memory of prior art
The details of one example of figure layout.
Wherein, in FIG, described efficient memory unit 11 is used for data storage, and under described dummy cell 12 is used as
Pull transistor.
The shortcoming of the laying out pattern of the Electrically Erasable Read Only Memory according to prior art shown in Fig. 1 is：
First, when reading data, larger due to reading electric current, the voltage drop on higher source electrode line can be produced, so that reading electricity
Stream reduces.Secondly, the pull-down current of described dummy cell 12 is limited, this is because the read voltage of wordline is effectively deposited by described
The wordline of storage unit 11 links together, thus being limited by read voltage, and the word of described efficient memory unit 11
Line read voltage limits only about 3V.And, in erasing, word line voltage is 12V, under the continuous effect of this high pressure
Belonging to lower, the wordline grid oxygen of dummy cell 12 is degenerated, and leads to threshold voltage to raise, pull-down current reduces, and drop-down performance can be impaired.
Accordingly, it is desirable to provide a kind of Electrically Erasable Read Only Memory laying out pattern, enabling increase drop-down electricity
Stream, reduces the voltage drop of source electrode line, and avoids the pull-down current leading to during high pressure erasing to degenerate.
Content of the invention
The technical problem to be solved is that there is drawbacks described above in prior art, provides one kind can increase
Pull-down current, reduce the voltage drop of source electrode line, and avoid the electric erasable that during high pressure erasing, the pull-down current that leads to is degenerated can
Program read-only memory laying out pattern.
In order to realize above-mentioned technical purpose, according to the present invention, there is provided a kind of Electrically Erasable Read Only Memory, bag
Include：Efficient memory unit and dummy cell；And, in the laying out pattern of described Electrically Erasable Read Only Memory,
Described efficient memory unit has the first wordline, and described dummy cell has the second wordline, and described first wordline and institute
State the second wordline mutually isolated and do not form connection.
Preferably, in described Electrically Erasable Read Only Memory, change to realize described first by domain
Wordline and described second wordline mutually isolated.
Preferably, in described Electrically Erasable Read Only Memory, described first wordline and described second wordline
Mutually isolated and do not form connection by isolated part.
Preferably, in described Electrically Erasable Read Only Memory, described isolated part is in described first word
In the middle of line and described second wordline.
Preferably, in described Electrically Erasable Read Only Memory, described first wordline and described second wordline
The region being respectively provided with embedded described isolated part is connected with other layers with being formed respectively.
Preferably, in described Electrically Erasable Read Only Memory, described first wordline and described second wordline
It is arranged symmetrically with respect to described isolated part.
Preferably, in described Electrically Erasable Read Only Memory, in read operation, described efficient memory
Unit and described dummy cell jointly constitute a point of gate transistor device.
Preferably, in described Electrically Erasable Read Only Memory, in read operation, for the word selecting
Line, the word line voltage of described dummy cell is 5V.
Preferably, in described Electrically Erasable Read Only Memory, for same a line, unselected wordline, described
The word line voltage of dummy cell is also 5V.
Preferably, in described Electrically Erasable Read Only Memory, described efficient memory unit and described void
If unit shares source electrode line.
According to the Electrically Erasable Read Only Memory of the present invention it is a technical advantage that, by making efficient memory
The wordline of the wordline of unit and described dummy cell is mutually isolated and does not form connection, and pull-down current will become greatly, this is because word
Line voltage can increase, and typically increases to 5V from 3V；And, during circulating, drop-down performance is not damaged, this is because wordline is wiped
Except voltage will not be increased to the wordline of described dummy cell；Additionally, the voltage drop of source electrode line will diminish, this is because illusory list
The pull-down current of unit becomes big.
Brief description
In conjunction with accompanying drawing, and by reference to detailed description below, it will more easily have more complete understanding to the present invention
And its adjoint advantages and features are more easily understood, wherein：
Fig. 1 schematically shows the laying out pattern of the Electrically Erasable Read Only Memory according to prior art.
Fig. 2 schematically shows the wordline layout laying out pattern of the Electrically Erasable Read Only Memory of prior art
Details.
Fig. 3 schematically shows the domain of Electrically Erasable Read Only Memory according to the preferred embodiment of the invention
Layout.
Fig. 4 schematically shows the wordline of Electrically Erasable Read Only Memory according to the preferred embodiment of the invention
Layout laying out pattern details.
It should be noted that accompanying drawing is used for the present invention is described, and the unrestricted present invention.Note, represent that the accompanying drawing of structure can
Can be not necessarily drawn to scale.And, in accompanying drawing, same or like element indicates same or like label.
Specific embodiment
In order that present disclosure is more clear and understandable, with reference to specific embodiments and the drawings in the present invention
Appearance is described in detail.
The invention provides a kind of new EPROM EPROM framework, wherein so that effective store
The wordline of the wordline of device unit and described dummy cell is mutually isolated and does not form connection, so that pull-down current will become greatly,
And drop-down performance during circulating is not damaged, the voltage drop additionally realizing source electrode line diminishes.
The specific embodiment of the present invention to be described below in conjunction with accompanying drawing.
Fig. 3 schematically shows the domain of Electrically Erasable Read Only Memory according to the preferred embodiment of the invention
Layout.
Specifically, as shown in figure 3, Electrically Erasable Read Only Memory according to the preferred embodiment of the invention includes
Effect memory cell 21 and dummy cell 22；And, deposit electrically erasable according to the preferred embodiment of the invention is read-only
In the laying out pattern of reservoir, described efficient memory unit 21 has the first wordline 23, and described dummy cell 22 has the second word
Line 24, and described first wordline 23 and described second wordline 24 are mutually isolated and do not form connection.
Additionally, described efficient memory unit 21 and described dummy cell 22 share source electrode line 25.
It is further preferred that changed by domain to realize described first wordline 23 and described second wordline 24 mutual every
From.
For example, Fig. 4 schematically shows Electrically Erasable Read Only Memory according to the preferred embodiment of the invention
Wordline layout laying out pattern details.
Specifically, as shown in figure 4, described first wordline 23 and described second wordline 24 are mutually isolated by isolated part 25
And do not form connection；And, wherein said isolated part 25 is in the middle of described first wordline 23 and described second wordline 24.Excellent
Selection of land, described first wordline 23 and described second wordline 24 are arranged symmetrically with respect to described isolated part.It is further preferred that institute
State the first wordline 23 and described second wordline 24 is respectively provided with the region of embedded described isolated part 25 to be formed respectively and other
Layer connects.
In particular preferred embodiment, described efficient memory unit 21 and described dummy cell 22 jointly constitute one
Divide gate transistor device.
In Electrically Erasable Read Only Memory according to the preferred embodiment of the invention, change to realize by domain
Described first wordline 23 and described second wordline 24 mutually isolated, the wordline of described dummy cell 22 is in mutually in colleague, but
It is can to realize connecting by reducing the transistor of selection between different words.
Table below 1 shows the example of Electrically Erasable Read Only Memory according to the preferred embodiment of the invention
Programming operation, the running voltage under erasing operation and read operation, the unit of wherein data is volt.
Form 1
As shown in Table 1, in read operation, for the wordline selecting, the word line voltage of described dummy cell is 5V；And
And, in read operation, for unselected wordline, the word line voltage of described dummy cell is also 5V.
The technical advantage of Electrically Erasable Read Only Memory according to the preferred embodiment of the invention at least includes：
1. in Electrically Erasable Read Only Memory according to the preferred embodiment of the invention, described effective by making
First wordline 23 of memory cell 21 and described dummy cell 22 and described second wordline 24 are mutually isolated and do not form connection,
Pull-down current will become greatly, this is because word line voltage can increase (typically increasing to 5V from 3V).
2. and, in Electrically Erasable Read Only Memory according to the preferred embodiment of the invention, during circulating
Drop-down performance is not damaged, this is because wordline erasing voltage (generally 12V) will not be increased to the word of described dummy cell
Line.
3. additionally, in Electrically Erasable Read Only Memory according to the preferred embodiment of the invention, the electricity of source electrode line
Pressure drop will diminish, this is because pull-down current is larger.
Furthermore, it is necessary to explanation, unless stated otherwise or point out, otherwise the term in description " first ", " the
Two ", " 3rd " etc. describes each assembly being used only in differentiation description, element, step etc., rather than is used for representing each
Logical relation between assembly, element, step or ordering relation etc..
Although it is understood that the present invention is disclosed as above with preferred embodiment, but above-described embodiment being not used to
Limit the present invention.For any those of ordinary skill in the art, without departing under technical solution of the present invention ambit,
The technology contents that the disclosure above all can be utilized are made many possible variations and modification, or are revised as to technical solution of the present invention
Equivalent embodiments with change.Therefore, every content without departing from technical solution of the present invention, according to the technical spirit pair of the present invention
Any simple modification made for any of the above embodiments, equivalent variations and modification, all still fall within the scope of technical solution of the present invention protection
Interior.
And it should also be understood that the present invention is not limited to specific method described herein, compound, material, system
Make technology, usage and application, they can change.It should also be understood that term described herein be used merely to describe specific
Embodiment, rather than be used for limiting the scope of the present invention.Must be noted that herein and claims used in
Singulative " one ", " a kind of " and " being somebody's turn to do " include complex reference, unless context explicitly indicates that contrary.Therefore, example
As the citation of " element " meaned with the citation to one or more elements, and including known to those skilled in the art
Its equivalent.Similarly, as another example, the citation of " step " or " device " is meaned to one or
Multiple steps or the citation of device, and potentially include secondary step and second unit.Should be managed with broadest implication
All conjunctions that solution uses.Therefore, word "or" should be understood that the definition with logical "or", rather than logical exclusive-OR
Definition, unless context explicitly indicates that contrary.Structure described herein will be understood as also quoting from the function of this structure
Equivalent.Can be interpreted that approximate language should be understood like that, unless context explicitly indicates that contrary.
Claims (10)
1. a kind of Electrically Erasable Read Only Memory is it is characterised in that include：Efficient memory unit and dummy cell；And
And, in the laying out pattern of described Electrically Erasable Read Only Memory, described efficient memory unit has the first wordline,
Described dummy cell has the second wordline, and described first wordline and described second wordline are mutually isolated and do not form connection.
2. Electrically Erasable Read Only Memory according to claim 1 is it is characterised in that change to come in fact by domain
Existing described first wordline and described second wordline mutually isolated.
3. Electrically Erasable Read Only Memory according to claim 1 and 2 is it is characterised in that described first wordline
Mutually isolated and do not form connection by isolated part with described second wordline.
4. Electrically Erasable Read Only Memory according to claim 3 is it is characterised in that described isolated part is in
In the middle of described first wordline and described second wordline.
5. Electrically Erasable Read Only Memory according to claim 3 is it is characterised in that described first wordline and institute
State the second wordline and be respectively provided with the region of embedded described isolated part and be connected with other layers with being formed respectively.
6. Electrically Erasable Read Only Memory according to claim 1 and 2 is it is characterised in that described first wordline
It is arranged symmetrically with respect to described isolated part with described second wordline.
7. Electrically Erasable Read Only Memory according to claim 1 and 2 is it is characterised in that in read operation,
Described efficient memory unit and described dummy cell jointly constitute a point of gate transistor device.
8. Electrically Erasable Read Only Memory according to claim 1 and 2 is it is characterised in that in read operation,
For the wordline selecting, the word line voltage of described dummy cell is 5V.
9. Electrically Erasable Read Only Memory according to claim 1 and 2 is not it is characterised in that for same a line
The wordline selecting, the word line voltage of described dummy cell is also 5V.
10. Electrically Erasable Read Only Memory according to claim 1 and 2 is it is characterised in that described effective storage
Device unit and described dummy cell share source electrode line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610885992.XA CN106384604A (en) | 2016-10-10 | 2016-10-10 | Electrically erasable programmable read-only memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610885992.XA CN106384604A (en) | 2016-10-10 | 2016-10-10 | Electrically erasable programmable read-only memory |
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| Publication Number | Publication Date |
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| CN106384604A true CN106384604A (en) | 2017-02-08 |
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ID=57937237
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| Application Number | Title | Priority Date | Filing Date |
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| CN201610885992.XA Pending CN106384604A (en) | 2016-10-10 | 2016-10-10 | Electrically erasable programmable read-only memory |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109273036A (en) * | 2017-07-18 | 2019-01-25 | 意法半导体国际有限公司 | Nonvolatile memory with the dummy row for supporting storage operation |
| CN111627885A (en) * | 2019-02-28 | 2020-09-04 | 爱思开海力士有限公司 | Vertical memory device |
| CN111693839A (en) * | 2020-06-17 | 2020-09-22 | 西安交通大学 | Method for distinguishing degradation reason of SiC MOSFET under repeated surge current of body diode |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101026005A (en) * | 2006-02-16 | 2007-08-29 | 株式会社东芝 | Semiconductor memory device |
| CN101465353A (en) * | 2007-12-17 | 2009-06-24 | 三星电子株式会社 | Nonvolatile memory devices that utilize dummy memory cells to improve data reliability in charge trap memory arrays |
-
2016
- 2016-10-10 CN CN201610885992.XA patent/CN106384604A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101026005A (en) * | 2006-02-16 | 2007-08-29 | 株式会社东芝 | Semiconductor memory device |
| CN101465353A (en) * | 2007-12-17 | 2009-06-24 | 三星电子株式会社 | Nonvolatile memory devices that utilize dummy memory cells to improve data reliability in charge trap memory arrays |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109273036A (en) * | 2017-07-18 | 2019-01-25 | 意法半导体国际有限公司 | Nonvolatile memory with the dummy row for supporting storage operation |
| CN109273036B (en) * | 2017-07-18 | 2023-05-23 | 意法半导体国际有限公司 | Nonvolatile memory with virtual rows supporting memory operations |
| CN111627885A (en) * | 2019-02-28 | 2020-09-04 | 爱思开海力士有限公司 | Vertical memory device |
| CN111627885B (en) * | 2019-02-28 | 2023-05-26 | 爱思开海力士有限公司 | Vertical memory device |
| CN111693839A (en) * | 2020-06-17 | 2020-09-22 | 西安交通大学 | Method for distinguishing degradation reason of SiC MOSFET under repeated surge current of body diode |
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Application publication date: 20170208 |