CN106375153A - A Schedulability Analysis Method for Real-time Communication in Network-on-Chip - Google Patents

Abstract

The invention discloses a schedulability analysis method for real-time communication on a network-on-chip. The method comprises the following steps: taking a stream with the highest priority among streams that are not analyzed as a target stream; searching a direct interference stream, the direct interference stream having high priority and sharing link resources on a routing path of the target stream; searching an indirect interference stream and a downstream indirect interference stream of the indirect interference stream, wherein the indirect interference stream is the stream that has high priority, shares the link resources with the direct interference stream on a direct interference stream path of the target stream and does not share the link resources with the target stream, and the indirect interference stream is divided into an upstream indirect interference stream and the downstream indirect interference stream according to a relative position in which the indirect interference stream and the direct interference stream share the link resources; calculating the maximum indirect interference and the maximum downstream indirect interference; and calculating the maximum time delay of the target stream. The method makes a distinction between different effects of the upstream indirect interference stream and the downstream indirect interference stream upon the target stream when analyzing and calculating the maximum time delay of the target stream, thereby ensuring correctness of schedulability analysis for real-time communication on the network-on-chip.

Description

A Schedulability Analysis Method for Real-time Communication in Network-on-Chip

technical field

The invention belongs to the technical field of integrated circuit on-chip network communication, and more specifically relates to a schedulability analysis method for real-time communication in an on-chip network.

Background technique

Compared with non-real-time communication, real-time communication not only requires the logical correctness of the transmission result, but also requires the transmission delay to be less than or equal to a preset threshold to ensure the Quality of Service (QoS for short). For critical systems, if the real-time communication fails to meet the corresponding preset thresholds during operation, the result will be catastrophic. Therefore, in the design stage, it is particularly important to verify whether all real-time communication flows in the network on chip can meet the corresponding preset thresholds, that is, to analyze the schedulability.

In response to this problem, "Real-time communication analysis for on-chip networks with wormhole switching" published on pages 161-170 of the 10th IEEE/ACM International Symposium onNetworks-on-Chip International Conference in 2008 uses real-time scheduling analysis theory to establish A model (hereinafter referred to as the SB model) is proposed to analyze the maximum delay of each target flow. This model is easy to calculate, but it introduces too many interferences that do not exist, resulting in the calculated maximum delay being too large, and the schedulability too low. "SLA: A stage-level latency analysis for real-time communication in a pipelined resource model" published in "IEEE Transactions on Computers", Volume 64, Issue 4, 1177-1190, 2015, proposes a finer-grained model (following SLA model for short), can remove the non-existent interference introduced in the previous model to a certain extent, so that the calculated maximum delay and schedulability are closer to reality, but this model increases the complexity of calculation. At the same time, the maximum delay calculated by the above model may be smaller than the actual delay, and the originally unschedulable flow is considered as schedulable, causing catastrophic consequences in real-time systems.

Contents of the invention

In view of the above defects or improvement needs of the prior art, the present invention provides a method for analyzing the schedulability of real-time communication in a network on chip. Based on the theory of real-time scheduling analysis, the actual and correct schedulability results are obtained through analysis, thus solving the technical problem that may produce wrong analysis results in the existing models.

In order to achieve the above object, according to one aspect of the present invention, a method for analyzing the schedulability of real-time communication in a network on chip is provided, comprising the following steps:

Step a: determining the flow with the highest priority among the unanalyzed flows in the network-on-chip as the target flow;

Step b: Find a high-priority flow that shares link resources on the routing path of the target flow, and use it as a direct interference flow;

Step c: On the direct interference flow path of the target flow, determine the high-priority flow that shares link resources with the direct interference flow but does not share link resources with the target flow as the indirect interference flow, according to the indirect interference flow and the direct interference flow The relative position of flow sharing link resources divides the indirect interference flow into upstream indirect interference flow and downstream indirect interference flow;

Step d: Calculate the maximum indirect interference and the maximum downstream indirect interference according to the direct interference flow, the upstream indirect interference flow and the downstream indirect interference flow;

Step e: According to the maximum indirect interference I _ji and the maximum downstream indirect interference Calculate the maximum delay of the target flow;

Step f: Determine whether the maximum delay of the target flow is less than or equal to the preset threshold value. The value of the threshold value is determined according to the service level agreement. If so, repeat steps a to f until all the flows in the network on chip are processed Otherwise, it means that the real-time communication in the NoC cannot be scheduled, and the process ends.

Preferably, in step b, if there are one or more flows on the routing path of the target flow whose priority is higher than that of the target flow, then the flow is regarded as a high-priority flow.

Preferably, the interfering flow includes direct interfering flow and indirect interfering flow, and the direct interfering flow set Among them, i and j are numbers, λ _i and λ _j are target flow and direct interference flow respectively, and are the link resource sets on the routing path of λ _i and λ _j respectively, and P _i and P _j are the priorities of λ _i and λ _j respectively.

Preferably, the high-priority flow in step c means that if there are one or more flows on the routing path of the direct interference flow, the priority of which is higher than that of the direct interference flow, then the flow is regarded as a high-priority flow .

Preferably, in step c, the set of indirect interference flows Where k is the serial number, λ _k is the indirect interference flow, and the upstream indirect interference flow set downstream indirect interfering flow set Among them, f _ji and f _jk are respectively the numbers of the first link shared by λ _i and λ _k with λ _j on the routing path of λ _j .

Preferably, the maximum indirect interference I _ji and the maximum downstream indirect interference They are:

I _ji =R _j -C _j

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; j</span>}\mathrm{<span\; class="notranslate">\; i</span>}}^{\mathrm{<span\; class="notranslate">\; D.</span>}}<span\; class="notranslate">\; =</span>\underset{{\mathrm{<span\; class="notranslate">\; \&lambda;</span>}}_{\mathrm{<span\; class="notranslate">\; k</span>}}<span\; class="notranslate">\; \&Element;</span>{\mathrm{<span\; class="notranslate">\; S</span>}}_{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}}^{{\mathrm{<span\; class="notranslate">\; D.</span>}}_{\mathrm{<span\; class="notranslate">\; j</span>}}}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; k</span>}\mathrm{<span\; class="notranslate">\; j</span>}}$

Among them, C _j is the maximum delay of λ _j when it is not disturbed, I _kj is the interference generated by λ _k on λ _j , R _j is the maximum delay of λ _j , and its calculation formula is as follows:

Among them, T _k is the minimum packet sending interval in λ _k , C _k is the maximum delay when λ _k is not disturbed, and J _k is the time jitter of the packet sending interval of λ _k .

Preferably, the formula for calculating the maximum delay of the target flow in step e is:

Generally speaking, compared with the prior art, the above technical solutions conceived by the present invention can achieve the following beneficial effects:

(1) The present invention can solve the problem of catastrophic consequences in the system due to errors in the calculation of the maximum delay in the existing model: due to the adoption of steps c, d and e, the indirect interfering flow is further divided into upstream indirect Interference flow and downstream indirect interference flow, so as to calculate the maximum downstream indirect interference, and apply it to the calculation of the maximum delay, so the calculation errors in the existing model can be corrected, and the correct schedulability of real-time real-time communication in the network on chip can be obtained Analyze the results.

(2) The present invention can ensure the accuracy of distinguishing the upstream indirect interference flow and the downstream indirect interference flow: in step c, use the first link shared by the indirect interference flow and the direct interference flow and the first link shared by the direct interference flow and the target flow The relative position between the first links is used as a judgment condition, which can quickly and accurately distinguish the upstream indirect interference flow from the downstream indirect interference flow.

(3) The present invention can solve the correct maximum downstream indirect interference: in step d, by summing the interference produced by the downstream indirect interference flow on the direct interference flow, it is guaranteed that the obtained result is not less than the downstream indirect interference under any circumstances Interference, which is the maximum indirect interference.

(4) The calculation speed of the method of the present invention is fast and the efficiency is high.

Description of drawings

Fig. 1 is the flowchart of the schedulability analysis method of real-time communication in the network on chip of the present invention;

Figure 2 is an on-chip network containing 5 real-time communication streams.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not constitute a conflict with each other.

As shown in Figure 1, the schedulability analysis method of real-time communication in the network on chip of the present invention comprises the following steps:

Step a: determining the flow with the highest priority among the unanalyzed flows in the network-on-chip as the target flow;

Step b: Find high-priority flows that share link resources on the routing path of the target flow, and treat them as direct interference flows; specifically, if there are one or more flows on the routing path of the target flow, their priority If the priority of the target flow is higher than that of the target flow, then the flow is regarded as a high-priority flow;

Interference flow is divided into direct interference flow and indirect interference flow. direct interference flow collection Among them, i and j are numbers, λ _i and λ _j are target flow and direct interference flow respectively, and are the link resource sets on the routing path of λ _i and λ _j respectively, and P _i and P _j are the priorities of λ _i and λ _j respectively.

Step c: On the direct interference flow path of the target flow, determine the high-priority flow that shares link resources with the direct interference flow but does not share link resources with the target flow as the indirect interference flow, according to the indirect interference flow and the direct interference flow The relative position of flow sharing link resources divides the indirect interference flow into upstream indirect interference flow and downstream indirect interference flow; specifically, the high priority flow mentioned in this step refers to the routing path if the direct interference flow If there are one or more streams whose priority is higher than that of the directly interfering stream, then the stream is regarded as a high-priority stream;

indirect interfering flow collection Among them, k is the serial number, and λ _k is the indirect interference flow. The indirect interfering flow is divided into upstream and downstream indirect interfering flows according to the relative position of sharing link resources with the direct interfering flow. upstream indirect interfering flow set downstream indirect interfering flow set Among them, f _ji and f _jk are respectively the numbers of the first link shared by λ _i and λ _k with λ _j on the routing path of λ _j (the link numbers on the routing path of a flow are along the forward direction of the flow Incrementing sequentially from 1). Specifically, if the first link shared by the indirect interfering flow and the direct interfering flow is upstream of the first link shared by the direct interfering flow and the target flow, the indirect interfering flow is upstream indirect interfering flow; otherwise, it is Downstream indirect disturbance flow.

Step d: Calculate the maximum indirect interference and the maximum downstream indirect interference according to the direct interference flow, the upstream indirect interference flow and the downstream indirect interference flow;

Maximum indirect interference I _ji and maximum downstream indirect interference They are:

I _ji =R _j -C _j

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; j</span>}\mathrm{<span\; class="notranslate">\; i</span>}}^{\mathrm{<span\; class="notranslate">\; D.</span>}}<span\; class="notranslate">\; =</span>\underset{{\mathrm{<span\; class="notranslate">\; \&lambda;</span>}}_{\mathrm{<span\; class="notranslate">\; k</span>}}<span\; class="notranslate">\; \&Element;</span>{\mathrm{<span\; class="notranslate">\; S</span>}}_{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}}^{{\mathrm{<span\; class="notranslate">\; D.</span>}}_{\mathrm{<span\; class="notranslate">\; j</span>}}}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; k</span>}\mathrm{<span\; class="notranslate">\; j</span>}}$

Among them, C _j is the maximum delay of λ _j when it is not disturbed, I _kj is the interference generated by λ _k on λ _j , R _j is the maximum delay of λ _j , and its calculation formula is as follows:

Among them, T _k is the minimum packet sending interval in λ _k , C _k is the maximum delay when λ _k is not disturbed, and J _k is the time jitter of the packet sending interval of λ _k .

Step e: According to the maximum indirect interference I _ji and the maximum downstream indirect interference Calculate the maximum delay of the target flow;

The formula for calculating the maximum delay of the target stream is

Step f: Determine whether the maximum delay of the target flow is less than or equal to a preset threshold, the value of which is determined according to the Service Level Agreement (Service Level Agreement), if so, repeat steps a to f until all until all the streams are processed, otherwise it means that the real-time communication in the network-on-chip cannot be scheduled, and the process ends.

1. Embodiment:

Taking the five real-time communication flows in Figure 2 as examples, the schedulability calculation process is deduced and analyzed. Table 1 shows the parameters of 5 real-time streams, where C _i , T _i , P _i , D _i and J _i are respectively the maximum delay without interference, the minimum packet sending interval, the priority, the preset threshold and the packet sending corresponding to the stream. interval jitter.

Table 1

Because the quantity of real-time flow is 5 in the present embodiment, so the process of the present invention should include 5 cyclic processes, specifically as follows:

(1) The first cycle:

Step a: Determine the flow with the highest priority among the unanalyzed flows in the network on chip as the target flow.

The unanalyzed flows in the network on chip include λ ₁ , λ ₂ , λ ₃ , λ ₄ and λ ₅ , among which λ ₁ has the highest priority. Therefore, λ ₁ is the target flow.

Step b: Find a high-priority flow sharing link resources on the routing path of the target flow, and use it as a direct interference flow.

For λ ₁ , there is no direct interfering flow,

Step c: On the direct interference flow path of the target flow, determine the high-priority flow that shares link resources with the direct interference flow but does not share link resources with the target flow as the indirect interference flow, according to the indirect interference flow and the direct interference flow The relative positions of flow sharing link resources divide the indirect interference flow into upstream indirect interference flow and downstream indirect interference flow.

For λ ₁ , there is no indirect interference flow, and there is no downstream indirect interference flow,

Step d: Calculate the maximum indirect interference and the maximum downstream indirect interference according to the direct interference flow, the upstream indirect interference flow and the downstream indirect interference flow.

For λ ₁ , both the maximum indirect interference and the downstream indirect interference are zero.

Step e: According to the maximum indirect interference I _ji and the maximum downstream indirect interference Calculate the maximum latency of the target stream.

For λ ₁ , the maximum delay is R ₁ =C ₁ =30.

Step f: Determine whether the maximum delay of the target flow is less than or equal to the preset threshold, if so, repeat steps a to f until all the flows in the network on chip are processed, otherwise it means that the real-time communication in the network on chip cannot be scheduled , the process ends.

For λ ₁ , R ₁ =30<D ₁ =100, less than the preset threshold, and there is still unanalyzed flow, so steps a to f are repeated.

(2) The second cycle:

Step a: Determine the flow with the highest priority among the unanalyzed flows in the network on chip as the target flow.

The unanalyzed flows in the network on chip include λ ₂ , λ ₃ , λ ₄ and λ ₅ , among which λ ₂ has the highest priority. Therefore, λ ₂ is the target flow.

Step b: Find a high-priority flow sharing link resources on the routing path of the target flow, and use it as a direct interference flow.

For λ ₂ , there is no direct interfering flow,

Step c: On the direct interference flow path of the target flow, determine the high-priority flow that shares link resources with the direct interference flow but does not share link resources with the target flow as the indirect interference flow, according to the indirect interference flow and the direct interference flow The relative positions of flow sharing link resources divide the indirect interference flow into upstream indirect interference flow and downstream indirect interference flow.

For λ ₂ , there is no indirect interference flow, and there is no downstream indirect interference flow,

Step d: Calculate the maximum indirect interference and the maximum downstream indirect interference according to the direct interference flow, the upstream indirect interference flow and the downstream indirect interference flow.

For λ ₂ , both the maximum indirect interference and the downstream indirect interference are zero.

Step e: According to the maximum indirect interference I _ji and the maximum downstream indirect interference Calculate the maximum latency of the target stream.

For λ ₂ , the maximum delay is R ₂ =C ₂ =30.

Step f: Determine whether the maximum delay of the target flow is less than or equal to the preset threshold, if so, repeat steps a to f until all the flows in the network on chip are processed, otherwise it means that the real-time communication in the network on chip cannot be scheduled , the process ends.

For λ ₂ , R ₂ =30<D ₂ =100, less than the preset threshold, and there is still unanalyzed flow, so steps a to f are repeated.

(3) The third cycle:

Step a: Determine the flow with the highest priority among the unanalyzed flows in the network on chip as the target flow.

The unanalyzed flows in the network on chip include λ ₃ , λ ₄ and λ ₅ , among which λ ₃ has the highest priority. Therefore, λ ₃ is the target flow.

Step b: Find a high-priority flow sharing link resources on the routing path of the target flow, and use it as a direct interference flow.

For λ ₃ , the set of direct interference flows is

Step c: On the direct interference flow path of the target flow, determine the high-priority flow that shares link resources with the direct interference flow but does not share link resources with the target flow as the indirect interference flow, according to the indirect interference flow and the direct interference flow The relative positions of flow sharing link resources divide the indirect interference flow into upstream indirect interference flow and downstream indirect interference flow.

For λ ₃ , there is no indirect interference flow, and there is no downstream indirect interference flow,

Step d: Calculate the maximum indirect interference and the maximum downstream indirect interference according to the direct interference flow, the upstream indirect interference flow and the downstream indirect interference flow.

For λ ₃ , both the maximum indirect interference and the downstream indirect interference are 0,

Step e: According to the maximum indirect interference I _ji and the maximum downstream indirect interference Calculate the maximum latency of the target stream.

For λ ₃ , the maximum delay is Solving R ₃ =270.

Step f: Determine whether the maximum delay of the target flow is less than or equal to the preset threshold, if so, repeat steps a to f until all the flows in the network on chip are processed, otherwise it means that the real-time communication in the network on chip cannot be scheduled , the process ends.

For λ ₃ , R ₃ =270<D ₃ =300, which is less than the preset threshold, and there is still unanalyzed flow, so steps a to f are repeated.

(4) The fourth cycle:

Step a: Determine the flow with the highest priority among the unanalyzed flows in the network on chip as the target flow.

The unanalyzed flows in the network on chip include λ ₄ and λ ₅ , among which λ ₄ has the highest priority. Therefore, _λ4 is the target flow.

Step b: Find a high-priority flow sharing link resources on the routing path of the target flow, and use it as a direct interference flow.

For λ ₄ , the set of direct interference flows is

Step c: On the direct interference flow path of the target flow, determine the high-priority flow that shares link resources with the direct interference flow but does not share link resources with the target flow as the indirect interference flow, according to the indirect interference flow and the direct interference flow The relative positions of flow sharing link resources divide the indirect interference flow into upstream indirect interference flow and downstream indirect interference flow.

For λ ₄ , the set of indirect interference flows is The direct interference flow sharing the link with λ ₁ is λ ₃ , since f ₃₁ =1<f ₃₄ =5, λ ₁ is the upstream indirect interference flow, and there is no downstream indirect interference flow,

Step d: Calculate the maximum indirect interference and the maximum downstream indirect interference according to the direct interference flow, the upstream indirect interference flow and the downstream indirect interference flow.

For λ ₄ , the maximum indirect interference is I ₂₄ =0 and I ₃₄ =120, the maximum downstream indirect interference is 0,

Step e: According to the maximum indirect interference I _ji and the maximum downstream indirect interference Calculate the maximum latency of the target stream.

For λ ₄ , the maximum delay is Solving R ₄ =340.

Step f: Determine whether the maximum delay of the target flow is less than or equal to the preset threshold, if so, repeat steps a to f until all the flows in the network on chip are processed, otherwise it means that the real-time communication in the network on chip cannot be scheduled , the process ends.

For λ ₄ , R ₄ =340<D ₄ =550, which is less than the preset threshold, and there is still unanalyzed flow, so steps a to f are repeated.

(5) The fifth cycle:

Step a: Determine the flow with the highest priority among the unanalyzed flows in the network on chip as the target flow.

There are λ ₅ unanalyzed flows in the network on chip, and λ ₅ has the highest priority. Therefore, λ ₅ is the target flow.

Step b: Find a high-priority flow sharing link resources on the routing path of the target flow, and use it as a direct interference flow.

For λ ₅ , the set of direct interference flows is,

Step c: On the direct interference flow path of the target flow, determine the high-priority flow that shares link resources with the direct interference flow but does not share link resources with the target flow as the indirect interference flow, according to the indirect interference flow and the direct interference flow The relative positions of flow sharing link resources divide the indirect interference flow into upstream indirect interference flow and downstream indirect interference flow.

For λ ₅ , the set of indirect interference flows is The direct interference flow sharing the link with λ ₁ and λ ₂ is λ ₃ , since f ₃₁ =1<f ₃₅ =2<f ₃₂ =5, so λ ₁ is the upstream indirect interference flow, and λ ₂ is the downstream indirect interference flow , the set of downstream indirect interference flows is

Step d: Calculate the maximum indirect interference and the maximum downstream indirect interference according to the direct interference flow, the upstream indirect interference flow and the downstream indirect interference flow.

For λ ₅ , the maximum indirect interference is I ₃₅ =120, and the maximum downstream indirect interference is

Step e: According to the maximum indirect interference I _ji and the maximum downstream indirect interference Calculate the maximum latency of the target stream.

For λ ₅ , the maximum delay is Solving R ₅ =310.

Step f: Determine whether the maximum delay of the target flow is less than or equal to the preset threshold, if so, repeat steps a to f until all the flows in the network on chip are processed, otherwise it means that the real-time communication in the network on chip cannot be scheduled , the process ends.

For λ ₅ , R ₂ =310<D ₅ =260, greater than the preset threshold, the analysis ends, and under this set of conditions, the real-time communication in the network-on-chip cannot be scheduled.

2. Use the SB model and the SLA model to analyze the above examples respectively.

3. Analysis and comparison of results:

Table 2

Table 2 lists the analysis results of the SB model, the SLA model and the method of the present invention, as well as the experimental data obtained through simulation. The simulation results show that both the SB model and the SLA model have obtained wrong analysis results, but the method of the invention correctly analyzes the schedulability of the real-time communication in the on-chip network under the condition set.

It is easy for those skilled in the art to understand that the above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention, All should be included within the protection scope of the present invention.

Claims (7)

1. a schedulability analysis method of real-time communication in a network on chip, is characterized in that, comprises the following steps: Step a: determining the flow with the highest priority among the unanalyzed flows in the network-on-chip as the target flow; Step b: Find a high-priority flow that shares link resources on the routing path of the target flow, and use it as a direct interference flow; Step c: On the direct interference flow path of the target flow, determine the high-priority flow that shares link resources with the direct interference flow but does not share link resources with the target flow as the indirect interference flow, according to the indirect interference flow and the direct interference flow The relative position of flow sharing link resources divides the indirect interference flow into upstream indirect interference flow and downstream indirect interference flow; Step d: Calculate the maximum indirect interference and the maximum downstream indirect interference according to the direct interference flow, the upstream indirect interference flow and the downstream indirect interference flow; Step e: According to the maximum indirect interference I _ji and the maximum downstream indirect interference Calculate the maximum delay of the target flow; Step f: Determine whether the maximum delay of the target flow is less than or equal to the preset threshold value. The value of the threshold value is determined according to the service level agreement. If so, repeat steps a to f until all the flows in the network on chip are processed Otherwise, it means that the real-time communication in the NoC cannot be scheduled, and the process ends. 2. The schedulability analysis method according to claim 1, wherein in step b, if there are one or more flows on the routing path of the target flow, whose priority is higher than that of the target flow, then the stream is considered a high-priority stream. 3. The schedulability analysis method according to claim 1, wherein the interfering flows include direct interfering flows and indirect interfering flows, and the set of direct interfering flows Among them, i and j are numbers, λ _i and λ _j are target flow and direct interference flow respectively, and are the link resource sets on the routing path of λ _i and λ _j respectively, and P _i and P _j are the priorities of λ _i and λ _j respectively. 4. The schedulability analysis method according to claim 3, wherein in step c, the high-priority flow mentioned in this step means that if there are one or more flows on the routing path of the direct interference flow A flow whose priority is higher than that of the directly interfering flow is considered a high priority flow. 5. The schedulability analysis method according to claim 4, characterized in that, in step c, the set of indirect interference flows Where k is the serial number, λ _k is the indirect interference flow, and the upstream indirect interference flow set downstream indirect interfering flow set Among them, f _ji and f _jk are respectively the numbers of the first link shared by λ _i and λ _k with λ _j on the routing path of λ _j . 6. The schedulability analysis method according to claim 5, wherein the maximum indirect interference I _ji and the maximum downstream indirect interference They are: I _ji =R _j -C _j ${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; j</span>}\mathrm{<span\; class="notranslate">\; i</span>}}^{\mathrm{<span\; class="notranslate">\; D.</span>}}<span\; class="notranslate">\; =</span>\underset{{\mathrm{<span\; class="notranslate">\; \&lambda;</span>}}_{\mathrm{<span\; class="notranslate">\; k</span>}}<span\; class="notranslate">\; \&Element;</span>{\mathrm{<span\; class="notranslate">\; S</span>}}_{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}}^{{\mathrm{<span\; class="notranslate">\; D.</span>}}_{\mathrm{<span\; class="notranslate">\; j</span>}}}}{<span\; class="notranslate">\; \&Sigma;</span>}{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; k</span>}\mathrm{<span\; class="notranslate">\; j</span>}}$ Among them, C _j is the maximum delay of λ _j when it is not disturbed, I _kj is the interference generated by λ _k on λ _j , R _j is the maximum delay of λ _j , and its calculation formula is as follows: Among them, T _k is the minimum packet sending interval in λ _k , C _k is the maximum delay when λ _k is not disturbed, and J _k is the time jitter of the packet sending interval of λ _k . 7. The schedulability analysis method according to claim 6, wherein the formula for calculating the maximum delay of the target flow in step e is: