CN106339347A - Unified transformer substation secondary equipment synchronizing device time setting method - Google Patents
Unified transformer substation secondary equipment synchronizing device time setting method Download PDFInfo
- Publication number
- CN106339347A CN106339347A CN201610789208.5A CN201610789208A CN106339347A CN 106339347 A CN106339347 A CN 106339347A CN 201610789208 A CN201610789208 A CN 201610789208A CN 106339347 A CN106339347 A CN 106339347A
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- Prior art keywords
- pair
- time setting
- plug
- engagement positions
- substation secondary
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Small-Scale Networks (AREA)
Abstract
The invention discloses a unified transformer substation secondary equipment synchronizing device time setting method, which comprises the following steps that 1, external time setting signals are modulated into signals capable of being received by an FPGA (field programmable gate array), and the signals are sent into the FPGA to be processed; 2, the resolved timing mode is told to the FPGA in the initialization process by a time setting receiving plug-in; 3, the FPGA resolves the received time setting signals by the FPGA according to different time setting modes; after the resolving, the time setting information is transmitted onto a time setting bus of a synchronizing device; 4, all plug-ins of the synchronizing device take time setting information on the time setting bus to realize the time synchronism of all plug-ins of the synchronizing device; 5, when external time setting is interrupted, the time stored by a time setting chip can be sent to the time setting bus to realize the time synchronization of the synchronizing device. The unified processing of a source of the time setting of the synchronizing device can be realized; in addition, all of the plug-ins of the synchronizing device can synchronously obtain the time setting information; the excessive relying of non-receiving time setting plug-ins on the time setting receiving plug-pins is avoided; the universality is realized.
Description
Technical field
The invention belongs to Substation Automation System field, particularly to be that a kind of unified substation secondary device is whole
Device setting means.
Background technology
At present, in transformer station, pair when mode more, when common pair, mode has three kinds, irig-b, sntp and 1588 right
When, because the input source of mode when three kinds pairs is different, result in device pair when processing mode on difference.Signal source one
As be all in a certain block of plug-in unit being directly connected in device, during this plug-in unit pair after, and by this plug-in unit by temporal information pass through soft report
The mode of literary composition+pps pulse per second (PPS) is transferred in plug-in unit when non-reception pair, by plug-in unit when non-reception pair when carrying out processing acquisition
Between.Pair when receive plug-in unit in, current irig-b and 1588 pair when reception processing typically by device fpga module parse,
After parsing will pair when information notifying unit cpu, sntp typically directly receives by the cpu of device and processes.
This mode causes the disunity that engagement positions time source is processed, in the occasion having specific demand to the time, two
Individual module all can need to change, if test is insufficient also can there is hidden danger；And if reception plug-in unit is abnormal during this mode pair,
Or internal pps pulse per second (PPS) sends extremely, then can lead to the time irreversibility of engagement positions difference plug-in unit, thus information of record etc.
Will there is deviation, more can lead to secondary device operation irregularity in transformer station.
Content of the invention
For overcoming the shortcomings of in prior art, the present invention provides a kind of unified substation secondary device engagement positions pair when side
Method, it is possible to achieve source during engagement positions pair is uniformly processed, and information when all plug-in units of engagement positions can synchronously get pair,
Plug-in unit is received during plug-in unit transition dependence pair when avoiding non-reception pair.
For solving above technical problem, the present invention provides a kind of unified substation secondary device engagement positions setting means,
Including:
1) mode during substation secondary device engagement positions pair is carried out unified, pair when signal received by preposition fpga module
And parse；
2) fpga module will parse after pair when signal pass through substation secondary device engagement positions inside pair when bus pass to institute
Have a plug-in unit, all plug-in units are unified receive after parsing pair when signal, realize the time synchronized of all plug-in units of engagement positions；
3) if pair when interrupt when, by inside substation secondary device engagement positions, the temporal information of clock chip is sent to fpga
Module, and by fpga module transmit this temporal information to pair when bus on, for all plug-in units receive, all plug-in units of engagement positions then
Time synchronized.
Described step 1) in, pair when mode when unifying, when selecting irig-b pair, 1588 pairs when, sntp pair when in
Any one, with pair when source signal output match, rebooting device allows setting to come into force.
Described step 2), bus when having inside substation secondary device engagement positions pair, use time in need plug-in unit
Be all from pair when bus obtain the time.
In described step 3), substation secondary device is self-contained to be equipped with unified time source, and can transmit to pair when total
Line, obtains for all plug-in units.
The invention has the beneficial effects as follows:
1, the invention provides the unified source processing method of engagement positions time, contributes to lifting the time of all plug-in units of engagement positions
Uniformity.
2 the invention provides within engagement positions pair when bus, all plug-in units of engagement positions all from pair when bus obtain when
Between, no longer transition receives plug-in unit when relying on pair, is capable of the synchronicity that all plug-in unit times obtain, not need soft message+
The mode of pps pulse per second (PPS), can by pair when chip-stored time send to pair when bus realize the time synchronized of engagement positions.
The 3rd, pair when interrupting when, the present invention provide inside engagement positions by will pair when chip time send to pair when bus, reality
The time synchronized of the existing all plug-in units of engagement positions and unification, it is possible to achieve source during engagement positions pair is uniformly processed, and engagement positions
Information when all plug-in units can synchronously get pair, it is to avoid when non-reception pair, plug-in unit transition receives plug-in unit when relying on pair, has
Versatility.
Brief description
Schematic flow sheet when Fig. 1 is normal when outside pair；
Fig. 2 is schematic flow sheet when interrupting when outside pair.
Specific embodiment
Technological means, creation characteristic, reached purpose and effect for making the present invention realize are easy to understand, with reference to
Specific embodiment, is expanded on further the present invention, and following described examples are only a part of example of the present invention, rather than entirely
The example in portion.
The unified engagement positions setting means of the present invention, in turn include the following steps:
1st, signal modulation when outside pair is the receivable signal of fpga, and signal is sent into fpga process.
The 2nd, pair receive when plug-in unit in initialization procedure by parsed pair when mode inform fpga.
3rd, fpga according to pair when the different parsing of mode receive pair when signal, after parsing will pair when information transmission to engagement positions
Pair when bus on.
4th, all plug-in units of engagement positions all from pair when bus take pair when information, realize time of all plug-in units of engagement positions with
Step.
5th, outside pair when when interrupting, can by pair when chip-stored time send to pair when bus realize engagement positions when
Between synchronous.
For describing the present invention in detail, the unified substation secondary device engagement positions setting means of the present embodiment, concrete from
Include the following:
1st, device interface setting engagement positions pair when pattern, when irig-b pair, 1588 pairs when, sntp pair when in any one,
With pair when source signal output match, rebooting device allows setting to come into force.
2 as shown in figure 1, illustrate presence outside to constantly, a hardware block diagram of whole process, device passes through preposition
Signal when fpga module receives pair, and being parsed, bus when signal being gone to pair after parsing, set time for all plug-in units
With.
If 3 as shown in Fig. 2 when interrupting when illustrating outside pair, maintain engagement positions by the time of clock chip
Pair when unification, in bus when will be transformed into pair time of clock chip, set time for all plug-in units.
4th, no matter engagement positions whether there is outside pair, all plug-in units of engagement positions all from pair when bus take pair when letter
Breath, realizes the time synchronized of all plug-in units of engagement positions.
Based on above-mentioned, the present invention can by pair when chip-stored time send to pair when bus realize time of engagement positions
Synchronous.The source that the present invention can realize during engagement positions pair is uniformly processed, and all plug-in units of engagement positions can synchronously get
Pair when information, it is to avoid when non-reception pair, plug-in unit transition receives plug-in unit when relying on pair, has versatility.
Above-mentioned combination accompanying drawing is only a kind of of the specific embodiment of the invention preferably to be described, not in order to limit this
Bright.One of ordinary skill in the art should be understood that on the basis of technical scheme, and those skilled in the art do not need to pay
Various modifications that creative work can be made or deformation are still within protection scope of the present invention.
Claims (4)
1. a kind of unified substation secondary device engagement positions setting means are it is characterised in that include:
1) mode during substation secondary device engagement positions pair is carried out unified, pair when signal received by preposition fpga module
And parse；
2) fpga module will parse after pair when signal pass through substation secondary device engagement positions inside pair when bus pass to institute
Have a plug-in unit, all plug-in units are unified receive after parsing pair when signal, realize the time synchronized of all plug-in units of engagement positions；
3) if pair when interrupt when, by inside substation secondary device engagement positions, the temporal information of clock chip is sent to fpga
Module, and by fpga module transmit this temporal information to pair when bus on, for all plug-in units receive, substation secondary device then
The time synchronized of all plug-in units of engagement positions.
2. unified substation secondary device engagement positions setting means according to claim 1 are it is characterised in that described step
In rapid 1), pair when mode when unifying, when selecting irig-b pair, 1588 pairs when, sntp pair when in any one, with pair when
The signal output in source matches, and rebooting device allows setting to come into force.
3. unified substation secondary device engagement positions setting means according to claim 1 are it is characterised in that described step
Rapid 2), bus when having inside substation secondary device engagement positions pair, use time in need plug-in unit be all from pair when bus
The upper acquisition time.
4. according to the unified substation secondary device engagement positions setting means of claim 1 it is characterised in that interrupt when, described
In step 3), substation secondary device is self-contained to be equipped with unified time source, and can transmit to pair when bus, for all plug-in units
Obtain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610789208.5A CN106339347A (en) | 2016-08-30 | 2016-08-30 | Unified transformer substation secondary equipment synchronizing device time setting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610789208.5A CN106339347A (en) | 2016-08-30 | 2016-08-30 | Unified transformer substation secondary equipment synchronizing device time setting method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106339347A true CN106339347A (en) | 2017-01-18 |
Family
ID=57823576
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610789208.5A Pending CN106339347A (en) | 2016-08-30 | 2016-08-30 | Unified transformer substation secondary equipment synchronizing device time setting method |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201535806U (en) * | 2009-07-22 | 2010-07-28 | 南京南瑞继保电气有限公司 | Relay protection test device |
| WO2010122896A1 (en) * | 2009-04-21 | 2010-10-28 | 京セラ株式会社 | Data transmission system, data transmission method, and data transmission apparatus |
| CN201828585U (en) * | 2010-10-20 | 2011-05-11 | 国电南瑞科技股份有限公司 | Portable transformer substation synchronous time ticking and SOE signal generator |
| CN102130504A (en) * | 2011-03-08 | 2011-07-20 | 国电南瑞科技股份有限公司 | Interactive sampling value transmission system and sampling value transmission method thereof |
| EP2863278A1 (en) * | 2013-10-15 | 2015-04-22 | LSIS Co., Ltd. | Event input module for time synchronisation among PLCs |
| CN104579624A (en) * | 2014-12-29 | 2015-04-29 | 云南电网公司电力科学研究院 | Clock synchronization method of network sampling intelligent substation |
-
2016
- 2016-08-30 CN CN201610789208.5A patent/CN106339347A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010122896A1 (en) * | 2009-04-21 | 2010-10-28 | 京セラ株式会社 | Data transmission system, data transmission method, and data transmission apparatus |
| CN201535806U (en) * | 2009-07-22 | 2010-07-28 | 南京南瑞继保电气有限公司 | Relay protection test device |
| CN201828585U (en) * | 2010-10-20 | 2011-05-11 | 国电南瑞科技股份有限公司 | Portable transformer substation synchronous time ticking and SOE signal generator |
| CN102130504A (en) * | 2011-03-08 | 2011-07-20 | 国电南瑞科技股份有限公司 | Interactive sampling value transmission system and sampling value transmission method thereof |
| EP2863278A1 (en) * | 2013-10-15 | 2015-04-22 | LSIS Co., Ltd. | Event input module for time synchronisation among PLCs |
| CN104579624A (en) * | 2014-12-29 | 2015-04-29 | 云南电网公司电力科学研究院 | Clock synchronization method of network sampling intelligent substation |
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Application publication date: 20170118 |
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| RJ01 | Rejection of invention patent application after publication |