CN106328593B - Using metal oxide as the memory component of substrate and its manufacturing method - Google Patents
Using metal oxide as the memory component of substrate and its manufacturing method Download PDFInfo
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- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 57
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 57
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 title abstract description 9
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 76
- 230000003647 oxidation Effects 0.000 claims abstract description 73
- 238000005516 engineering process Methods 0.000 claims abstract description 26
- 239000010410 layer Substances 0.000 claims description 58
- 239000011229 interlayer Substances 0.000 claims description 43
- 238000003860 storage Methods 0.000 claims description 41
- 239000004020 conductor Substances 0.000 claims description 39
- 238000000034 method Methods 0.000 claims description 34
- 239000010937 tungsten Substances 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 15
- 229910052721 tungsten Inorganic materials 0.000 claims description 15
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 14
- 239000007943 implant Substances 0.000 claims description 9
- 230000003746 surface roughness Effects 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 239000000203 mixture Substances 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 5
- 239000007772 electrode material Substances 0.000 claims 2
- 239000007769 metal material Substances 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 9
- 230000005055 memory storage Effects 0.000 abstract description 2
- 239000011232 storage material Substances 0.000 abstract description 2
- 238000006243 chemical reaction Methods 0.000 description 9
- 238000009826 distribution Methods 0.000 description 8
- 239000007789 gas Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000001000 micrograph Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- DZKDPOPGYFUOGI-UHFFFAOYSA-N tungsten(iv) oxide Chemical compound O=[W]=O DZKDPOPGYFUOGI-UHFFFAOYSA-N 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- -1 Ta) Chemical compound 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 239000001272 nitrous oxide Substances 0.000 description 2
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 description 2
- 230000001737 promoting effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 239000013077 target material Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 150000003657 tungsten Chemical class 0.000 description 2
- 229910001930 tungsten oxide Inorganic materials 0.000 description 2
- 229910001934 tungsten pentoxide Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- VIKNJXKGJWUCNN-XGXHKTLJSA-N norethisterone Chemical compound O=C1CC[C@@H]2[C@H]3CC[C@](C)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1 VIKNJXKGJWUCNN-XGXHKTLJSA-N 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000008961 swelling Effects 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- CMPGARWFYBADJI-UHFFFAOYSA-L tungstic acid Chemical compound O[W](O)(=O)=O CMPGARWFYBADJI-UHFFFAOYSA-L 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- Optics & Photonics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
The memory component and its manufacturing method that the invention discloses a kind of using metal oxide as substrate, especially have using metal oxide manufactured by bias plasma oxidation technology as the memory component of the memory storage material of substrate, this bias plasma oxidation technology can improve the interface between memory cell and top electrodes, with electric field more evenly when making operation, can lift elements reliability.
Description
Technical field
The memory component (devices) that the invention relates to a kind of using metal oxide as substrate and these
The manufacturing method of element；Especially have with bias plasma oxidation technology (biased plasma oxidation
Process the metal oxide manufactured by) is the memory component of the memory storage material of substrate, the oxidation of this bias plasma
Technique can improve the interface between memory cell (elements) and top electrodes, with electric field more evenly when making operation,
Can lift elements reliability.
Background technique
Resistive random access memory (resistive random access memory, RRAM or ReRAM) is one
Kind of nonvolatile memory (nonvolatile memory), it is possible to provide small memory cell size, expandability
(scalability), supper-fast operation, low-power operation, high-durability (endurance), good data keeping quality
(retention), high on-off ratio (on/off ratio), and with complementary metal oxide semiconductor (complementary
Metal-oxide semiconductor, CMOS) compatibility (compatibility) the advantages that.With metal oxide layer
Resistive random access memory can by apply be adapted for carrying out the electric pulse (electric in integrated circuit
Pulses), change resistance value and between two or multiple stable resistance ranges, and these resistance values can and pass through arbitrary access
(random access) reads or is written, to show the data information being stored.
Resistive random access memory may include the gold in the current path between first electrode and second electrode
Belong to oxide memory cell.This electrode can be the endpoint for access devices, and/or may be coupled to access line, access line example
Such as bit line, wordline and source electrode line.These access lines are connected to circuit to execute operation, such as setting (SET) is operated and answered
Position (RESET) operation changes the state of memory component by these operations to store data information.
In the prior art, for the side of the formation memory cell in the storage unit of resistive random access memory
Method has used chemical vapor deposition (chemical vapor deposition, CVD) to carry out deposited metal plug, and e.g. tungsten is inserted
It fills in (tungsten plug).Wherein, this tungsten plug is come by rapid thermal oxidation (rapid thermal oxidation, RTO)
It is aoxidized.Oxidation procedure forms metal oxide layer, is used as the memory cell of storage unit.Top electrodes deposition
On the surface being oxidized.However, being formed by oxidized surface by oxidation procedure is coarse, electric field when may cause operation
It is uneven, and influence the reliability of element.Moreover, opposite which results in having with storage unit made of manufactured by this technique
Low resistance, and the resistance value consistency between storage unit and storage unit is reduced, so being located at single memory component
In storage unit have wider resistance value range.
Therefore the one kind in need that provides can provide the storage unit and such storage unit of uniform electric field when operation
Manufacturing method.It is more in need that the manufacturing method of a kind of storage unit and storage unit is provided, make to be located in single element and deposit
Storage unit resistive memory cell value with higher, and promote the resistance value consistency with other storage units.
Summary of the invention
Description remembers layer depositing as substrate as the memory component of substrate, such as using tungsten oxide using metal oxide memory layer
Memory element and its manufacturing method.
About one embodiment of memory component, including first electrode and second electrode, and be located at first electrode and
Between second electrode and it is electrically coupled to the memory cell of first electrode and second electrode.In an example embodiment, deposit
Storage unit includes the interface smooth arc (arcuate) for being rounded the edge of (rounded) and being constituted with second electrode.
A kind of embodiment of the manufacturing method of memory component is provided, is included the following steps.Use chemical vapor deposition work
The bottom floor units of skill deposition interlayer form of conductors in the interlayer hole (via) being formed in inside insulating layer, such as tungsten plug.This tungsten
Plug is to be aoxidized for example, by the technique of rapid thermal oxidation, and form metal oxide layer.The oxidized portion of tungsten plug
Compared to the tungsten plug originally formed, there is biggish volume and rougher surface.It carries out bias plasma and aoxidizes work
Skill reduces the volume of the oxide material in metal oxide layer, and remaining gold further in the oxide skin(coating) of oxidized metal
Belong at least a part of in oxide.Moreover, this bias plasma oxidation technology forms smooth and sphering arc table
Face to deposit top electrodes, and improves the distribution of oxygen element in metal oxide layer.Compared to not carrying out bias plasma
Oxidation technology, electric field of deposition top electrodes when smooth and sphering curved surfaces make operation is more evenly.And but also
Storage unit made of as manufactured by bias plasma oxidation technology has compared to not using bias plasma oxidation work
The higher resistance of storage unit made of skill is manufactured, and the resistance value consistency between storage unit is also higher.For manufacturing
The method of memory component can further include to be formed for being read and write operation (such as setting and reset operation)
Circuit.In some embodiments, memory cell can be by using above-mentioned bias plasma method for oxidation not aoxidize
Interlayer conductor formed.
Structure and method of the invention is the detailed description disclosed as after.Other aspects and advantage of this disclosure,
It can be understood by schema and detailed narration below.
Detailed description of the invention
The present invention will be illustrated for specific embodiment and referring to following figures, in which:
Figure 1A is the circuit diagram of the storage unit according to depicted in an embodiment.
Figure 1B is the circuit signal of the crosspoint according to depicted in an embodiment (cross-point) memory cell array
Figure.
Fig. 2 is the simplification cross-sectional view of the structure for the first embodiment for being painted variable resistance memory unit.
Fig. 3 A to Fig. 3 D is the structural profile illustration that each manufacturing step of storage unit is painted according to an embodiment.
Fig. 4 A is the transmission electron microscope image of corresponding diagram 3B.
Fig. 4 B is the transmission electron microscope image of corresponding diagram 3D.
Fig. 5 A is the simplification cross-sectional view of the structure for the second embodiment for being painted variable resistance unit.
Fig. 5 B is the transmission electron microscope image of corresponding diagram 5A.
Fig. 6 A and Fig. 6 B are to be painted the resistance value distribution figure that memory cell is formed by by different process.
Fig. 7 is the simplification block diagram of the IC array according to depicted in an embodiment.
[symbol description]
10: integrated circuit
14: word-line decoder and driver
16: wordline
18: bit line decoder
20: bit line
22: bus
24: the block with sensing amplifier and data input structure
26: data/address bus
28: Data In-Line
30: other circuits
32: DOL Data Output Line
34: controller
36: bias arrangement Voltage Supply Device
100: storage unit
102: transistor
104: first end point
106: the second endpoints
108: memory cell
110: the first access lines
112: the second access lines
114: third access line
202: interlayer conductor
204: insulation dielectric layer
206: electrode surface
208: the first metal oxide layers
210: the second metal oxide layers
212: top electrodes
601~618: resistance value distribution
Specific embodiment
Although the content of following exposure is referring to specific constructive embodiment and method.But it is to be understood that having no
The range of this disclosure is only defined in the embodiment and method specifically disclosed by meaning, other still can be used in the content of this exposure
Feature, element, method and embodiment are implemented.Described preferred embodiment is intended merely to the example as this disclosure
Show, but be not used to limit its range, the range of this disclosure is subject to defined in aftermentioned scope of the claims.Institute
Category field has usually intellectual for cognizable to various equivalent deformations described in the following contents.In multiple and different embodiments,
Similar element is usually indicated with similar component symbol.
Figure 1A circuit diagram according to depicted in the storage unit 100 of an embodiment.Storage unit 100 includes transistor
The access devices of 102 forms, this transistor 102 have first end point 104 and the second endpoint 106.Storage unit includes being located at the
Memory cell 108 between end point 104 and the first access line 110, in the present embodiment, the first access line 110 is bit line,
And the second access line 112 is further included, in the present embodiment, the second access line 112 is the source electrode line for connecting the second endpoint 106.?
In using transistor 102 as the embodiment of access devices, memory component can further include third access line 114, in such implementation
In example, third access line 114 is to connect the wordline of the grid of transistor 102.In another embodiment, access devices can be two
Depicted 100 crosspoint array of storage unit in pole pipe, such as Figure 1B.It in the present embodiment, does not include third access line.
Fig. 2 is the simplification cross-sectional view of the structure for being painted the first embodiment of memory cell 108 of variable resistance.Interlayer conductor
202 extend through insulation dielectric layer 204, and insulation dielectric layer 204 is for example silicon dioxide layer.Interlayer conductor 202 is in one end
May be coupled to access devices, for example, access transistor drain terminal or diode end point.In the embodiment described,
Interlayer conductor 202 is tungsten plug.However, the material of interlayer conductor can be other metals, such as titanium in some embodiments
(titanium, Ti), tantalum (tantalum, Ta), aluminium, titanium nitride, tantalum nitride, copper and hafnium (hafnium, Hf).And in some
In embodiment, interlayer conductor layer can be surrounded by a liner layer, this liner layer is, for example, titanium nitride liner.
Memory cell 108 is on the electrode surface 206 of interlayer conductor 202.Memory cell has, such as Fig. 2
Cross-section structure shown in shown in arc external form, the dome-shaped surface (domelike) of smooth sphering.The embodiment shown in
In, memory cell 108 be it is writable at least two or more resistance states.Although memory cell is shown in Fig. 2
Being includes that first metal oxide layer 208 and one that can clearly separate can understand the second metal oxide layer 210 that separate.So
And in some embodiments, the first metal oxide layer and the second metal oxide layer can with or without clear boundary,
Herein so attempt referred to as the first metal oxide layer and the second metal oxide layer, be in order to described in being expressed as follows
The embodiment of memory unit is formed as manufactured by two different oxidation procedures.First metal oxide layer 208 and the second metal
Oxide skin(coating) 210 can respectively include the oxide (WO of one or more tungstenx), for example tungstic acid (WO3), tungsten pentoxide
(W2O5), tungsten dioxide (WO2) one of or it is a variety of.Second metal oxide layer 210 is by bias plasma as described below
Manufactured by body oxidation technology.Positioned at the top of memory cell 108, the especially top of the second metal oxide layer 210, for top
Portion's electrode 212 is access line in this embodiment.
The portion of storage unit, especially memory cell can be formed by manufacturing step depicted in Fig. 3 A to Fig. 3 D
Point.The explanation of this technique highlights the memory cell elements of storage unit, and ignore access devices, in storage unit for spy
Determine the element and array configuration of access devices and access line.
As shown in Figure 3A, interlayer conductor 202 is the interlayer hole being placed through in insulation dielectric layer 204 and is formed, such one
Come the bottom end contact access line of interlayer conductor 202 or the endpoint of access devices.In the embodiment shown in, interlayer conductor 202
For tungsten plug.Tungsten plug can be formed among interlayer hole by the chemical vapor deposition of tungsten material.Being formed by plug is from right
Quasi- (self-aligned) is in interlayer hole.In some embodiments, after forming plug, it will do it such as chemical machinery and grind
Grind the planarization steps of (chemical mechanical polishing).
Then, carrying out oxidation step makes the tip portion oxidation of interlayer conductor continue one section of first time, and is formed as schemed
Structure depicted in 3B.For example, thermal oxidation technology can be 500 by the way that the tip portion of interlayer conductor is exposed to temperature
DEG C, flow velocity is to continue to come for 1 minute in the oxygen of 10 standard liters (standard liters per minute, slm) per minute
It completes.The first metal oxide layer 208 is formed on interlayer conductor 202 in this approach, has and is formed on interlayer conductor
The advantages of self aligned metal oxide layer.This first oxidation step may include rapid thermal oxidation process.This oxidation technology can
It can cause to expand, so that the volume of the material after oxidation at most about is used to generate the three of the non-oxidation material volume of oxidation material
Times.Moreover, the top surface surface still more unoxidized than former interlayer conductor 202 after oxidation is come coarse.It can be observed in Figure 4 A
This swelling.Wherein, Fig. 4 A is the transmission electron microscope image corresponding to Fig. 3 B.
The rough surface as depicted in Fig. 3 B and Fig. 4 A is not desired as a result, because of top electrodes 212 are deposited on
It is formed by the rough surface of memory cell 108 by aoxidizing tungsten plug, non-uniform interface may be generated, as a result
Cause the spacing between the curvature and top electrodes and bottom electrode of interlayer conductor edge across metal oxide layer, Ke Nengyu
Variation is generated in single memory cell or between storage unit and storage unit.The variation of spacing can be in the operation of element
Non-uniform electric field is caused, and influences the reliability of element.The variation of edge may cause the electric field gain in corner
The variation of (field enhancement), and the uniformity that element shows in entire array may be influenced.Therefore, having used can
The technique of the more evenly smooth surface of sphering is formed on the edge of metal oxide memory cell.In order to form smooth table
Face can carry out again bias plasma oxidation technology after forming the first metal oxide layer, be formed as depicted in Fig. 3 C
Structure.As depicted in Fig. 3 C, memory cell 108, and memory list are modified with oxidation technology with bombardment (bombardment)
Member 108 may include being formed by the first metal oxide layer 208 by interlayer conductor indium and aoxidizing institute's shape by bias plasma
At the second metal oxide layer 210 combination.
Bias plasma oxidation technology includes that the bombardment similar with sputtering (sputtering) is generated in same step
Effect, can by the surface smoothing of metal oxide layer, and combine can further oxidation package contain the material previously aoxidized
The oxidation technology of interlayer conductor tip portion.Bombardment is with oxidation as a result, to be located at the metal oxide on interlayer conductor
Memory cell 108, as depicted in the arc external form of Fig. 3 C, the corner with dome-shaped surface and sphering.Bias plasma
Oxidation technology also can sphering around the corner of the insulation dielectric layer 204 of interlayer conductor 202, and produce a smooth surface and use
To deposit top electrodes.Moreover, bias plasma oxidation procedure can improve the oxygen element in the first metal oxide layer 208 point
Cloth, and then improve the performance of element.
Plasma for bias plasma oxidation technology may be from single kind or multiple gases.Plasma is to use
Bombard, aoxidize, or both combination.Plasma gas for bombardment can be argon gas and/or oxygen, be used for aoxidizing
Plasma gas can be oxygen.And such as nitrous oxide (nitrous oxide, N2O) gas can dual-purpose as bombardment and
Oxidation plasma gas used.Bias plasma oxidation technology can be carried out with single step or multi-step, and may include
Separated implant steps and oxidation step, and/or including bombarding the combination step carried out simultaneously with oxidation.For example, it bombards
Effect may be from the bias oxonium ion for being aoxidized, such bias plasma oxidation technology can by single step,
Pure gas is completed.
In the bias plasma oxidation technology for including implant steps, it is transferred to the bombardment gross energy of target material surface, with
And the initial roughness of target material surface, it is the surface roughness (surface roughness) for determining memory cell finished product
Principal element, therefore be also the main determining factor of the interface uniformity of memory cell and top electrodes.Bombarding energy is
It is determined by the amount of the bombardment plasma of one or more implant steps with type, bias, power and duration.The
The thickness of two metal oxide layers is determined by the oxidation step in bias plasma oxidation technology, and can be by oxidation step
In bias voltage, process time, pressure and/or temperature controlled.The second gold medal in multiple embodiments, on memory cell
Belong to oxide skin(coating) 210 thickness between about 30 to 50 angstroms (angstrom,) between.
After bias plasma oxidation technology, resistive random access memory, the effect of the smooth structure of sphering
Benefit, the top corners including the interlayer conductor in entire array have the electric field more evenly enhanced.The shape in corner is for behaviour
The condition of work is important, because the shape that electric field when operation will receive corner influences.Rounded structure also facilitates to lower angle
Fall the variation of shape, and the uniformity of lift elements and operating condition.In multiple embodiments, the memory cell in need that makes
Top surface has the surface roughness RA lower than 3 nanometers of r.m.s.s (root-mean-square, RMS), electricity when promoting operation
The uniformity of field.Surface roughness RA, for the resulting value in section for analyzing memory cell.The section of top section is to correspond to
The external form of the top surface of memory cell.Through fitting algorithm (fitting algorithm), most close fitting section is calculated
Top section equation.The equation for defining matching line segment can be for arbitrarily including such as camber line or parabola (parabola)
Etc. linear equation.Then, roughness can be calculated as from fit line to true section-top external form part, with fitting
Average deviation (average deviation) on the orthogonal direction of line.
Fig. 4 B corresponds to Fig. 3 D, is to be painted to be applied to tungsten oxide shown in such as Fig. 4 A with bias plasma oxidation technology
Plug is formed by the transmission electron microscope striograph of partial memory cell.The parameter of this technique includes: that bias is 100 volts
Special (volt, V), radio frequency (radio frequency, RF) power are 600 watts (watt, W), the time is 60 seconds, and are carried out 2 times.
The comparative example of element and manufacturing method, including bias plasma oxidation is carried out to unoxidized interlayer conductor, to be formed as schemed
Memory cell shown in 5A and Fig. 5 B.Wherein, Fig. 5 A and corresponding transmission electron microscope striograph Fig. 5 B, wherein storing
Element includes as being similar to the second metal oxide layer 210 manufactured by embodiment shown in Fig. 3 A to Fig. 3 D.In Fig. 5 B, tungsten
Plug interlayer conductor 202 is aoxidized by bias plasma set by following parameters: bias is 100 volts, radio-frequency power is
600 watts, the time be 60 seconds.
Fig. 6 A and Fig. 6 B are painted the resistance value distribution that memory cell is formed by with different method for oxidation.Fig. 6 A is painted only
By the various resistance value distributions 601 to 607 of rapid thermal oxidation memory cell manufactured under different temperatures.Wherein 601 to
607 temperature respectively represented are 350 DEG C, 400 DEG C, 450 DEG C, 500 DEG C, 550 DEG C, 600 DEG C, 500 DEG C.Fig. 6 B is painted as in figure
Left side is by rapid thermal oxidation plus bias plasma oxidation (being indicated with ROT+Biased Plasma Oxidation) in not
With the various resistance value distributions 612 to 618 of memory cell manufactured under Fabrication parameter, and only by bias on the right side of in figure
Plasma oxidation (indicates) memory cell manufactured under Yu Butong Fabrication parameter with Biased Plasma Only
Various resistance value distributions 608 to 611, these Fabrication parameters include different rapid thermal oxidation temperature and plasma oxygen
Atmospheric pressure, power and the voltage of change.Wherein 608 bias plasma oxidation reaction condition is 30 millitorr of air pressure
600 watts of (millitorr, mT), power, 140 volts of voltage；609 reaction condition is 30 millitorrs, 600 watts, 180 volts；610
Reaction condition be 20 millitorrs, 600 watts, 100 volts；611 reaction condition is 30 millitorrs, 700 watts, 100 volts.612 it is fast
Speed heat oxidation reaction condition is 450 DEG C of temperature, and bias plasma oxidation reaction condition is 30 millitorrs, 600 watts, 180 volts；
613 reaction condition is 450 DEG C, 20 millitorrs, 600 watts, 100 volts；614 reaction condition be 450 DEG C, 30 millitorrs, 700 watts,
100 volts；615 reaction condition is 500 DEG C, 30 millitorrs, 600 watts, 180 volts；616 reaction condition be 500 DEG C, 30 milli
Support, 700 watts, 100 volts；617 reaction condition is 550 DEG C, 30 millitorrs, 600 watts, 180 volts；618 reaction condition is 550
DEG C, 30 millitorrs, 700 watts, 100 volts.Furthermore 612 to 618 rapid thermal oxidation time is 30 seconds, 608 to 618 bias etc.
The oxygen gas flow rate of gas ions oxidation is 400 standard liters per minute, and the time is 60 seconds.As shown, compared to by quick
Thermal oxide aoxidizes the resistance value distribution of manufactured person plus bias plasma, only the resistance of the person as manufactured by rapid thermal oxidation point
Cloth is lower and relatively wide.As it can be seen that if only the initial resistance of the person as manufactured by rapid thermal oxidation is lower, additional plasma oxidation
The resistance value range for changing element makes it have preferable operating condition, and has higher and more consistent resistance value.And
As shown, promoting tungsten plug oxidation to be formed by memory cell by bias plasma oxidation step, resistance is higher than
Only the person as manufactured by rapid thermal oxidation and manufactured person is aoxidized plus bias plasma by rapid thermal oxidation.Initial resistivity value
Change so that can be used to finely tune operating condition range expand, operating condition include generate voltage (forming
Voltage), setting/reset voltage and electric current and durability.
Fig. 7 is the simplification block diagram of integrated circuit 10, and integrated circuit 10 includes having and being aoxidized with metal as depicted in Figure 1B
Storage unit crosspoint array of the object as the memory of substrate.Word-line decoder (decoder) 14 is coupled to and is electrically connected
To a plurality of wordline 16.Bit line decoder (column decoder) 18 is electrically connected at multiple bit lines 20, for depositing from multiple in array
Storage unit (not being painted) reads data and writes data into multiple storage units in array.Address is provided to bus
(bus) 22, then arrive word-line decoder and driver 14 and bit line decoder 18.With sensing amplifier (sense
Amplifier) bit line is coupled to via data/address bus 26 with the block 24 of data input structure (data-in structure) to translate
Code device 18.The number of data source inside or outside input/output terminal or other integrated circuits 10 from integrated circuit 10
According to via data input structure of the Data In-Line 28 into block 24.It may include other circuits 30 in integrated circuit 10, such as
General processor (general purpose processor) or special-purpose applications circuit (special purpose
Application circuitry), or system-on-a-chip (system-on-a-chip) function is provided, and by storage unit
The combination for the multiple module that the array of 100 compositions is supported.The data of data input structure, defeated via data in block 24
Data destination inside or outside outlet 32 to the input/output terminal of integrated circuit 10 or other integrated circuits 10.
The controller 34 implemented in this uses bias arrangement state machine (bias arrangement state
Machine the applications of Voltage Supply Device (bias arrangement supply voltages) 36 bias arrangements, example are controlled)
Such as read voltage, write-in voltage and write verification voltage (program verify voltage).Controller 34 can be by making
Implemented with known special-purpose applications circuit.In multiple alternate embodiments, controller 34 includes general processor, can
Implement on identical integrated circuit being operated with execution computer procedures control element.In other multiple embodiments, controller
34 it is implementable for use special-purpose applications circuit and general processor combination.
It should be understood that memory array should not necessarily be limited to array configuration as shown in Figure 1B, other other battle arrays
Column configuration can also be used for the above-mentioned disclosed storage unit including memory unit.
Although the present invention is disclosed in detail with embodiment through above-mentioned preferable embodiment, should it is to be understood that this
A little embodiments are intended to illustrative and not limiting.It is contemplated that the technical field of the invention tool usually intellectual can be easily
Expect improvement of the invention with combine, these improve and combine also among spirit of the invention, with aftermentioned claim model
Within enclosing.
Claims (14)
1. a kind of method for manufacturing a storage unit, comprising:
It forms an interlayer conductor and extends through an insulating layer, wherein a first end of the interlayer conductor is coupled to an access devices
End point；And
A memory cell is formed from a second end of the interlayer conductor, comprising:
One implant steps form a smooth arc tip portion in a section of the memory cell；And
One oxidation step generates multiple metal oxides in the memory cell, and wherein the metal oxide includes by one
One second metal oxide layer that two materials are formed, which is by a bias plasma oxidation technology institute
Manufacture.
2. according to the method described in claim 1, wherein the implant steps and the oxidation step system are implemented on a metal oxide
On material.
3. according to the method described in claim 1, the storage unit includes wherein after the implant steps and the oxidation step
One arc-shaped top of one metal oxide materials, the surface roughness of the arc-shaped top is less than 3 nanometers.
4. according to the method described in claim 1, wherein the implant steps and the oxidation step are included in a bias plasma
In body oxidation technology.
5. according to the method described in claim 4, wherein the bias plasma oxidation technology system is implemented on a metal oxide
On layer, which formed by a rapid thermal oxidation process of the interlayer conductor.
6. according to the method described in claim 1, wherein the implant steps are the insulating layers that will be in close proximity to the memory cell
It is edge rounded.
7. according to the method described in claim 1, wherein the memory cell by the interlayer conductor metal material multiple oxygen
Chemistry and Physics Institute's composition.
8. according to the method described in claim 1, wherein the memory cell is characterized by having a writable resistance value.
9. a kind of method for manufacturing a storage unit, comprising:
It forms an interlayer conductor and extends through an insulating layer, wherein a first end of the interlayer conductor is coupled to an access devices
End point；And
A memory cell is formed from a second end of the interlayer conductor, comprising:
Aoxidize a part of the second end of the interlayer conductor；
It when aoxidizing the interlayer conductor or aoxidizes and uses an implant steps after the interlayer conductor, form a metal oxide layer,
A cambered top end part with surface roughness (surface roughness) less than 3 nanometers, the wherein metal oxide layer
Including one second metal oxide layer formed by one second material, which is by a bias plasma
Manufactured by oxidation technology；And
An electrode material is deposited on the metal oxide layer.
10. a kind of storage unit, comprising:
One interlayer conductor, extends through an insulating layer, and wherein a first end of the interlayer conductor is coupled to an access devices
End point；
One memory cell, on a second end of the interlayer conductor, and including an oxidized portion, which includes
One second metal oxide layer formed by one second material, second metal oxide layer are aoxidized by a bias plasma
Manufactured by technology；And
One electrode is located on the memory cell, and including an electrode material, wherein the memory cell and the electrode it
Between be formed by an interface, the interface have an arc section of the surface roughness less than 3 nanometers.
11. storage unit according to claim 10, wherein the oxidized portion further includes one formed by one first material
The composition of first metal oxide layer, first material is not identical as the composition of second material.
12. storage unit according to claim 11, wherein first metal oxide layer be located at the electrode and this
Between two metal oxide layers, an interface is formed by between first metal oxide layer and second metal oxide layer
With an arc section.
13. storage unit according to claim 11, wherein first metal oxide layer and second metal oxide
Layer includes the different compositions of the oxide of tungsten.
14. storage unit according to claim 10, wherein being adjacent to the edge of the insulating layer of the memory cell is
It is rounded.
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