CN106328196A - Write-in method of resistive memory device - Google Patents
Write-in method of resistive memory device Download PDFInfo
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- CN106328196A CN106328196A CN201510377405.1A CN201510377405A CN106328196A CN 106328196 A CN106328196 A CN 106328196A CN 201510377405 A CN201510377405 A CN 201510377405A CN 106328196 A CN106328196 A CN 106328196A
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Abstract
The invention provides a write-in method of a resistive memory device. The method comprises the following steps: receiving logic data, and selecting a corresponding selective storage unit; judging the logic level of the logic data; providing a reset pulse to the selective storage unit in the write-in period when the logic data is the first logic level, and providing a set pulse being smaller than a reference write-in current and having a pulse width being a class moment pulse width to the selective storage unit; and providing the reset pulse to the selective storage unit in the write-in period when the logic data is a second logic level, and providing a set pulse being greater than the reference write-in current and having a pulse width being a class moment pulse width to the selective storage unit. The method can avoid logic level misjudgment in the data reading process, caused by overlapping of read current ranges corresponding to a low resistance state and a high resistance state in high temperature environment.
Description
Technical field
The invention relates to a kind of method for writing data, and in particular to a kind of resistance-type memory
The wiring method of device.
Background technology
Nonvolatile memory has the advantage that the data being stored in the most also will not disappear, and is therefore perhaps
Polyelectron product maintains memory element essential to normal operating.At present, resistive random access memory
(resistive random access memory, RRAM) is that the one that industry actively develops is non-volatile
Memorizer, it has, and write operation voltage is low, write is erased, and the time is short, length memory time, non-destructive
The advantages such as reading, multimode storage, simple in construction and required area are little, at following PC and electricity
Great application potential on subset.
In general, resistance-type memory can change silk according to the pulse voltage size applied and polarity
The width of shape conductive path (filament path).Whereby by reversible and non-volatile for resistance value be set as low
Resistance states (low resistance state, LRS) or high resistance state (high resistance state,
HRS), to represent the storage data of Different Logic level respectively.For example, at write mathematical logic 1
Time, can by apply reset pulse (RESET pulse) narrow thread conductive path width with formed
High resistance state.When writing mathematical logic 0, can be by applying opposite polarity setting pulse (SET
Pulse) width of thread conductive path is increased to form low resistance state.Whereby, when reading data,
Logic 1 can be read according to the reading electric current of the different size scope produced under different resistance states or patrols
Collect the data of 0.
But, the thread conductive path in variable resistor element but may be affected by hot environment and not
Stable, cause its data reserve force (data retention) to be tested.Specifically, low resistance state
May increase resistance value because of hot environment, high resistance state may reduce resistance because of hot environment
Value.In the case, the magnitude range reading electric current of corresponding two kinds of resistance states has the possibility of overlap,
Causing when reading data, the storage data of Different Logic level may produce the reading electric current of formed objects,
Thus storage data cannot be properly read.
Summary of the invention
In view of this, the present invention provides the wiring method of a kind of resistive memory device, can be for difference
The data of logic level use polarity identical and vary in size or setting pulse that pulse width is different is carried out
Write operation, with the phenomenon avoiding the magnitude range reading electric current under hot environment to overlap.
The wiring method of the resistive memory device of the present invention receives logical data, and selects the choosing of correspondence
Select memory element.Next, it is determined that the logic level of logical data.When logical data is the first logic level
Time, in address period, first provide replacement pulse to select storage unit, reoffer less than with reference to write electricity
Stream and setting pulse that pulse width is class square pulse width are to select storage unit.When logical data is
During two logic levels, in address period, first provide replacement pulse to select storage unit, reoffer and be more than
With reference to reset current and setting pulse that pulse width is class square pulse width to select storage unit.
The wiring method of the resistive memory device of the present invention receives logical data, and selects the choosing of correspondence
Select memory element.Next, it is determined that the logic level of logical data.When logical data is the first logic level
Time, in address period, first provide replacement pulse to select storage unit, reoffer more than with reference to write electricity
Stream and setting pulse that pulse width is narrow peak pulse width are to select storage unit.When logical data is
During two logic levels, in address period, first provide replacement pulse to select storage unit, reoffer and be more than
With reference to reset current and setting pulse that pulse width is class square pulse width to select storage unit.
Based on above-mentioned, the wiring method of the resistive memory device of the present invention, when receiving Different Logic
During the data of level, all vary in size so that polarity is identical or setting pulse that pulse width is different is carried out
Data write operation.Further, correctly read by the setting of specific reading current range when reading data
Take storage data.Whereby, in high temperature environments, corresponding low resistance state and high resistance state can be avoided
Reading current range overlaps each other, thus for the erroneous judgement of logic level when causing reading data.
For the features described above of the present invention and advantage can be become apparent, special embodiment below, and coordinate
Accompanying drawing is described below in detail.
Accompanying drawing explanation
Fig. 1 is according to the graph of a relation reading electric current before and after the temperature rising shown by one embodiment of the invention.
Fig. 2 is the schematic diagram according to the resistive memory device shown by one embodiment of the invention.
Fig. 3 is the stream of the wiring method according to the resistive memory device shown by one embodiment of the invention
Cheng Tu.
Fig. 4 is the stream of the wiring method according to the resistive memory device shown by one embodiment of the invention
Cheng Tu.
Description of reference numerals:
200: resistive memory device；
210: resistive memory cell array；
212: resistive memory cell；
214: select storage unit；
220: current sense unit；
230: control unit；
BL: bit line；
D: interval；
DATA: logical data；
Iaft, Ibef, IR1, IR2, RI3: read electric current；
IREF, IREF1, IREF2: reference current；
L1, L2: dotted line；
PRESET: reset pulse；
PSET1, PSET2, PSET3: set pulse；
SL: source electrode line；
Each step of the wiring method of S302～S312, S502～S512: resistive memory device.
Detailed description of the invention
Fig. 1 is according to the graph of a relation reading electric current before and after the temperature rising shown by one embodiment of the invention.
Refer to Fig. 1, wherein the transverse axis of Fig. 1 is (under the room temperature) resistance-type when reading data before temperature raises
Memorizer is produced reads electric current Ibef (unit is milliampere), the longitudinal axis be after temperature raises (such as
Reach 260 degree Celsius) read electric current Iaft produced by resistance-type memory (unit is when reading data
Milliampere).Circle, triangle and square sign point in Fig. 1 represent respectively via reset pulse or
After setting pulse write data, temperature reads the corresponding relation of electric current Ibef Yu Iaft before and after raising.Wherein,
The circular point that indicates is in order to represent reading electric current when applying to reset pulse.Triangle and square sign point are used
To represent reading electric current when applying different size of setting pulse respectively.
Refer to Fig. 1, traditionally, resistance-type memory can form high resistance by applying replacement pulse
State is with the data of such as stored logic 1.And can be formed by applying opposite polarity setting pulse
Low resistance state is with the data of such as stored logic 0.Therefore when reading data, can by correspondence not
Its resistance states is differentiated, to properly read logic 1 or logical zero with the reading electric current of resistance states
Data.But, the most thread conductive path can be affected by temperature, causes reading
The reading electric current of data changes.As it is shown in figure 1, the distribution indicating point will not maintain expression completely
Dotted line L1 equal for reading electric current Ibef with Iaft before and after temperature rising.By Fig. 1 it is apparent that
Reading electric current Iaft same on dotted line L2 can correspond to simultaneously low resistance state (circular indicate point) with
And the reading electric current Ibef of high resistance state (triangle sign point), causing cannot be by just reading electric current
Really differentiate its resistance states, cause and read the error storing data.
But, observe Fig. 1 it is found that for apply vary in size set pulse triangle and
Square sign point, distribution has obvious difference.Wherein, as reading electric current Ibef less than with reference to electricity
The triangle of stream IREF1 (such as 20 micromicroampere) indicates the distribution of point can be from dotted line L1 toward lower-left
Distribution.As reading the electric current Ibef square sign more than reference current IREF2 (such as 25 micromicroampere)
The distribution of point but can be distributed from dotted line L1 toward upper right.It can therefore be concluded that go out corresponding in high temperature environments
Can have bright between the reading electric current Iaft of both states above-mentioned represented by triangle and square sign point
Aobvious interval D, does not have the phenomenon of overlap.Accordingly, the resistance-type storage that the embodiment of the present invention is proposed
Device device and wiring method thereof, be i.e. to utilize the distribution character described in Fig. 1 (to set the reading electric current of pulse
Even if the most also having characteristic that will not be overlapping in specific reading current range), it is right to propose
Answer the method for writing data under hot environment.Will be described below how realizing what the embodiment of the present invention was proposed
The wiring method of resistive memory device.
Fig. 2 is the schematic diagram according to the resistive memory device shown by one embodiment of the invention.Please join
According to Fig. 2, resistive memory device 200 includes resistive memory cell array 210, current sense unit
220 and control unit 230.Resistive memory cell array 210 includes the most several resistive memory cell
212.Resistive memory cell array 210 is coupled to current sense unit 220 by a plurality of bit line BL,
And it is coupled to control unit 230 by many several source electrode lines SL.Each resistive memory cell 212 can
To include switch element, such as gold oxygen partly leads field-effect transistor or bipolarity junction transistor, and variable
Resistive element, and each resistive memory cell 212 can provide the storage data of single bit.
Current sense unit 220 can be any type current measuring element/circuit.Such as, sensing amplifies
Device circuit.Current sense unit 220 can pass through many several bit lines BL coupling resistance formula memory element 212,
And detect electric current produced by resistive memory cell 212.
Control unit 230 can be for example CPU (Central Processing Unit, CPU),
Microprocessor (Microprocessor), digital signal processor (Digital Signal Processor, DSP),
Programmed controller, programmable logic devices (Programmable Logic Device, PLD) or
Other similar devices or the combination of these devices.Control unit 230 is to may be coupled to current sense unit 220
And many several source electrode lines SL of resistive memory cell array 210.Hereinafter i.e. for embodiment, resistance is described
The detailed step of the method for writing data of formula storage arrangement 200.
Fig. 3 is the stream of the wiring method according to the resistive memory device shown by one embodiment of the invention
Cheng Tu.Referring to Fig. 2 and Fig. 3, the present embodiment is applicable to Fig. 2 for the wiring method of logical data
Resistive memory device 200, the most i.e. collocation resistive memory device 200 in each item
Each step of the wiring method of the embodiment of the present invention is described.
In step s 302, control unit 230 can receive logical data DATA, and selects the choosing of correspondence
Select memory element 214.Specifically, the logical data of single bit is received when control unit 230
During DATA, control unit 230 can be by the choosing selecting correspondence in multiple resistive memory cell 212
Select memory element 214.Select storage unit 214 can include switch element and variable resistor element.Control
Unit 230 processed can such as provide and select voltage to crystal as switch element in select storage unit 214
The gate (or base stage) of pipe is to switch it on, to carry out follow-up data for select storage unit 214
Write operation.
In step s 304, control unit 230 can determine whether the logic level of logical data DATA.Tool
For body, control unit 230 can determine whether that the logical data DATA of single bit is logic 1 or logical zero.
When logical data DATA is logic 1 (the first logic level), in step S306, counting
According to address period, control unit 230 can first provide replacement pulse PRESET to select storage unit
214, reoffer setting pulse PSET1 to select storage unit 214.Wherein, pulse PSET1 is set
Polarity with reset pulse PRESET contrary, and set pulse PSET1 current value be less than for example, 100
The reference reset current of micromicroampere, sets pulse width that pulse PSET1 had as specific class square arteries and veins
Rush width (class square pulse width for example, 100 nanosecond), to make selection deposit by setting pulse PSET1
Storage unit 214 becomes high resistance state (high resistance state, HRS).Specifically, select
The variable resistance unit of memory element 214 can for example, oxide basis (oxide-based) resistance-type with
Machine access memorizer.When being intended to make select storage unit 214 reach high resistance the data write of logic 1
During state, control unit 230 can first pass through source electrode line SL and provides and set pulse PSET1 opposite polarity
Replacement pulse PRESET to select storage unit 214, with conduction thread in the variable resistor element that narrows
The width in path resets the resistance value of (raising) variable resistor element.Then, control unit 230 can
Again by source electrode line SL provide less than with reference to reset current and pulse width such as specifically for 100 nanoseconds about
The setting pulse PSET1 of class square pulse width to the variable resistor element of select storage unit 214.Make
Obtain the width adjustment of thread conductive path in variable resistor element extremely to select to when the suitable read voltage of applying
The reading electric current IR1 of reference current IREF can be generated less than during memory element 214.For example, reading
In the case of power taking presses 0.2 volt, reference current IREF for example, 10～20 micromicroampere, but the present invention is not
It is limited according to this.
Then, in order to the reading electric current after determining write data may conform to specifically read current range,
In step S308, control unit 230 can apply read voltage to select storage unit 214, and can
Judge that whether produced test electric current is less than reference current IREF.Specifically, in control unit 230
After providing setting pulse PSET1 to write logic 1 to select storage unit 214, for avoiding thread leading
Not being adjusted to expected width of power path and produce error, read voltage can be applied extremely by control unit 230
Select storage unit 214 first allows current sense unit testing 220 detect produced test electric current.Control
Unit 230 processed can judge to test whether electric current is less than according to the detecting result of current sense unit testing 220
Reference current IREF.
Further, when testing electric current not less than reference current IREF, represent that the thread of variable resistor element is led
The width of power path may be wide.Therefore, returning in step S306, control unit 230 can provide again
Pulse PRESET is to select storage unit 214 in replacement, reoffers less than with reference to reset current and pulse width
The setting pulse PSET1 that degree is class square pulse width is to select storage unit 214, thread again to adjust
The width of conductive path.Afterwards, test again to step S308, until test electric current meets regulation
Till reading current range (less than reference current IREF).
Accordingly, during reading, when control unit 230 applies read voltage to select storage unit 214
Time, current sense unit 220 can will accurately detect the reading electric current met less than reference current IREF
IR1.Further, detecting result can be sent to control unit 230, control unit by current sense unit 220
According to the reading current range less than reference current IREF, 230 can judge that select storage unit 214 is as high electricity
Resistance state, to read the data of logic 1.
On the other hand, when logical data DATA is logical zero (the second logic level), in step S310
In, in the address period of data, control unit 230 can first provide replacement pulse PRESET to deposit to selection
Storage unit 214, reoffers setting pulse PSET2 to select storage unit 214.Wherein, pulse is set
The polarity of PSET2 is contrary with resetting pulse PRESET, and sets the current value of pulse PSET2 more than example
Such as the reference reset current for 100 micromicroamperes, the pulse width that setting pulse PSET2 is had is also for spy
Fixed class square pulse width (class square pulse width for example, 100 nanosecond), with by setting pulse PSET2
Select storage unit 214 is made to become low resistance state (low resistance state, LRS).Specifically,
When being intended to write the data of logical zero and make select storage unit 214 reach low resistance state, control single
Unit 230 can first pass through source electrode line SL and provides and set pulse PSET2 opposite polarity replacement pulse
PRESET, to select storage unit 214, comes with the width of conductive path thread in the variable resistor element that narrows
Reset the resistance value of (raising) variable resistor element.Then, control unit 230 can pass through source electrode line again
SL provides and is more than reference reset current and pulse width such as specifically for the class square pulse width about 100 nanoseconds
The setting pulse PSET2 of degree is to the variable resistor element of select storage unit 214.Make variable resistance unit
In part, the width adjustment of thread conductive path is to when applying suitable read voltage (for example, 0.2 volt)
To producing during select storage unit 214 more than reference current IREF (for example, 10～20 micromicroampere)
Read electric current IR2.And in the present embodiment, because setting the reading electric current model corresponding to pulse PSET2
Enclose higher than the reading current range set corresponding to pulse PSET1, therefore set pulse PSET2 higher than setting
Pulse PSET1, and the polarity setting pulse PSET1 and PSET2 is identical.
Then, in order to the reading electric current after determining write data may conform to specifically read current range,
In step S312, control unit 230 can apply read voltage to select storage unit 214, and can
Judge that whether produced test electric current is more than reference current IREF.Specifically, in control unit 230
After providing setting pulse PSET2 to write logical zero to select storage unit 214, for avoiding thread leading
Not being adjusted to expected width of power path and produce error, read voltage can be applied extremely by control unit 230
Select storage unit 214 first allows current sense unit testing 220 detect produced test electric current.Control
Unit 230 processed can judge to test whether electric current is more than according to the detecting result of current sense unit testing 220
Reference current IREF.
Further, when testing electric current not more than reference current IREF, represent that the thread of variable resistor element is led
The width of power path may be narrow.Therefore, returning in step S310, control unit 230 can provide again
Pulse PRESET is to select storage unit 214 in replacement, reoffers more than with reference to reset current and pulse width
The setting pulse PSET2 that degree is class square pulse width is to select storage unit 214, thread again to adjust
The width of conductive path.Afterwards, test again to step S312, until test electric current meets regulation
Till reading current range (more than reference current IREF).
Accordingly, during reading, when control unit 230 applies read voltage to select storage unit 214
Time, current sense unit 220 can will accurately detect the reading electric current met more than reference current IREF
IR2.Further, detecting result can be sent to control unit 230, control unit by current sense unit 220
According to the reading current range more than reference current IREF, 230 can judge that select storage unit 214 is as low electricity
Resistance state, to read the data of logical zero.It should be noted that, the embodiment of the present invention can't be to difference
Reading the logical data representated by current range to be any limitation as, in one embodiment, control unit 230 is also
Can judge to read the data of logical zero according to the reading current range less than reference current IREF, can be according to being more than
The reading current range of reference current IREF judges to read the data of logic 1.
Therefore, the wiring method implemented by the present invention, utilizing, corresponding specific reading current range is (little
In or more than reference current IREF) settings pulse PSET1 and PSET2 write Different Logic level
In the case of data, even if in high temperature environments, select storage unit 214 also can will not be overlapping reading
Produce the reading electric current of counterlogic 0 or logic 1 in the range of obtaining current respectively, can avoid causing storage number
According to the erroneous judgement of logic level.
In one embodiment, the variable resistor element of control unit 230 adjustable choosing pool memory element 214
Resistance value be zero (such as by two terminal shortcircuits of variable resistor element), and apply read voltage to select
Memory element 214 and produce the reference reset current of corresponding selection memory element 214.
Fig. 4 is the stream of the wiring method according to the resistive memory device shown by one embodiment of the invention
Cheng Tu.Referring to Fig. 2 and Fig. 4, the present embodiment is applicable to Fig. 2 for the wiring method of logical data
Resistive memory device 200, the most i.e. collocation resistive memory device 200 in each item
Each step of the wiring method of the embodiment of the present invention is described.
In step S402, control unit 230 can receive logical data DATA, and selects the choosing of correspondence
Select memory element 214.In step s 404, control unit 230 can determine whether patrolling of logical data DATA
Collect level.These steps S402, S404 system and step S302 of previous embodiment, S304 be identical or phase
Seemingly, thus its detailed content does not repeats them here.
Unlike previous embodiment, in the present embodiment, it is logic 1 (as logical data DATA
One logic level) time, in step S406, control unit 230 can first provide replacement pulse PRESET
To select storage unit 214, reoffer setting pulse PSET3 to select storage unit 214.Wherein,
The polarity setting pulse PSET3 is contrary with resetting pulse PRESET, and sets the electricity of pulse PSET3
Flow valuve, more than the reference reset current of for example, 100 micromicroamperes, sets the pulse that pulse PSET3 is had
Width is specific narrow peak pulse width (narrow peak pulse width for example, 10 nanosecond), with by setting arteries and veins
Rushing PSET3 makes select storage unit 214 become high resistance state.Specifically, when being intended to logic 1
When data write and make select storage unit 214 reach high resistance state, control unit 230 can first pass through
Source electrode line SL provides and sets pulse PSET3 opposite polarity replacement pulse PRESET to selecting storage
Unit 214, resets (raising) with the width of conductive path thread in the variable resistor element that narrows variable
The resistance value of resistive element.Then, control unit 230 can be provided more than with reference to writing by source electrode line SL again
Enter electric current and pulse width such as specifically for the setting pulse of the narrow peak pulse width about 10 nanoseconds
PSET3 is to the variable resistor element of select storage unit 214.Make thread conduction in variable resistor element
The width adjustment in path is to when applying suitable read voltage (for example, 0.2 volt) to selecting storage single
The reading electric current IR3 of reference current IREF (for example, 10～20 micromicroampere) can be generated less than during unit 214.
Then, in order to the reading electric current after determining write data may conform to specifically read current range,
In step S408, control unit 230 can apply read voltage to select storage unit 214, and can
Judge that whether produced test electric current is less than reference current IREF.Specifically, in control unit 230
After providing setting pulse PSET3 to write logic 1 to select storage unit 214, for avoiding thread leading
Not being adjusted to expected width of power path and produce error, read voltage can be applied extremely by control unit 230
Select storage unit 214 first allows current sense unit testing 220 detect produced test electric current.Control
Unit 230 processed can judge to test whether electric current is less than according to the detecting result of current sense unit testing 220
Reference current IREF.
Further, when testing electric current not less than reference current IREF, represent that the thread of variable resistor element is led
The width of power path may be wide.Therefore, returning in step S406, control unit 230 can provide again
Pulse PRESET is to select storage unit 214 in replacement, reoffers more than with reference to reset current and pulse width
The setting pulse PSET3 that degree is narrow peak pulse width is to select storage unit 214, thread again to adjust
The width of conductive path.Afterwards, test again to step S408, until test electric current meets regulation
Till reading current range (less than reference current IREF).
Accordingly, during reading, when control unit 230 applies read voltage to select storage unit 214
Time, current sense unit 220 can will accurately detect the reading electric current met less than reference current IREF
IR3.Further, detecting result can be sent to control unit 230, control unit by current sense unit 220
According to the reading current range less than reference current IREF, 230 can judge that select storage unit 214 is as high electricity
Resistance state, to read the data of logic 1.
On the other hand, when logical data DATA is logical zero (the second logic level), in step S410
In, in the address period of data, control unit 230 can first provide replacement pulse PRESET to deposit to selection
Storage unit 214, reoffers setting pulse PSET2 to select storage unit 214.Wherein, pulse is set
The polarity of PSET2 is contrary with resetting pulse PRESET, and sets the current value of pulse PSET2 more than example
Such as the reference reset current for 100 micromicroamperes, set pulse width that pulse PSET2 had as specific
Class square pulse width (class square pulse width for example, 100 nanosecond), with by set pulse PSET2
Select storage unit 214 is made to become low resistance state.Make thread conductive path in variable resistor element
Width adjustment can be produced to when applying read voltage (for example, 0.2 volt) to select storage unit 214
The raw reading electric current IR2 more than reference current IREF (for example, 10～20 micromicroampere).
Then, in step S412, control unit 230 can apply read voltage to select storage unit
214, and can determine whether that whether produced test electric current is more than reference current IREF.When testing electric current not
During more than reference current IREF, represent that the width of the thread conductive path of variable resistor element may be narrow.
Therefore, returning in step S410, control unit 230 can provide replacement pulse PRESET to selecting again
Memory element 214, reoffers more than with reference to reset current and setting that pulse width is class square pulse width
Pulse PSET2 is to select storage unit 214, again to adjust the width of thread conductive path.Afterwards,
Test again to step S412, until test electric current meets the reading current range of regulation (more than reference
Electric current IREF) till.
Accordingly, during reading, when control unit 230 applies read voltage to select storage unit 214
Time, current sense unit 220 meets the reading electricity more than reference current IREF condition by can accurately detect
Stream IR2.According to the reading current range more than reference current IREF, control unit 230 can judge that selection is deposited
Storage unit 214 is low resistance state, to read the data of logical zero.Even if in high temperature environments, choosing
Select memory element 214 also can produce counterlogic 0 respectively in reading current range that will not be overlapping or patrol
Collect the reading electric current of 1, can avoid causing the erroneous judgement of the logic level storing data.
In sum, the wiring method of the resistive memory device of the present invention, can be for Different Logic electricity
The setting pulse that flat data all vary in size so that polarity is identical or pulse width is different carries out write behaviour
Make.Further, storage data are properly read when reading data by the setting of specific reading current range.
Whereby, in high temperature environments, the reading current range of corresponding low resistance state and high resistance state can be avoided
Overlap each other, thus for the erroneous judgement of logic level when causing reading data.
Last it is noted that various embodiments above is only in order to illustrate technical scheme, rather than right
It limits；Although the present invention being described in detail with reference to foregoing embodiments, this area common
Skilled artisans appreciate that the technical scheme described in foregoing embodiments still can be modified by it,
Or the most some or all of technical characteristic is carried out equivalent；And these amendments or replacement, and
The essence not making appropriate technical solution departs from the scope of various embodiments of the present invention technical scheme.
Claims (10)
1. the wiring method of a resistive memory device, it is characterised in that including:
Receive a logical data, and select a select storage unit of correspondence；
Judge the logic level of this logical data；
When this logical data is first logic level, in an address period, first provide a replacement pulse
To this select storage unit, reoffering less than a reference reset current and pulse width is a class square pulse width
One setting pulse of degree is to this select storage unit；And
When this logical data is second logic level, in this address period, first provide this replacement pulse
To this select storage unit, reoffering more than this reference reset current and pulse width is such square pulse width
One setting pulse of degree is to this select storage unit.
The wiring method of resistive memory device the most according to claim 1, it is characterised in that
This select storage unit includes a variable resistor element, and before receiving the step of this logical data, also
Including:
The resistance value adjusting this variable resistor element is zero, and it is single to this selection storage to apply a read voltage
Unit and produce this reference reset current.
The wiring method of resistive memory device the most according to claim 1, it is characterised in that
Thering is provided less than this reference reset current and this setting pulse that pulse width is such square pulse width to this
After select storage unit, also include:
Apply a read voltage to this select storage unit, and whether judge a produced test electric current
Less than a reference current；And
When this test electric current is not less than this reference current, again provide this replacement pulse single to this selection storage
Unit, reoffers less than this setting pulse that this reference reset current and pulse width are such square pulse width
To this select storage unit.
The wiring method of resistive memory device the most according to claim 1, it is characterised in that
Thering is provided more than this reference reset current and this setting pulse that pulse width is such square pulse width to this
After select storage unit, also include:
Apply a read voltage to this select storage unit, and whether judge a produced test electric current
More than a reference current；And
When this test electric current is not more than this reference current, again provide this replacement pulse single to this selection storage
Unit, reoffers more than this setting pulse that this reference reset current and pulse width are such square pulse width
To this select storage unit.
The wiring method of resistive memory device the most according to claim 1, it is characterised in that
This reference reset current is 100 micromicroamperes, and such square pulse width was 100 nanoseconds.
6. the wiring method of a resistive memory device, it is characterised in that including:
Receive a logical data, and select a select storage unit of correspondence；
Judge the logic level of this logical data；
When this logical data is first logic level, in an address period, first provide a replacement pulse
To this select storage unit, reoffering more than a reference reset current and pulse width is a narrow peak pulse width
One setting pulse of degree is to this select storage unit；And
When this logical data is second logic level, in this address period, first provide this replacement pulse
To this select storage unit, reoffering more than this reference reset current and pulse width is a class square pulse width
One setting pulse of degree is to this select storage unit.
The wiring method of resistive memory device the most according to claim 6, it is characterised in that
This select storage unit includes a variable resistor element, and before receiving the step of this logical data, also
Including:
The resistance value adjusting this variable resistor element is zero, and it is single to this selection storage to apply a read voltage
Unit and produce this reference reset current.
The wiring method of resistive memory device the most according to claim 6, it is characterised in that
Thering is provided more than this reference reset current and this setting pulse that pulse width is this narrow peak pulse width to this
After select storage unit, also include:
Apply a read voltage to this select storage unit, and whether judge a produced test electric current
Less than a reference current；And
When this test electric current is not less than this reference current, again provide this replacement pulse single to this selection storage
Unit, reoffers more than this setting pulse that this reference reset current and pulse width are this narrow peak pulse width
To this select storage unit.
The wiring method of resistive memory device the most according to claim 6, it is characterised in that
Thering is provided more than this reference reset current and this setting pulse that pulse width is such square pulse width to this
After select storage unit, also include:
Apply a read voltage to this select storage unit, and whether judge a produced test electric current
More than a reference current；And
When this test electric current is not more than this reference current, again provide this replacement pulse single to this selection storage
Unit, reoffers more than this setting pulse that this reference reset current and pulse width are such square pulse width
To this select storage unit.
The wiring method of resistive memory device the most according to claim 6, it is characterised in that
This reference reset current is 100 micromicroamperes, and this narrow peak pulse width was 10 nanoseconds, such square pulse width
It it was 100 nanoseconds.
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