CN106326553A - Distributed signal topological relation construction method used for analyzing single-particle and soft-error fault propagation - Google Patents
Distributed signal topological relation construction method used for analyzing single-particle and soft-error fault propagation Download PDFInfo
- Publication number
- CN106326553A CN106326553A CN201610710113.XA CN201610710113A CN106326553A CN 106326553 A CN106326553 A CN 106326553A CN 201610710113 A CN201610710113 A CN 201610710113A CN 106326553 A CN106326553 A CN 106326553A
- Authority
- CN
- China
- Prior art keywords
- circuit
- circuit node
- signal
- information
- node
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Logic Circuits (AREA)
Abstract
The invention relates to a distributed signal topological relation construction method used for analyzing single-particle and soft-error fault propagation and belongs to the technical field of evaluation of single-particle and soft-error reliability in a system. The method comprises the following steps: based on circuit nodes and corresponding inter-signal cascaded information under hardware resource construction in XDL (Xilinx Design Language) net list information, providing a cascaded forward search analysis method of signal cascaded information between the circuit nodes, constructing a directed propagation topological relation between the circuit nodes in the system and finishing circuit signal propagation relation analysis between hardware resources with different types; meanwhile, correlating circuit connection reflected according to an XDL net list and control configuration bit information. According to the method provided by the invention, a configuration information matching rule is provided, and an internal signal propagation path under resource mapping of the circuit nodes is analyzed and constructed; the circuit signal propagation relation analysis under the hardware resources with the specific type is finished.
Description
Technical field
The present invention relates to a kind of distributed signal topological relation structure side propagating for single-particle soft error failure and analyzing
Method, belongs to system single-particle soft error reliability assessment technical field.
Background technology
Currently, in the electronic equipment one-of-a-kind system of AEROSPACE APPLICATION, using Xilinx SRAM type FPGA as core devices structure
The Digital Signal Processing class stand-alone application built is quite varied.But owing to the configuration of SRAM type FPGA will be stored by single particle effect
Position produces impact, and then the annexation of circuit signal in each resource of FPGA can be caused to produce mistake, affects the merit of Circuits System
Energy.Therefore, one-of-a-kind system based on this type of PLD has carried out the evaluation studies of single-particle soft error Reliable Design,
Wherein will relate to the propagation model building circuit signal, and obtain the propagation topological relation between signal, and then it is soft to be used for calculating system
Error reliability evaluation index.
Currently, the technique study built about signal topological relation is the analysis method using rtl netlist, and it analyzes knot
Fruit can only provide the clock signal topological relation of elementary cell logical layer, it is impossible to Efficient Characterization goes out single particle effect and patrols able to programme
Collect the impact in circuit and communication process.
Summary of the invention
The technology of the present invention solves problem: overcome the deficiencies in the prior art, proposes one for the event of single-particle soft error
Barrier propagates the distributed signal topological relation construction method analyzed.
The technical solution of the present invention is:
A kind of distributed signal topological relation construction method propagating analysis for single-particle soft error failure, step bag
Include:
(1) first stage, the preparatory stage is designed；
According to user to signal propagate topological relation range of application design requirement, can to VHDL Engineering Documents according to
The vhd functional module of system top level functional module and other level divides, thus completes the input of functional module, outfan message
Number extract, and generate the XDL net meter file after each functional module comprehensive maps；
Step 1: defined function block code section；The storehouse that it is mark with keyword library that functional module code segment includes
Quote part, with keyword entity for mark entity part and with keyword architecture be mark structure body
Point；
Step 2: import the VHDL Engineering Documents of Circuits System, according to VHDL Engineering Documents in ISE instrument
Level divide relation, obtain top layer and other each level functional module and corresponding code segment and corresponding function module respectively
Input/output signal port name；
Step 2-1: the VHDL Engineering Documents of input circuit system, by ISE instrument identification each level functional module；
Step 2-2: according to (keyword library is that part is quoted, with keyword in the storehouse of mark with functional module code segment
Entity be mark entity part and with keyword architecture be mark structure part) format code divide
Functional module, the functional module code segment after dividing successively is stored in the new vhd file of correspondence, and new vhd file is with function
Entity (entity) name name in block code section, the most newly-generated vhd file is the functional module of former FPGA engineering, vhd literary composition
The functional module name of the entitled correspondence of file of part；
Step 2-3: according to the functional module generated, obtain the input signal end of corresponding function module with port interface definition
Mouth name and output signal port name；
Step 3: signal is propagated the design requirement of topological relation range of application according to user, selects corresponding function mould
Block, completes comprehensively to map in ISE instrument, firstly generates ncd file, and the ncd2xdl order calling ISE subsequently generates XDL net
List file.
(2) second stage, net meter file resolves
Step 4: complete circuit node cascade sweep forward and resolve；
The method that search resolves is: with the circuit section of the input signal port name name that step 2-3 of functional module obtains
Point starts, and according to the information in the XDL net meter file that step 3 generates, obtains input and output signal between circuit node successively
Cascade connection, until functional module step 2-3 obtain output signal port name name node till, it is achieved dissimilar
Under configuration resource, the signal between circuit node propagates relation analysis.Wherein, circuit node represents the XDL netlist literary composition that step 3 generates
With the information of " inst " keyword definition in part, with the information of " inst " keyword definition be called FPGA Slice,
The circuit structure that Block RAM or IOB resource are formed, signal between this circuit node propagates that relation is follow-up be can be used for point
Analysis signal calculates because of single-particle soft error, the soft error error rate of circuit node.
Step 4-1: by the oriented logical circuitry of XDL net meter file conformation function module, oriented logical circuitry defines
For G (V1, E), in XDL net meter file, " inst " circuit node is V1Representing the end points in directed graph, " net " contains logic
In circuit diagram, the oriented signal between circuit node transmits link information, is stored in E；E represents the oriented transmission of circuit node
Line set；
Step 4-2: connect based on the circuit node defined with " inst " in XDL net meter file and the circuit comprised and close
The configuration bit information of system, is defined as V by the node set of be likely to occur single particle effect1；For it may happen that single-particle
The node of effect is circuit node keyword with " inst ", calls the roll as circuit section using the alphabetical information after " inst ", is stored in
V1In, thus obtain traversal set V1{ni, 1≤i≤N}, wherein, niCalling the roll for i-th circuit section, N is V1The institute that traversal obtains
There is circuit node number；
Step 4-3: for i-th circuit node, component cascade sweep forward analytic method finds current circuit section to call the roll
For niThe all nodes that can reach in circuit, it is achieved process is as follows:
Step 4-3-1: " inst " keyword in search XDL net meter file, and it is defined as i-th with alphabetical information thereafter
The node name n of circuit nodei, 1≤i≤N, by niInformation is stored in V1；
Step 4-3-2: search for the field information initial with keyword " net " in XDL net meter file, wherein comprises current
Output circuit node name and next stage cascade input circuit node name, and corresponding circuits output signal node name and input signal
Name, builds circuit node oriented chain list structure figure, and list structure figure includes the circuit section roll-call n of circuit node ii, electricity
Circuit node output signal name outpin, subsequent cascaded oriented circuit section roll-call XX, YY, Yy；The input signal name of XX circuit node
Aa, output signal name aa`, input signal name bb of YY circuit node, output signal name bb`, the input signal of Yy circuit node
Name Bb, output signal name Bb`；Current circuit node fanout k, t to next stage cascade circuit output signal node；Module is defeated
Go out circuit section roll-call O and input signal name inpin；
Step 4-3-3: resolve circuit node information, if currently according to the chain list structure figure that step 4-3-2 builds
The most corresponding next cascade circuit node input signal name unique of circuit node i output signal, then it represents that circuit node i signal exports
Singly it is fanned out to the circuit node of next stage cascade input signal, jumps to step 4-3-4 and continue search for circuit node；If it is current
Circuit node i output signal output fanout cascades the circuit node of input signal more than or equal to 2 to plural next stage,
Jump to step 4-3-5 and continue search for circuit node；
Step 4-3-4: for circuit node output signal list fan-out situation, by fixed next stage cascade circuit node
Circuit node associated by Ming is defined as i+1 cascade circuit node (i < i+1≤N), and circuit node information is stored in V1,
And oriented for circuit node signal transmission information is saved in E, until it is that O/inpin terminates that circuit node searches information, jump
Go to step 4-4；Otherwise, step 4-3-2～step 4-3-3 are repeated；
Step 4-3-5: for circuit node output signal fanout situation, set up multi-path signal respectively according to fanout
Transmission line, simultaneously according to difference transmission line search subsequent conditioning circuit node, saves fixed current next stage cascade circuit
Circuit node associated by roll-call re-defines for i+1 cascade circuit node (i < i+1≤N), and circuit section is called the roll information
It is stored in V1, the circuit node oriented signal transmission information of different fan-outs is saved in E, until circuit node searches information and is
O/inpin terminates, jump procedure 4-4；Otherwise, step 4-3-2～step 4-3-3 are repeated；
Step 4-4: obtain G (V according to the effective transmission information in chain list structure figure1, E) topological sorting,
Construct the circuit node forward direction circuit transmission topological relation of functional module；
Step 5: formulate configuration information coupling rule, resolves netlist circuit node internal signal transmission information, i.e. according to each
Circuit node internal structure is called in the different resource of Slice, Block RAM, IOB, and XDL net meter file under circuit node
Keyword " cfg " contained by the configuration bit information of content mate, it is achieved under certain types of circuit node configuration resource
Signal propagate relation analysis.The follow-up circuit node internal signal that can be used for of this transmission relation, because of single-particle soft error, carries out electricity
The analytical calculation of circuit node soft error error rate.
Step 5-1: coupling rule 1, circuit node maps resource information coupling.Resolve " inst " bag in XDL net meter file
Containing information, the position that its corresponding circuits node name, configuration resource and resource are placed in the devices.Different circuit nodes may
Corresponding other such as Slice, Block RAM resource；
Step 5-2: coupling rule 2, logic circuit unit signal-line choosing transmission information matches.Based on step 5-1, at electricity
Circuit node inner search is with the configuration bit information that " cfg " is that keyword comprises, and this information is that circuit node is in correspondence mappings resource
The transmission of lower control each circuit logic cell input signal and output signal selects；
Step 5-3: coupling rule 3, circuit signal transmission controls configuration bit and resolves coupling.Based on step 5-2, search by field
Rope comprises " * *:: * * " sign bit information, and before ":: " symbol, the logical block name of information indication circuit, is equal to Xilinx
To logic circuit unit name nominating rule in FPGA device internal resource；After ":: " symbol, information represents circuit logic unit
Control bit selects, if being entered as " #OFF " expression not configure this circuit logic unit control bit, other assignment then counterlogic
The signal transmission of unit controls configuration bit, and under different resource, circuit node completes the inside under control bit configuration information coupling
The structure in the defeated path of signal transmission relation；
Step 5-4: according to step 5-1～5-3, divide in conjunction with FPGA resource internal logic unit and signal transmssion line control bit
Cloth, obtains the circuit signal transmission relation structure being made up of inside circuit node resource structures such as Slice, IOB and Block RAM
Build.
(3 phase IIIs: distributed signal topological relation builds
Step 6: according to step 4 to step 5 for XDL net meter file information analysis, builds between circuit node to circuit
The discrete circuitry signal of intra-node propagates topological relation, it is achieved Circuits System is between difference configuration resource type and configures
Temporal and logic relation within resource maps；Meanwhile, configuration control signal transmission configuration position within resource is directly and FPGA is mono-
Particle-sensitive position is associated, and can truly describe single-particle soft error transmitting procedure in circuit signal.
Step 6-1: based on step 4, XDL net meter file is resolved, to G (V1, E) and carry out forward signal between circuit node
Transmission topological relation sequence, obtains signal transmission topological relation between the circuit node of FPGA function module.Company between circuit node
Connecing relational representation is: the output port YQ of circuit node AND0/ex_value is current demand signal outfan, and cascades according to forward direction
It is separately input to F4 and the G2 port of circuit node NOR6/ex_value；
Step 6-2: resolve XDL net meter file based on step 5, maps the configuration resource of circuit node, obtains internal
Circuit signal transmission topological relation, obtains the signal transmission topological relation figure of sequential logical circuit in circuit node.
Step 6-3: according to step 6-1 and step 6-2, it is possible to obtain distributed signal and propagate topological relation, and it is entered
The inside and outside cascade of row, thus obtain the signal transmission topological relation of whole circuit function module or system.
Beneficial effect
(1) present invention is XDL netlist literary composition after FPGA engineering is comprehensively mapped by ISE instrument based on Xilinx company
Part, proposes a kind of distributed signal topological relation construction method propagated for single-particle soft error failure and analyze, by this net
The signal cascade information that in table, between circuit node and circuit node inside is contained carries out discrete circuitry interconnecting relation
Information analysis, thus obtaining in Circuits System is being that the sequential mainly mapping resource construction is patrolled with Slice, Block RAM, IOB
Collect circuit signal and propagate topological relation.
(2) method of the present invention highlights signal and propagates the relation of topology and device underlying resource architecture combined, base simultaneously
In XDL net meter file, with circuit signal, device single-particle inversion sensitivity position is propagated topological relation to be associated, thus combine simple grain
The working mechanism of sub-effect symbolizes circuit signal communication process in systems, and then follow-up can be used for promotes Circuits System
Single-particle soft error fail-safe analysis precision, instructs system single-particle soft error protection Design.
(3) method of the present invention completes the discrete circuitry signal between circuit node and within circuit node and propagates topology
Relation builds, thus realizes coupling and relation conversion between sequential logical circuit and the different resource type of complexity, obtains electricity
The signal of road system propagates topological relation.
(4) this method from single-particle inversion to Programmable Logic Device sensitivity, by by the netlist after comprehensive
And the circuit resource mapping relations of feedback, resolve with circuit node cascade sweep forward and configuration information coupling rule resolves netlist
Information, the signal logic building particular electrical circuit hardware resource configuration relation connects topological relation, is adapted to assist in lifting single-particle soft
Mistake, in systems reliability analysis precision, instructs systematic protection to design.
(5) present invention is based on XDL net meter file, it is proposed that a kind of sequential logical circuit letter being combined with device bottom architecture
Number transmission the distributed construction method of topological relation, can be used for lifting system single-particle soft error emulation testing fail-safe analysis.
(6) control bit configuration information based on the single-particle sensitivity position coupling rule of the present invention, completes to provide hardware configuration
The internal circuit signal transmission topological relation in source builds.
(7) cascade sweep forward analytic method between the circuit node of the present invention, complete between different hardware configurations resource type
Circuit signal transmission topological relation coupling.
(8) the method design object of the present invention is for SRAM type FPGA and the PLD of other analog structure,
Method possesses certain universality.
(9) circuit node under the method for the present invention builds based on hardware resource in XDL netlist information and corresponding signal
Between cascaded message, it is proposed that to the cascade sweep forward analytic method of signal cascade information between circuit node, in constructing system electricity
Oriented propagation topological relation between circuit node, completes the circuit signal between dissimilar hardware resource and propagates relation analysis；
Meanwhile, the circuit reflected according to XDL net meter file connects and controls configuration bit information association, and the method for the present invention proposes to join
Confidence breath coupling rule, resolves and builds the circuit node defeated path of internal signal transmission relation under resource maps, complete spy
Determine the circuit signal under the hardware resource of type and propagate relation analysis.
Accompanying drawing explanation
Fig. 1 is the method flow schematic diagram of the present invention；
Fig. 2 is the composition schematic diagram of the format code section of functional module；
Fig. 3 is the XDL net meter file of Virtex 4FPGA in embodiment；
Fig. 4 is circuit node cascade sweep forward analytic method flow chart in embodiment；
Fig. 5 is circuit node oriented chain list structure figure in embodiment；
Fig. 6 is that in embodiment, XDL net meter file circuit node resource information calls structure chart；
Fig. 7 is Virtex-4Slice resource internal logic unit and signal transmssion line control bit scattergram in embodiment；
Fig. 8 is the forward direction circuit transmission topological relation figure of circuit node in embodiment；
Fig. 9 is forward direction circuit diagram based on Slice resource circuit joint structure in embodiment；
Figure 10 is circuit node cnt<0 in embodiment>XDL net meter file control configuration bit hum pattern；
Figure 11 is circuit node cnt<0>internal signal propagation pathway figure in embodiment；
Figure 12 (a) is the VHDL design code figure of frequency dividing circuit in embodiment；
Figure 12 (b) is XDL net meter file circuit link information figure in embodiment；
Figure 13 is the forward direction circuit node topological relation figure of frequency dividing circuit in embodiment.
Detailed description of the invention
The invention will be further described with embodiment below in conjunction with the accompanying drawings.
Embodiment
The framework of whole method forms as it is shown in figure 1, be broadly divided into three phases, is respectively as follows:
(1) first stage: design prepares
According to user to signal propagate topological relation range of application design requirement, can to VHDL Engineering Documents according to
The vhd functional module of system top level functional module and other level divides, thus completes the input of functional module, outfan message
Number extract, and generate the XDL net meter file after each functional module comprehensive maps.
Step 1: representation function block code section, functional module is according to such as three structure part compositions of Fig. 2.
Step 2: import VHDL Engineering Documents, divides relation according to engineering level in ISE instrument, obtains respectively
Top layer and other each level functional module and corresponding code segment.
Step 2-1: input VHDL Engineering Documents, by ISE instrument identification each level functional module；
Step 2-2: according to the format code partition functionality module of Fig. 2, the functional module code after can dividing successively is protected
Being stored in the new vhd file of correspondence, new vhd file is named with entity (entity) name in functional module code segment, the most newly-generated
The functional module that vhd file is former FPGA engineering, the functional module name of the entitled correspondence of file of vhd file；
Step 2-3: according to the functional module generated, obtain the input and output letter of corresponding function module with port interface definition
Number port name.
Step 3: signal is propagated the design requirement of topological relation range of application according to user, selects corresponding function mould
Block, completes comprehensively to map in ISE instrument, firstly generates ncd file, and the ncd2xdl order calling ISE subsequently generates XDL net
List file.
(2) process two: net meter file resolves
As shown in Figure 4, step 4: complete to cascade sweep forward between circuit node and resolve, i.e. name with the input signal of module
Circuit node start, corresponding XDL netlist information, obtain input and output signal cascade connection between circuit node successively, directly
To the output signal name node of module, it is achieved under dissimilar configuration resource, the signal between circuit node propagates relation
Analysis.Wherein, circuit node represents the information in netlist with " inst " keyword definition, represent called FPGA Slice,
The circuit structure that Block RAM or IOB resource are formed.This annexation is follow-up can be used for analyzing signal because of single-particle soft
Mistake, the soft error error rate of circuit node calculates.
Step 4-1: be defined as G (V by the oriented logical circuitry of XDL file build module1, E), Fig. 3 is typical XDL
File, in its netlist, " inst " circuit node is V1Representing the end points in directed graph, " net " contains electricity in logical circuitry
Oriented signal transmission link information between circuit node, is stored in E；
Step 4-2: based on comprising the configuration bit information of circuit connecting relation in circuit node, define be likely to occur list
The node set of particle effect is V1, and be circuit node keyword to search " inst ", and with the alphabetical information after " inst "
Call the roll as circuit section, store and obtain traversal set V1{ni, all circuit node information in 1≤i≤N}, niFor i-th
Circuit section is called the roll, and N is V1All circuit node numbers that traversal obtains.
Step 4-3: for i-th circuit node, utilizes cascade sweep forward analytic method to find current circuit section to call the roll
For niThe all nodes that can reach in circuit, it is achieved process is as follows:
Step 4-3-1: " inst " keyword in search XDL net meter file, and it is defined as i-th with alphabetical information thereafter
The node name n of circuit nodei, 1≤i≤N, by niInformation is stored in V1；
Step 4-3-2: search for the field information initial with keyword " net " in netlist, as it is shown on figure 3, Fig. 3 lists
In XDL net meter file, the circuit node as a example by the entitled AND0/ex_value of circuit node inputs and defeated with other circuit node
Go out signal annexation, display in the information that " net " is start field, the current output circuit node name wherein comprised and under
One-level cascades input circuit node name, and corresponding circuits node exports and input signal name, the information row built according to such as Fig. 5
Table storage circuit node propagates topological relation.N in figurei/The circuit section roll-call n of outpin indication circuit node iiAnd output signal
outpin；XX and YY represents that subsequent cascaded oriented name circuit section is called the roll respectively, aa and aa` then distinguishes the input of related circuit node
The most above-mentioned with the physical meaning that output signal name, Yy, Bb and Bb` represent identical；K and t then represent current circuit node under
The fanout of one-level cascade circuit output signal node；O/inpin representation module output circuit node name O and input signal
inpin；
Step 4-3-3: resolve circuit node information according to the chain list structure figure that Fig. 5 builds, if current circuit section
The most corresponding next cascade circuit node input signal unique of some i output signal, then it represents that the output of circuit node i signal is singly fanned out to
The circuit node of next stage cascade input signal, jumps to step 4-3-4 and continues search for circuit node；If current circuit node
The output of i output signal is fanned out to the circuit node of multiple next stage cascade input signal more, jumps to step 4-3-5 and continues search for
Circuit node；
Step 4-3-4: for circuit node output signal list fan-out situation, by fixed next stage cascade circuit node
Circuit node associated by Ming is defined as i+1 (i < i+1≤N), and circuit node information is stored in V1, and circuit node is oriented
Signal transmission information is also saved in E, until it is that O/inpin terminates that circuit node searches information, and jump procedure 4-4；Otherwise,
Repeat step 4-3-2～step 4-3-3；
Step 4-3-5: for circuit node output signal many fan-outs situation, set up multi-path signal respectively according to fanout
Transmission line, simultaneously according to difference transmission line search subsequent conditioning circuit node, saves fixed current next stage cascade circuit
Circuit node associated by roll-call re-defines for i+1 (i < i+1≤N), circuit node information will be stored in V1, different fan-outs
Circuit node oriented signal transmission information is also saved in E.
Step 5: formulate configuration information coupling rule, resolves netlist circuit node internal signal transmission information, i.e. according to each
Circuit node internal structure calls the different resource of Slice, Block RAM, IOB, and the key under circuit node in netlist
Contained by word " cfg ", the configuration bit information of content is mated, it is achieved the signal under certain types of circuit node configuration resource
Propagate relation analysis.The follow-up circuit node internal signal that can be used for of this transmission relation, because of single-particle soft error, carries out circuit node
The analytical calculation of soft error error rate.
Step 5-1: coupling rule 1, circuit node maps resource information coupling.Resolve " inst " in XDL netlist and comprise letter
Breath, the position that its corresponding circuits node name, configuration resource and resource are placed in the devices.As shown in Figure 6, Fig. 6 shows respectively
With the circuit node configuration resource map information of clk and clk_out name in XLD netlist, wherein shade shows circuit node
The IOB resource of clk and correspondence, different circuit node may corresponding other such as Slice, Block RAM resource；
Step 5-2: coupling rule 2, logic circuit unit signal-line choosing transmission information matches.Based on step 5-1, at electricity
Circuit node inner search is with the configuration bit information that " cfg " is that keyword comprises, and this information is that circuit node is in correspondence mappings resource
The transmission of lower control each circuit logic unit input and output signal selects；
Step 5-3: coupling rule 3, circuit signal transmission controls configuration bit and resolves coupling.Based on step 5-2, search by field
Rope comprises " * *:: * * " sign bit information, and before ":: " symbol, the logical block name of information indication circuit, is equal to Xilinx
To logic circuit unit name nominating rule in FPGA device internal resource；After ":: " symbol, information represents circuit logic unit
Control bit selects, if being entered as " #OFF " expression not configure this circuit logic unit control bit, other assignment then counterlogic
The signal transmission of unit controls configuration bit, and it is according to user's manual that the circuit structure distribution that configuration bit is corresponding can refer to Fig. 7, Fig. 7
The V4 device Slice resource internal logic unit enumerated and show and signal transmssion line control bit scattergram.Under different resource,
Circuit node completes the structure in the defeated path of internal signal transmission relation under control bit configuration information coupling；
Step 5-4: according to step 5-1～5-3, divide in conjunction with FPGA resource internal logic unit and signal transmssion line control bit
Cloth, obtains the circuit signal transmission relation structure being made up of inside circuit node resource structures such as Slice, IOB and Block RAM
Build.
(3) process three: distributed signal topological relation builds
Step 6: according to step 4～5 for XDL net meter file information analysis, build between circuit node to circuit node
Internal discrete circuitry signal propagates topological relation, it is achieved Circuits System is between difference configuration resource type and configures resource
Internal temporal and logic relation maps；Meanwhile, configuration control signal transmission configuration position resource within is direct and FPGA single particle
Sensitive position is associated, and can truly describe single-particle soft error transmitting procedure in circuit signal.
Obtain G (V1, E) topological sorting, can construct module each circuit node forward direction circuit transmission topology close
System.
Step 6-1: based on step 4, net meter file is resolved, to G (V1, E) and carry out forward signal transmission between circuit node
Topological relation sorts, and obtains signal transmission topological relation between the circuit node of FPGA function module.As can according to Fig. 3 net meter file
To obtain result transmission relation as shown in Figure 8, Fig. 8 is the netlist information as a example by Fig. 3, the circuit node AND0/ex_ of acquisition
The forward direction circuit transmission topological relation figure of value and NOR6/ex_value, the annexation between circuit node is expressed as: circuit
The output port YQ of node AND0/ex_value is current demand signal outfan, and is separately input to circuit section according to forward direction cascade
F4 and the G2 port of some NOR6/ex_value；
Step 6-2: resolve net meter file based on step 5, maps the configuration resource of circuit node, obtains internal circuit
Signal transmission topological relation.As a example by the Slice resource circuit mapping relations of Fig. 7, Fig. 9 can be obtained by formalization, according to configuration
Information matches rule, Fig. 9 shows that circuit node is interior under clk sequential effect, from input signal to the transmission of output signal
Logical relation, the signal transmission topological relation figure of sequential logical circuit in shown circuit node.
Step 6-3: integrating step 6-1 and step 6-2, propagates topological relation to the distributed signal obtained and carries out inside and outside level
Connection, obtains the signal transmission topological relation of whole circuit function module or system.
It is designed as test case with 16 frequency dividing circuits, illustrates and XDL netlist level circuit signal is propagated relation construction method
Analyze and application.
1, the vhd design document of frequency dividing circuit is comprehensively mapped by ISE instrument, obtain XDL net meter file, such as figure
12 (a) and Figure 12 (b), Figure 12 (a) list the functional module VHDL design code of 16 frequency dividing circuits, and Figure 12 (b) is corresponding 16
Circuit node cnt<0 in the XDL netlist information of frequency dividing circuit>, cnt<1>, cnt<2>, cnt<3>between input and output letter
Number link information, respectively illustrates in frequency dividing circuit VHDL design code and netlist signal link information between circuit node, wherein
Clk and clk_out is denoted respectively as the input and output signal port name of frequency dividing circuit.
2, circuit is according to the circuit node netlist information after comprehensive, cascades sweep forward analytic method with circuit node, obtains
Taking the circuit node cascade connection topological diagram of forward direction circuit structure, as shown in figure 13, Figure 13 is with 16 frequency dividing circuit functional modules
As a example by, build the cascaded transmission topological relation figure of forward direction circuit between circuit node；
3, by circuit node cnt<0>as a example by, use configuration information coupling rule to circuit node cnt<0>configuration bit letter
Breath resolves, and Figure 10 is in the functional module of 16 frequency dividing circuits, enumerates in XDL netlist the netlist of<0>with circuit node as cnt
Controlling configuration bit information, after giving comprehensively, the XDL netlist of this circuit node controls configuration bit information.
4, mating rule based on configuration information, the configuration bit information resolving and obtaining is as follows:
(1) logical block DYMUX is configured to Y, i.e. DYMUX have selected and exports to subsequent conditioning circuit from Y-port by signal, enters
And exported to YQ by trigger；
(2) signal of the Y-port of logical block DYMUX is to be exported through look-up table LUT by input signal port G1～G4
It is supplied to, and LUT is configured to G2 and the G4 input port that A2@A4, i.e. A2 and A4 are corresponding LUT respectively；
(3) logical block YMUXUSED is configured to #OFF, represents port shutdown, so no signal is transferred to circuit node
Output port Y, YQ be then the unique output mouth of whole circuit node.
5, configuration bit information analysis result based on above-mentioned acquisition, builds the biography of circuit node cnt<0>internal circuit signal
Broadcasting path, as the black runic solid line in Figure 11 marks part, Figure 11 black runic solid line has marked the function of 16 frequency dividing circuits
In module, circuit node cnt<0>mate rule according to configuration information, obtain in Slice resource from signal G2 and G4 input
Internal circuit signal propagation path to signal YQ outfan.
6, other circuit node carries out circuit node internal circuit signal propagation path structure according to above-mentioned implementation successively
Build, and according to obtain circuit node between and circuit node internal signal inside and outside cascade connection, build 16 frequency dividing circuit systems
Distributed signal propagates topological relation figure.
Claims (10)
1. propagate the distributed signal topological relation construction method analyzed for single-particle soft error failure for one kind, it is characterised in that
Step includes:
(1) first stage, the preparatory stage is designed；
According to user, signal is propagated the design requirement of topological relation range of application, to VHDL Engineering Documents according to system merit
Energy Module Division, completes the input signal port of functional module, the extraction of output signal port, and generates the comprehensive of each functional module
XDL net meter file after mapping；
(2) second stage, net meter file resolves
Step 4: complete circuit node cascade sweep forward and resolve；
The method that search resolves is: start, according to the first rank with the circuit node that the input signal port name of functional module is named
Information in the XDL net meter file of Duan Shengcheng, obtains input and output signal cascade connection between circuit node successively, until merit
Till the node of the output signal port name name of energy module；
Step 5: formulate configuration information coupling rule, resolve netlist circuit node internal signal transmission information；
(3) phase III: distributed signal topological relation builds
Step 6: build and propagate topological relation to the discrete circuitry signal within circuit node between circuit node.
A kind of distributed signal topological relation propagating analysis for single-particle soft error failure the most according to claim 1
Construction method, it is characterised in that: the described first stage, the step of design preparatory stage is:
Step 1: defined function block code section；Functional module code segment includes quoting with keyword library for the storehouse of mark
Partly, with keyword entity for mark entity part and with keyword architecture be mark structure part；
Step 2: import the VHDL Engineering Documents of Circuits System, according to VHDL Engineering Documents layer in ISE instrument
Level divides relation, obtains each functional module and corresponding code segment and the input signal port name of corresponding function module and output letter
Number port name；
Step 3: signal is propagated the design requirement of topological relation range of application according to user, selects corresponding functional module,
Completing in ISE instrument comprehensively to map, firstly generate ncd file, the ncd2xdl order calling ISE subsequently generates XDL netlist literary composition
Part.
A kind of distributed signal topological relation propagating analysis for single-particle soft error failure the most according to claim 2
Construction method, it is characterised in that: the step of described step 2 is:
Step 2-1: the VHDL Engineering Documents of input circuit system, by the ISE each functional module of instrument identification；
Step 2-2: according to the form partition functionality module with functional module code segment, the functional module code after dividing successively
Section is stored in the new vhd file of correspondence, and new vhd file is named with physical name in functional module code segment, the most newly-generated vhd
File is the functional module of former FPGA engineering, the functional module name of the entitled correspondence of file of vhd file；
Step 2-3: according to the functional module generated, obtain the input signal port name of corresponding function module with port interface definition
With output signal port name.
A kind of distributed signal topological relation propagating analysis for single-particle soft error failure the most according to claim 1
Construction method, it is characterised in that: fixed with " inst " keyword during in described second stage, circuit node represents XDL net meter file
The information of justice, Slice, Block RAM or the IOB resource institute group being called FPGA with the information of " inst " keyword definition
The circuit structure become.
A kind of distributed signal topological relation propagating analysis for single-particle soft error failure the most according to claim 1
Construction method, it is characterised in that: the step completing circuit node cascade sweep forward parsing in described step 4 is:
Step 4-1: by the oriented logical circuitry of XDL net meter file conformation function module, oriented logical circuitry is defined as G
(V1, E), in XDL net meter file, " inst " circuit node is V1Representing the end points in directed graph, " net " contains logic circuit
In figure, the oriented signal between circuit node transmits link information, is stored in E；E represents the oriented transmission line of circuit node
Set；
Step 4-2: based on the circuit node defined with " inst " in XDL net meter file and the circuit connecting relation comprised
Configuration bit information, is defined as V by the node set of be likely to occur single particle effect1；For it may happen that single particle effect
Node with " inst " be circuit node keyword, using the alphabetical information after " inst " as circuit section call the roll, be stored in V1In,
Thus obtain traversal set V1{ni, 1≤i≤N}, wherein, niCalling the roll for i-th circuit section, N is V1All electricity that traversal obtains
Circuit node number；
Step 4-3: find the entitled n of current circuit nodeiThe all nodes that can reach in circuit；
Step 4-4: obtain G (V according to the effective transmission information in chain list structure figure1, E) topological sorting, can construct
The circuit node forward direction circuit transmission topological relation of functional module.
A kind of distributed signal topological relation propagating analysis for single-particle soft error failure the most according to claim 5
Construction method, it is characterised in that: the step of described step 4-3 is:
Step 4-3-1: " inst " keyword in search XDL net meter file, and it is defined as i-th circuit with alphabetical information thereafter
The node name n of nodei, 1≤i≤N, by niInformation is stored in V1；
Step 4-3-2: search for the field information initial with keyword " net " in XDL net meter file, wherein comprises current output
Circuit section is called the roll and next stage cascades input circuit node name, and corresponding circuits output signal node name and input signal name,
Build circuit node oriented chain list structure figure；
Step 4-3-3: resolve circuit node information according to the chain list structure figure that step 4-3-2 builds, if current circuit
The most corresponding next cascade circuit node input signal name unique of node i output signal, then it represents that the single fan of circuit node i signal output
Go out the circuit node to next stage cascade input signal, then jump to step 4-3-4 and continue search for circuit node；If currently electricity
Circuit node i output signal output fanout cascades the circuit node of input signal more than or equal to 2 to plural next stage, then
Jump to step 4-3-5 and continue search for circuit node；
Step 4-3-4: for circuit node output signal list fan-out situation, by fixed next stage cascade circuit node name institute
The circuit node of association is defined as i+1 cascade circuit node (i < i+1≤N), and circuit node information is stored in V1, and by electricity
Circuit node oriented signal transmission information is saved in E, until it is that O/inpin terminates that circuit node searches information, and jump procedure
4-4；Searching for less than information O/inpin else if, repeating step 4-3-2～step 4-3-3, until searching information O/
Inpin connects bundle, jumps to step 4-4；
Step 4-3-5: for circuit node output signal fanout situation, sets up multi-path signal transmission respectively according to fanout
Line, simultaneously according to difference transmission line search subsequent conditioning circuit node, by fixed current next stage cascade circuit node name
Associated circuit node re-defines for i+1 cascade circuit node (i < i+1≤N), and circuit section roll-call information is stored in
V1, the circuit node oriented signal transmission information of different fan-outs is saved in E, until it is O/ that circuit node searches information
Inpin terminates, jump procedure 4-4；Search for less than information O/inpin else if, repeat step 4-3-2～step 4-3-3, directly
Connect bundle to the information O/inpin of searching, jump to step 4-4.
A kind of distributed signal topological relation propagating analysis for single-particle soft error failure the most according to claim 6
Construction method, it is characterised in that: in step 4-3-2, list structure figure includes the circuit section roll-call n of circuit node ii, circuit
Output signal node name outpin, subsequent cascaded oriented circuit section roll-call XX, YY, Yy；Input signal name aa of XX circuit node,
Output signal name aa`, input signal name bb of YY circuit node, output signal name bb`, the input signal name of Yy circuit node
Bb, output signal name Bb`；Current circuit node fanout k, t to next stage cascade circuit output signal node；Module exports
Circuit section roll-call O and input signal name inpin.
A kind of distributed signal topological relation propagating analysis for single-particle soft error failure the most according to claim 1
Construction method, it is characterised in that: the step of step 5 is:
Step 5-1: coupling rule 1, circuit node maps resource information coupling, resolves " inst " in XDL net meter file and comprises letter
Breath, the position that its corresponding circuits node name, configuration resource and resource are placed in the devices；
Step 5-2: coupling rule 2, logic circuit unit signal-line choosing transmission information matches；Based on step 5-1, at circuit section
Point inner search is the configuration bit information that keyword comprises with " cfg ", and this information is that circuit node is controlled under correspondence mappings resource
The transmission making each circuit logic cell input signal and output signal selects；
Step 5-3: coupling rule 3, circuit signal transmission controls configuration bit and resolves coupling；Based on step 5-2, by field searches bag
Containing " * *:: * * " sign bit information, before ":: " symbol, the logical block name of information indication circuit, is equal to Xilinx FPGA device
To logic circuit unit name nominating rule in internal resource；After ":: " symbol, information represents the control bit choosing of circuit logic unit
Select, if being entered as " #OFF " expression not configure this circuit logic unit control bit, the letter of other assignment then counterlogic unit
Number transmission control configuration bit, under different resource, circuit node complete control bit configuration information coupling under internal signal transmission
The structure of relation path；
Step 5-4: according to step 5-1 to step 5-3, divide in conjunction with FPGA resource internal logic unit and signal transmssion line control bit
Cloth, obtains the circuit signal transmission relation being made up of Slice, IOB and Block RAM inside circuit node and builds.
A kind of distributed signal topological relation propagating analysis for single-particle soft error failure the most according to claim 1
Construction method, it is characterised in that: the step of step 6 is:
Step 6-1: based on step 4, XDL net meter file is resolved, to G (V1, E) carry out between circuit node forward signal transmission and open up
Flutter relation sequence, obtain signal transmission topological relation between the circuit node of FPGA function module；
Step 6-2: resolve XDL net meter file based on step 5, maps the configuration resource of circuit node, obtains internal circuit
Signal transmission topological relation, obtains the signal transmission topological relation figure of sequential logical circuit in circuit node；
Step 6-3: according to step 6-1 and step 6-2, obtains distributed signal and propagates topological relation, and it is carried out inside and outside level
Connection, thus obtain the signal transmission topological relation of whole circuit.
A kind of distributed signal topology analyzed of propagating for single-particle soft error failure the most according to claim 1 is closed
It is construction method, it is characterised in that: in step 6-1, the annexation between circuit node is expressed as: circuit node AND0/ex_
The output port YQ of value is current demand signal outfan, and is separately input to circuit node NOR6/ex_ according to forward direction cascade
F4 and the G2 port of value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610710113.XA CN106326553B (en) | 2016-08-23 | 2016-08-23 | A kind of distributed signal topological relation construction method for propagating analysis for single-particle soft error failure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610710113.XA CN106326553B (en) | 2016-08-23 | 2016-08-23 | A kind of distributed signal topological relation construction method for propagating analysis for single-particle soft error failure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106326553A true CN106326553A (en) | 2017-01-11 |
| CN106326553B CN106326553B (en) | 2019-09-06 |
Family
ID=57742479
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610710113.XA Active CN106326553B (en) | 2016-08-23 | 2016-08-23 | A kind of distributed signal topological relation construction method for propagating analysis for single-particle soft error failure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106326553B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111221670A (en) * | 2019-10-21 | 2020-06-02 | 西安空间无线电技术研究所 | Single-particle soft error protection design method for relieving detection conflict |
| CN113848455A (en) * | 2021-09-24 | 2021-12-28 | 成都华微电子科技有限公司 | Delay testing method for internal interconnection line of FPGA (field programmable Gate array) |
| CN115859886A (en) * | 2023-02-16 | 2023-03-28 | 山东启芯软件科技有限公司 | High-efficiency low-coupling design splitting method based on multi-fanout logic |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102646143A (en) * | 2011-11-30 | 2012-08-22 | 清华大学 | Conductance matrix construction method and system in simulation of on-chip power supply network |
| CN104215893A (en) * | 2014-08-28 | 2014-12-17 | 上海电力学院 | Circuit reliability evaluating method based on signal probability |
-
2016
- 2016-08-23 CN CN201610710113.XA patent/CN106326553B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102646143A (en) * | 2011-11-30 | 2012-08-22 | 清华大学 | Conductance matrix construction method and system in simulation of on-chip power supply network |
| CN104215893A (en) * | 2014-08-28 | 2014-12-17 | 上海电力学院 | Circuit reliability evaluating method based on signal probability |
Non-Patent Citations (2)
| Title |
|---|
| 梁华国 等: "考虑单粒子多瞬态故障的数字电路失效概率评估", 《计算机辅助设计与图形学学报》 * |
| 王忠明: "SRAM型FPGA的单粒子效应评估技术研究", 《中国博士学位论文全文数据库 信息科技辑》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111221670A (en) * | 2019-10-21 | 2020-06-02 | 西安空间无线电技术研究所 | Single-particle soft error protection design method for relieving detection conflict |
| CN111221670B (en) * | 2019-10-21 | 2023-03-28 | 西安空间无线电技术研究所 | Single-particle soft error protection design method for relieving detection conflict |
| CN113848455A (en) * | 2021-09-24 | 2021-12-28 | 成都华微电子科技有限公司 | Delay testing method for internal interconnection line of FPGA (field programmable Gate array) |
| CN115859886A (en) * | 2023-02-16 | 2023-03-28 | 山东启芯软件科技有限公司 | High-efficiency low-coupling design splitting method based on multi-fanout logic |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106326553B (en) | 2019-09-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH05143674A (en) | Automatic logic-model forming method based on circuit graphic database | |
| CN106326553A (en) | Distributed signal topological relation construction method used for analyzing single-particle and soft-error fault propagation | |
| Zhao et al. | An automated topology synthesis framework for analog integrated circuits | |
| CN102033990A (en) | Method for producing excitation waveform during logic parameter extraction of combinational logic circuit | |
| US7363599B1 (en) | Method and system for matching a hierarchical identifier | |
| CN110823226B (en) | Unmanned aerial vehicle intelligent route planning test method based on metamorphic test technology | |
| CN104123407A (en) | Automatic testability model building method based on circuit simulation | |
| US20110010157A1 (en) | Process for automatic creation of wiring simulation | |
| CN109492127A (en) | Data processing method, device, medium and calculating equipment | |
| CN104765902A (en) | Characterizing cell using input waveform geneartion considering different circuit topoloiges | |
| WO1999009497A1 (en) | Method of extracting timing characteristics of transistor circuits, storage medium storing timing characteristic library, lsi designing method, and gate extraction method | |
| US8266573B2 (en) | Method and system for test point insertion | |
| CN104486222B (en) | Small time delay defect test critical path system of selection based on ant colony optimization algorithm | |
| CN110032792B (en) | Superconducting digital circuit design method | |
| US20020186247A1 (en) | Method of displaying delay | |
| US7249329B1 (en) | Technology mapping techniques for incomplete lookup tables | |
| US20160224700A1 (en) | Method for Determining the Sizing of the Transistors of an Analog Circuit | |
| CN114186523A (en) | Digital-analog hybrid design method and process migration method based on asynchronous circuit | |
| Spichkova | Formalisation and analysis of component dependencies | |
| CN107340466A (en) | Analog signal detection system and analog signal detection method | |
| Lawsunnee et al. | Signal persistence checking of asynchronous system implementation using SPIN | |
| Lukyanova | Component modeling: on connections of detailed Petri model and component model of parallel distributed system | |
| Capilayan et al. | Analysis on HSpice performance trade-off versus simulation time | |
| US7979818B1 (en) | Packet processing validation | |
| Ismail | Efficient model order reduction via multi-node moment matching |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |