CN106326153A - Interface detection circuit - Google Patents
Interface detection circuit Download PDFInfo
- Publication number
- CN106326153A CN106326153A CN201510365650.0A CN201510365650A CN106326153A CN 106326153 A CN106326153 A CN 106326153A CN 201510365650 A CN201510365650 A CN 201510365650A CN 106326153 A CN106326153 A CN 106326153A
- Authority
- CN
- China
- Prior art keywords
- detecting
- signal
- card
- add
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3804—Memory card connected to a computer port directly or by means of a reader/writer
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Small-Scale Networks (AREA)
- Details Of Connecting Devices For Male And Female Coupling (AREA)
Abstract
The invention discloses an interface detection circuit. The interface detection circuit comprises a control circuit and a management chip connected with the control circuit, wherein the control circuit is connected with a connector; the connector is connected with an external card in an inserted manner; the control circuit is used for outputting a first control signal when the connector is not electrically connected with the external card in the inserted manner, and is used for outputting a second control signal when the connector is electrically connected with the external card in the inserted manner; and the management chip is used for outputting a first output signal according to the first control signal, and is used for outputting a second output signal according to the second control signal.
Description
Technical field
The present invention relates to a kind of interface circuit for detecting.
Background technology
In the motherboard design of computer, it usually needs use add-on card to meet the demand of user.Some add-on card is that the plug by cable is connected on the adapter of mainboard.During use, the plug of some cable can not well be inserted on the adapter of mainboard, so that add-on card can not electrically be plugged on adapter normally to use.A kind of the circuit that add-on card is the most electrically plugged on the adapter of mainboard can be detected therefore, it is necessary to design.
Summary of the invention
In view of the foregoing, it is necessary to a kind of power supply circuits that can interpolate that add-on card is the most electrically plugged on the adapter of mainboard are provided.
A kind of interface circuit for detecting, the managing chip of described control circuit is connected including a control circuit and one, described control circuit is used for connecting a connector, described adapter is used for grafting one add-on card, described control circuit for exporting one first control signal and for exporting one second control signal when add-on card described in the electrical grafting of described adapter when add-on card described in described adapter does not has electrical grafting, and described managing chip is for according to described first control signal output one first output signal and for according to described second control signal output one second output signal.
Preferably, described adapter includes one first detecting pin and one second detecting pin, described first detecting pin is used for exporting described first detection signal, described second detecting pin is used for exporting described second detection signal, described first detection signal has different level values when described first detects add-on card described in pin the most electrically grafting, and described second detection signal has different level values when described second detects add-on card described in pin the most electrically grafting.
Preferably, described first detecting pin and described second detecting pin lay respectively at the two ends that described adapter is relative.
Preferably, when described first detecting pin is not electrically connected with described add-on card, described first detection signal is high level signal, and when described first detects the pin described add-on card of electric connection, described first detection signal is low level signal.
Preferably, when described second detecting pin is not electrically connected with described add-on card, described second detection signal is high level signal, and when described second detects the pin described add-on card of electric connection, described second detection signal is low high level signal.
Preferably, described managing chip is for exporting described second output signal at described first detection signal and described second detection signal when being low level.
Preferably, described second output signal is high level signal.
Preferably, described control circuit includes that a logic circuit, described logic circuit are one or door, and the first detecting pin of described adapter connects a described or first input end of door, second detecting pin connects described or one second input of door, and described or door a outfan connects described managing chip.
Preferably, described first output signal is low level signal.
Preferably, described first control signal is high level signal.
Compared with prior art, in above-mentioned interface circuit for detecting, when add-on card described in described adapter does not has electrical grafting, described control circuit exports described first control signal, thus described managing chip exports described first output signal；When add-on card described in the electrical grafting of described adapter, described control circuit exports described second control signal, thus described managing chip exports described second output signal.During use, the first output signal that can export according to described managing chip or the second output signal judge add-on card described in the most electrically grafting of described adapter.
Accompanying drawing explanation
Fig. 1 is a functional block diagram of a better embodiment of interface circuit for detecting of the present invention.
Fig. 2 is a circuit connection diagram of a better embodiment of interface circuit for detecting of the present invention.
Main element symbol description
| Motherboard power supply | 10 |
| First power supply | 11 |
| Second source | 13 |
| Control circuit | 20 |
| Logic circuit | 21 |
| Managing chip | 30 |
| Sense terminal | 31 |
| Adapter | 40 |
| First detecting pin | 41 |
| Second detecting pin | 43 |
| Detecting system | 50 |
| Add-on card | 60 |
Following detailed description of the invention will further illustrate the present invention in conjunction with above-mentioned accompanying drawing.
Detailed description of the invention
Referring to Fig. 1, a better embodiment of interface circuit for detecting of the present invention includes that a motherboard power supply 10, connects control circuit 20 and the managing chip 30 of a described control circuit 20 of connection of described motherboard power supply 10.Described control circuit 20 is used for connecting a connector 40.Described motherboard power supply 10 is for powering to described control circuit 20.
Described managing chip 30 is for connecting a detecting system 50.Described adapter 40 is for grafting one add-on card 60.Described adapter 40 is additionally operable to export one first detection signal and one second detection signal.Described control circuit 20 is for exporting one first control signal or one second control signal according to described first detection signal and the level value of described second detection signal.Described managing chip 30 exports one first output signal for the first control signal according to the output of described control circuit 20, and exports one second output signal for the second control signal according to the output of described control circuit 20.Described detecting system 50 judges add-on card 60 described in described adapter 40 the most electrically grafting for the first output signal according to the output of described managing chip 30 or the second output signal.
Referring to Fig. 2, described motherboard power supply 10 includes one first power supply 11 and two second sources 13.Described first power supply 11 and each second source 13 are used to provide the voltage of a 3V.
Described control circuit 20 includes logic circuit 21, a 1 first resistance R1, an one second resistance R2 and electric capacity C1.Described logic circuit 21 is one or door, and includes first input end 1,1 second input 2, power end 5, outfan 4 and an earth terminal 3.
Described managing chip 30 includes a sense terminal 31.In one embodiment, described managing chip 30 is a South Bridge chip, and described sense terminal 31 is a universal input/output (General Purpose
Input Output, GPIO) end.
Described adapter 40 includes one first detecting pin 41 and one second detecting pin 43.Described first detecting pin 41 and described second detecting pin 43 lay respectively at the two ends that described adapter 40 is relative.Described first detecting pin 41 is used for exporting described first detection signal, and described second detecting pin 43 is used for exporting described second detection signal.Described first detection signal has different level values when described first detects add-on card 60 described in pin 41 the most electrically grafting, and described second detection signal has different level values when described second detects add-on card 60 described in pin 43 the most electrically grafting.In one embodiment, when described first detects add-on card 60 described in the not electrical grafting of pin 41, described first detection signal is high level signal, is otherwise low level signal；When described second detects add-on card 60 described in the not electrical grafting of pin 43, described second detection signal is high level signal, is otherwise low level signal.
Wherein a second source 13 connects one end of described first resistance R1.The other end of described first resistance R1 connects the first detecting pin 41 of described adapter 40 and connects the first input end 1 of described logic circuit 21.Another second source 13 connects one end of described second resistance R2.The other end of described second resistance R2 connects the second detecting pin 43 of described adapter 40 and connects the second input 2 of described logic circuit 21.The power end 5 of described logic circuit 21 connects described first power supply 11 and by described electric capacity C1 ground connection.The outfan 4 of described logic circuit 21 connects the sense terminal 31 of described managing chip 30.Earth terminal 3 ground connection of described logic circuit 21.
During detecting, when described first detection signal is high level signal and described second detection signal is high level signal, described logic circuit 21 exports the first control signal of a high level, described managing chip 30 exports low level first output signal after receiving the first control signal of described high level, and described detecting system 50 judges described adapter 40 electrical add-on card 60 described in grafting after receiving described low level first output signal.When described first detection signal is high level signal and described second detection signal is low level signal, described logic circuit 21 exports the first control signal of described high level, described managing chip 30 exports described low level first output signal after receiving the first control signal of described high level, and described detecting system 50 judges described adapter 40 electrical add-on card 60 described in grafting after receiving described low level first output signal.When described first detection signal is low level signal and described second detection signal is high level signal, described logic circuit 21 exports the first control signal of described high level, described managing chip 30 exports described low level first output signal after receiving the first control signal of described high level, and described detecting system 50 judges described adapter 40 electrical add-on card 60 described in grafting after receiving described low level first output signal.When described first detection signal is low level signal and described second detection signal is low level signal, described logic circuit 21 exports low level second control signal, described managing chip 30 receives the second output signal exporting a high level after after described low level second control signal, and described detecting system 50 judges add-on card 60 described in the described electrical grafting of adapter 40 after receiving the second output signal of described high level.
In above-mentioned interface circuit for detecting, when add-on card 60 described in the described electrical grafting of adapter 40, described adapter 40 exports described low level first detection signal and described low level second detection signal, thus described control circuit 20 exports described low level second control signal, make described managing chip 30 export the second output signal of described high level, and then described detecting system 50 judges add-on card 60 described in the described electrical grafting of adapter 40；When described add-on card 60 is the most electrically plugged to described adapter 40 grafting, described control circuit 20 exports the first control signal of high level, thus described managing chip 30 exports described low level first output signal, and then described detecting system 50 judges described adapter 40 electrical add-on card 60 described in grafting, judge add-on card 60 described in the described the most electrical grafting of adapter 40 to facilitate.
Make other be altered or modified accordingly it will be apparent to those skilled in the art that being actually needed of producing can be combined according to the scheme of the invention of the present invention and inventive concept, and these change and adjust and all should belong to scope disclosed in this invention.
Claims (10)
1. an interface circuit for detecting, it is characterized in that: described interface circuit for detecting includes that a control circuit and connects the managing chip of described control circuit, described control circuit is used for connecting a connector, described adapter is used for grafting one add-on card, described control circuit for exporting one first control signal and for exporting one second control signal when add-on card described in the electrical grafting of described adapter when add-on card described in described adapter does not has electrical grafting, described managing chip is for according to described first control signal output one first output signal and for according to described second control signal output one second output signal.
2. interface circuit for detecting as claimed in claim 1, it is characterized in that: described adapter includes one first detecting pin and one second detecting pin, described first detecting pin is for output one first detection signal, described second detecting pin is for output one second detection signal, described first detection signal has different level values when described first detects add-on card described in pin the most electrically grafting, and described second detection signal has different level values when described second detects add-on card described in pin the most electrically grafting.
3. interface circuit for detecting as claimed in claim 2, it is characterised in that: described first detecting pin and described second detecting pin lay respectively at the two ends that described adapter is relative.
4. interface circuit for detecting as claimed in claim 2, it is characterized in that: when described first detecting pin is not electrically connected with described add-on card, described first detection signal is high level signal, when described first detects the pin described add-on card of electric connection, described first detection signal is low level signal.
5. interface circuit for detecting as claimed in claim 4, it is characterized in that: when described second detecting pin is not electrically connected with described add-on card, described second detection signal is high level signal, when described second detects the pin described add-on card of electric connection, described second detection signal is low high level signal.
6. interface circuit for detecting as claimed in claim 5, it is characterised in that: described managing chip is for exporting described second output signal at described first detection signal and described second detection signal when being low level.
7. interface circuit for detecting as claimed in claim 6, it is characterised in that: described second output signal is high level signal.
8. interface circuit for detecting as claimed in claim 2, it is characterized in that: described control circuit includes a logic circuit, described logic circuit is one or door, first detecting pin of described adapter connects a described or first input end of door, second detecting pin connects described or one second input of door, and described or door a outfan connects described managing chip.
9. interface circuit for detecting as claimed in claim 1, it is characterised in that: described first output signal is low level signal.
10. interface circuit for detecting as claimed in claim 1, it is characterised in that: described first control signal is high level signal.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510365650.0A CN106326153A (en) | 2015-06-29 | 2015-06-29 | Interface detection circuit |
| TW104121567A TW201701167A (en) | 2015-06-29 | 2015-07-02 | Interface detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510365650.0A CN106326153A (en) | 2015-06-29 | 2015-06-29 | Interface detection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106326153A true CN106326153A (en) | 2017-01-11 |
Family
ID=57722440
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510365650.0A Pending CN106326153A (en) | 2015-06-29 | 2015-06-29 | Interface detection circuit |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN106326153A (en) |
| TW (1) | TW201701167A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108572935A (en) * | 2017-03-07 | 2018-09-25 | 鸿富锦精密工业(武汉)有限公司 | Usb control circuit |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101769977A (en) * | 2008-12-30 | 2010-07-07 | 鸿富锦精密工业（深圳）有限公司 | Connector detection system |
| CN101769976A (en) * | 2008-12-26 | 2010-07-07 | 鸿富锦精密工业（深圳）有限公司 | Connector detection system |
| CN104007353A (en) * | 2013-02-26 | 2014-08-27 | 鸿富锦精密工业(武汉)有限公司 | Interface detection circuit |
| CN104237716A (en) * | 2013-06-07 | 2014-12-24 | 鸿富锦精密工业（深圳）有限公司 | Serial connector detection system and method |
| CN104731679A (en) * | 2013-12-23 | 2015-06-24 | 鸿富锦精密工业（深圳）有限公司 | Connection card detection system |
-
2015
- 2015-06-29 CN CN201510365650.0A patent/CN106326153A/en active Pending
- 2015-07-02 TW TW104121567A patent/TW201701167A/en unknown
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101769976A (en) * | 2008-12-26 | 2010-07-07 | 鸿富锦精密工业（深圳）有限公司 | Connector detection system |
| CN101769977A (en) * | 2008-12-30 | 2010-07-07 | 鸿富锦精密工业（深圳）有限公司 | Connector detection system |
| CN104007353A (en) * | 2013-02-26 | 2014-08-27 | 鸿富锦精密工业(武汉)有限公司 | Interface detection circuit |
| CN104237716A (en) * | 2013-06-07 | 2014-12-24 | 鸿富锦精密工业（深圳）有限公司 | Serial connector detection system and method |
| CN104731679A (en) * | 2013-12-23 | 2015-06-24 | 鸿富锦精密工业（深圳）有限公司 | Connection card detection system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108572935A (en) * | 2017-03-07 | 2018-09-25 | 鸿富锦精密工业(武汉)有限公司 | Usb control circuit |
| CN108572935B (en) * | 2017-03-07 | 2022-07-29 | 鸿富锦精密工业(武汉)有限公司 | USB interface control circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201701167A (en) | 2017-01-01 |
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| PB01 | Publication | ||
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| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20170111 |