CN106325600A

CN106325600A - Control method of electromagnetic and capacitive double-mode touch device

Info

Publication number: CN106325600A
Application number: CN201610724650.XA
Authority: CN
Inventors: 张家文
Original assignee: Shanghai Weishan Electronic Technology Co Ltd
Current assignee: Shanghai Weishan Electronic Technology Co Ltd
Priority date: 2016-08-25
Filing date: 2016-08-25
Publication date: 2017-01-11
Anticipated expiration: 2036-08-25
Also published as: CN106325600B

Abstract

The invention provides a control method of an electromagnetic and capacitive double-mode touch device. The control method comprises: acquiring an electromagnetic signal and a capacitive signal, which are generated by triggering a screen, by a signal control module; receiving the signals, which are sent by the signal control module, by a control assembly module, and controlling cooperated operation of a capacitive control module and an electromagnetic control module through a manner of a general input/output port; setting a C to L port to low frequency by the control assembly module according to interval time and a pre-set time threshold value; if judging that the C to L port is the low frequency, setting the C to L port to be the low frequency and the electromagnetic control module being at a working state; meanwhile, detecting input of the electromagnetic signal; if judging that the C to L port is high frequency, the capacitive control module being at the working state, and detecting the input of the capacitive signal. By adopting the control method of the electromagnetic and capacitive double-mode touch device, the problem of a current electromagnetic and capacitive double-mode touch device that two types of data are interfered with each other when electromagnetic data and capacitive data are input so that errors are generated when the data is received by a touch screen is solved.

Description

Control method of electromagnetic-capacitor dual-mode touch device

Technical Field

The invention relates to the technical field of wireless communication and touch display, in particular to a control method of an electromagnetic-capacitor dual-mode touch device.

Background

With the rapid development of information technology, portable mobile electronic devices are increasingly relevant to the lives of people. The portable mobile electronic device may receive an input from a user and implement a function desired by the user according to the input.

The electromagnetic capacitance dual-mode touch device is input equipment which can send electromagnetic signals input by a user through an electromagnetic screen and can also send capacitance signals input by the user through a capacitance screen. Wherein the electromagnetic induction technology simulates the writing track or other operations of a pen to input electromagnetic signals. When an electromagnetic signal and a capacitance signal are input, the two signals can interfere with each other, so that the problem of error of the signals received by the capacitance electromagnetic touch screen body is caused.

Therefore, how to provide a control scheme for an electromagnetic capacitive dual-mode touch device to control the input of an electromagnetic signal and a capacitive signal, so that the electromagnetic capacitive touch screen can stably and accurately receive signals is a problem to be solved at present.

Disclosure of Invention

The technical problem to be solved by the present invention is to provide a method for controlling an electromagnetic capacitive dual-mode touch device, so as to solve the problem that in the current electromagnetic capacitive dual-mode touch device, when electromagnetic data and capacitive data are input, the two data interfere with each other, which causes an error in the data received by an electromagnetic capacitive touch screen body.

In order to solve the above problem, the present invention provides a method for controlling an electromagnetic-capacitive dual-mode touch device, including:

a signal control module in the electromagnetic capacitance dual-mode touch device acquires an electromagnetic signal and a capacitance signal generated after a screen is triggered;

a control assembly module in the electromagnetic capacitance dual-mode touch device receives a signal sent by a signal control module and controls the cooperative operation of the capacitance control module and an electromagnetic control module in a universal input/output port mode, wherein the universal input/output port comprises an L to C port and a C to L port;

the control assembly module sets the C to L port as a low electric frequency according to a preset time threshold value according to the interval time; if the C to L port is judged to be low electric frequency, the L to C port is set to be low electric frequency, meanwhile, the electromagnetic control module is in a working state, and the input of an electromagnetic signal is detected; and if the C to L port is judged to be in a high-frequency state, the capacitance control module is in a working state, and the input of a capacitance signal is detected.

Compared with the prior art, the electromagnetic capacitance dual-mode touch control device has the advantages that the electromagnetic scanning signals and the capacitance changing pump signals are processed in a time-sharing mode, the capacitance control module and the electromagnetic control module achieve a synchronization function in a universal input/output port mode, when no electromagnetic pen works around the inductor, the electromagnetic pen operates in a capacitance touch control mode, when the electromagnetic pen is close to the periphery of the inductor, the electromagnetic pen is switched to the electromagnetic pen touch control mode, and signals received by a screen body of the electromagnetic capacitance dual-mode touch control device reach a very stable state. The electromagnetic capacitance dual-mode touch device is simple and reasonable to control and easy to realize.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a flowchart of a control method of an electromagnetic capacitive dual-mode touch device according to the present invention;

FIG. 2 is a schematic structural diagram of a control assembly module according to the present invention;

3-1, 3-2, 3-3 and 3-4 are schematic structural views of the working detection module of the present invention;

FIG. 4 is a schematic structural diagram of a capacitance control module according to the present invention;

FIG. 5 is a schematic diagram of the structure of an electromagnetic control module according to the present invention;

fig. 6-1, 6-2, 6-3 and 6-4 are schematic structural diagrams of a signal control module in the invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The control process of the electromagnetic capacitance dual-mode touch device comprises the following steps: the electromagnetic scanning signal and the capacitance chargingpump signal are processed in a time-sharing mode, a synchronous function is realized between the capacitance control module and the electromagnetic control module in a GPIO (general purpose input/output port) port mode, when no electromagnetic pen works around the inductor, the electromagnetic control module operates in a capacitance touch mode, and when the electromagnetic pen is close to the periphery of the inductor, the electromagnetic control module is switched to the electromagnetic pen touch mode, so that the signals received by a screen body of the electromagnetic capacitance dual-mode touch device reach a very stable state. The electromagnetic capacitance dual-mode touch device is simple and reasonable to control and easy to realize.

As shown in fig. 1, the present invention provides a method for controlling an electromagnetic-capacitive dual-mode touch device, comprising the following steps:

110, a signal control module in the electromagnetic capacitance dual-mode touch device acquires an electromagnetic signal and a capacitance signal generated after a screen is triggered;

step 120, the control assembly module in the electromagnetic capacitance dual-mode touch device receives the signal sent by the signal control module, and controls the cooperative operation of the capacitance control module and the electromagnetic control module in a general input/output port mode, wherein the general input/output port comprises an L to C port and a C to L port;

the control assembly module comprises a micro control unit, a crystal oscillator unit and a plurality of capacitive reactance units, wherein after the capacitive reactance units are connected with the micro control unit, the capacitive reactance units are used for filtering the micro control unit, reducing input ripples, removing signals of interference chips and participating in oscillation and frequency stabilization operations.

The control assembly module includes: micro-control unit U7, resistor R47, resistor R65, crystal oscillator X1, capacitor C1, short-circuit point J1, test point TP1 and test point TP1, wherein the 1 st pin of micro-control unit U1 is connected with WER, 2 nd pin, 3 rd pin, 6 th pin, 7 th pin, 21 st pin and 22 st pin are connected with electromagnetic control module, the 4 th pin is connected with resistor R1, capacitor C1 and capacitor C1, the other ends of capacitors C1 and C1 are grounded, the other end of resistor R1 is connected with POWER supply 3.3V and test point 1, the first pin 16 th pin is connected with POWER supply control module, the first pin 16 th pin 16, the first pin is connected with POWER supply control module, the ground connection point J369, the first pin is connected with POWER supply control module, the POWER supply control module is connected with POWER supply control module 9, the second pin 16, the second pin is connected with POWER supply point J, The other end of the short-circuit point J3 is connected to the 3 rd pin of the connector CON2, the 11 th pin is connected to one end of the short-circuit point J4, the other end of the short-circuit point J4 is connected to the 4 th pin of the connector CON2, the 12 th pin is connected to the short-circuit point J5, the short-circuit point J5 is connected to the 6 th pin of the connector CON2, the 13 th pin is connected to the short-circuit point J5, the short-circuit point J6 is connected to the 7 th pin of the connector CON2, the 14 th pin is connected to the TP4 of the test and the 52 th pin of the capacitor IC, the 15 th pin is connected to the TP11 of the test and the 51 th pin of the capacitor IC, the 18 th pin is connected to ground, the 19 th pin is connected to the power supply 3.3V, the 20 th pin is connected to the 8 th pin of the connector CON2, the 23 rd, 24 th and 25 th pins are connected to the floating, one end of the J8 of the short-circuit point of the 26 th pin is connected to the short-circuit point, the other end of the 4 th pin 2 th, the 32 th pin and the 33 rd pin are suspended, the 34 th pin is connected with a test TP1, the 35 th pin is connected with a test TP8 and a 9 th pin of a connector CON2, the 36 th pin is connected with a 3 rd pin of a crystal oscillator X1, the 37 th pin is connected with a 1 st pin of the crystal oscillator X1, one end of a capacitor C45, one end of a capacitor C46 and the other ends of capacitors C46 and C45 are grounded, the 38 th pin is connected with the ground, the 39 th pin is connected with a power supply 3.3VA, the 40 th, 41 th, 42 th, 43 th and 44 th pins are suspended, and the 45 th, 46 th, 47 th and 48 th pins are connected with the ground

Specifically, as shown in fig. 2, pin 1 of the mcu U7 is connected to one end of the MOS transistor G, pin 2 is connected to pin 52 of the inductor ICU10, pin 3 is connected to pin 51 of the inductor IC U10, pin 4 is connected to the resistor R47 (the value ranges from 10R to 30R; the value 22R is used as a current limiting in the circuit), the capacitor C53 (the value ranges from 0.1UF to 1; the value 1UF acts as a filtering function of a power supply in the circuit), the capacitor C54 (the value ranges from 0.01UF to 0.1 UF; the value 0.01UF acts as a filtering function of a power supply in the circuit), the other ends of the capacitors C53 and C54 are grounded, the other end of the resistor R47 is connected to the power supply 3.3V and the test point TP6, pin 5 is connected to pin 14 of the operational amplifier U6, pin 6 is connected to pin 50 of the inductor IC U10, pin 7 is connected to pin 49 of the IC U463, pin 8 is grounded, the pin 9 is connected to the power supply 3.3V, one end of the pin 10 is connected to the short-short circuit, The other end of the short-circuit point J3 is connected with the 3 rd pin of the CON2, the 11 th pin is connected with one end of the resistor R22 and one end of the short-circuit point J4, the other end of the short-circuit point J4 is connected with the 4 th pin of the CON2, the 12 th pin is connected with the short-circuit point J5 and the short-circuit point J5 is connected with the 6 th pin of the CON2, the 13 th pin is connected with the 7 th pin of the short-circuit point J5 and the short-circuit point J6 are connected with the 7 th pin of the CON2, the 14 th pin is connected with the TP4 tested and the 52 th pin of the capacitor IC, the 15 th pin is connected with the TP11 tested and the 51 pin of the capacitor IC, the 16 th pin is connected with one end of the resistor R28, the 17 th pin is connected with the cathode of a diode, the 18 th pin is connected with the ground, the 19 th pin is connected with a power supply 3.3.3V, the 20 th pin is connected with the 8 th pin of the CON2, the 21 st pin is connected with the 8 th pin, the 48 th pin of the inductor IC 10 th pin is connected with the 21, The other end of the J7 of the short circuit point is connected with a pin 3 of CON2, a pin 28 is connected with a pin 4 of U1, a pin 29 is connected with a pin 3 of U1, a pin 30 is connected with ground, a pin 31 is connected with 3.3V of a power supply, pins 32 and 33 are suspended, a pin 34 is connected with a test TP1 (used for controlling an IC burning program), a pin 34 is connected with a test TP8 and a pin 9 of CON2, a pin 36 is connected with a pin 3 of a crystal oscillator (16 MHZ: providing the crystal oscillator frequency of an external high-speed clock 16MZH for the IC), a pin 37 is connected with a pin 1 of the crystal oscillator (16 MHZ: providing the crystal oscillator frequency of the external high-speed clock 16MZH for the IC), a capacitor C45 (22 pf is obtained according to the crystal oscillator capacitance charge, a capacitor C46 is involved in oscillation and a frequency stabilization (22 pf is obtained according to the crystal oscillator capacitance charge; a capacitor C46 and a pin 45 is connected with ground, a pin 38 is connected with a pin 3.39 VA 3, the 40 th, 41 th, 42 th, 43 th and 44 th pins are suspended, and the 45 th, 46 th, 47 th and 48 th pins are connected with the ground.

Step 130, the control assembly module sets the C to L port to be low electric frequency according to a preset time threshold value according to the interval time; if the C to L port is judged to be low electric frequency, the L to C port is set to be low electric frequency, meanwhile, the electromagnetic control module is in a working state, and the input of an electromagnetic signal is detected; and if the C to L port is judged to be in a high-frequency state, the capacitance control module is in a working state, and the input of a capacitance signal is detected.

The preset time threshold value can be 1ms to 3ms, the interval time can be 10ms to 30ms, and the setting of 3ms for the preset time threshold value and the setting of 30ms for the interval time are the optimal implementation modes, so that the power consumption control of the electromagnetic-capacitor dual-mode touch device can be reduced.

Further comprising: and the control assembly module judges whether the L to C port is in a low electric frequency state, the electromagnetic control module is in a working state, and the capacitance control module cannot start working until the L to C port is set to be in a high electric frequency state.

Through the process, when no electromagnetic pen works around the inductor, the electromagnetic pen operates in a capacitive touch mode, and when the electromagnetic pen is close to the periphery of the inductor, the system is switched to the electromagnetic pen touch mode, so that signals received by a screen body of the electromagnetic capacitive dual-mode touch device reach a very stable state.

The electromagnetic capacitance dual-mode touch device also comprises a work detection module, and the work detection module is connected with the control assembly module and the signal control module; the work detection module receives a control signal of the control assembly module and receives a signal sent by the signal control module;

the working detection module comprises a connector unit, a voltage stabilizing integrated circuit unit, an unstable voltage negative output voltage integrated circuit unit and a plurality of capacitive reactance units, wherein the capacitive reactance units respectively connected with the voltage boosting integrated circuit unit and the unstable voltage negative output voltage integrated circuit unit filter high and low frequency signals of the voltage boosting integrated circuit unit and reduce the operation of input ripples and noise.

The work detection module comprises a connector CON2, a voltage-stabilizing integrated circuit unit Q5, an unstable voltage negative output voltage integrated circuit unit U3, a resistor R7, a resistor R22, a resistor R21, a resistor R8, a resistor R9, a resistor R23, a resistor R1, a resistor R24, a capacitor C26, a capacitor C27, a capacitor C29, a capacitor C104, a capacitor C110, a capacitor C8, a capacitor C107, a capacitor C108, a capacitor C2, a capacitor C69, a capacitor C70, a capacitor C61, a capacitor C20, a capacitor C10, an inductor L4, an inductor L1 and a MOS tube Q1; wherein,

a first pin of the connector CON2 is connected to a VBUS5V power input port, a second pin is suspended, a third pin is connected to one end of the short-circuit point J3, a fourth pin is connected to one end of the short-circuit point J4, a fifth pin is grounded, one end of a sixth pin is connected to one end of a resistor R9 and the other end of the resistor R9 are connected to the power supply 3.3V, a seventh pin is connected to one end of a resistor R8, the other end of the resistor R8 is connected to the power supply 3.3V, an eighth pin is connected to one end of a resistor R23 and the other end of the resistor R23 are connected to the power supply 3.3V, a ninth pin is connected to the TP8 port and is connected to the 35 pin of the micro-control unit U7, a tenth pin is grounded, a tenth pin;

one end of a resistor R22 is connected with 3.3V, the other end of a resistor R22 is connected with a pin 10 of the micro control unit U7, one end of a resistor R21 is connected with 3.3V, and the other end of a resistor R21 is connected with a pin 11 of the micro control unit U7;

the D end of the MOS tube Q1 is connected with +3.3V and a capacitor C27, the S end is connected with a power supply 3.3V and one end of a resistor R24 (the resistor is not attached), and the G end and the S end of the MOS tube Q1 are connected with a pin 1 of the micro control unit U7 and one end of a resistor R24;

one end of the resistor R7 is connected with a power supply of-3.3V, the other end of the resistor R7 is connected with the power supply of 3.3V and one end of the capacitor C26, and the other end of the capacitor C26 is grounded;

the second pin of the voltage stabilizing integrated circuit unit Q5 is connected to one end of the capacitors C110 and C8, and the other end of the capacitors C110 and C8 is grounded, and the third pin is connected to one end of the capacitors C29 and C104, and the other end of the capacitors C29 and C104 is grounded;

one end of the inductor L1 is connected with a power supply 3.3V, a capacitor C110 and a capacitor C8, and the other end of the inductor L1 is connected with a power supply VBUS5V, a capacitor C29 and a capacitor C104;

the second pin of the non-regulated negative output voltage integrated circuit unit U3 is connected with +3.3V of the power supply, one end of a capacitor C107 and one end of a capacitor C108; the other ends of the capacitor C107 and the capacitor C108 are grounded, the first pin is connected with one ends of the capacitor C69, the capacitor C70 and the inductor L4, the other end of the inductor L4 is connected with one ends of-AVCC, the capacitor C69 and the capacitor C70, the other ends of the capacitor C69 and the capacitor C70 are grounded, the third pin is connected with one end of the capacitor C2, the fourth pin is grounded, and the fifth pin is connected with the other end of the capacitor C2;

one end of the capacitor C61, one end of the capacitor C20, and one end of the capacitor C10 are connected to a negative power supply terminal-AVCC, and the other end of the capacitor C61, one end of the capacitor C20, and one end of the capacitor C10 are grounded.

As shown in fig. 3-1, 3-2, 3-3, and 3-4, specifically, a first pin of the connector CON2 is connected to the VBUS5V power input port, a second pin is floating, a third pin is connected to one end (I2C data line) of the short-circuit point J3, a fourth pin is connected to one end (I2C clock line) of the short-circuit point J4, a fifth pin is grounded, a sixth pin is connected to one end of a resistor R9 (value range 4.7K-10K; value 5.6K is used to increase the driving capability, which plays a role of pulling up), another end of the resistor R9 is connected to the power 3.3V, a seventh pin is connected to the resistor R8 (value range 4.7K-10K; value 5.6K is used to increase the driving capability, which plays a role of pulling up), another end of the resistor R8 is connected to the power 3.3V, an S end of the MOS transistor Q3, a BAT2V4, and an eighth pin is connected to the resistor R23 (value range 4.7K-10K; value is used to increase the driving capability, playing a role of pulling up), the other end of the resistor R23 is connected with the power supply of 3.3V, the ninth pin is connected with the TP8 port and is connected with the 35 pin of the master control IC U7, the tenth pin is grounded, the eleventh pin is grounded, and the twelfth pin is grounded.

One end of a resistor R22 (with the value range of 4.7K-10K; the value of 5.6K plays a role in pulling up in order to increase the driving capability) is connected with 3.3V, the other end of a resistor R22 is connected with a pin 10 of the micro control unit U7, one end of a resistor R21 (with the value range of 4.7K-10K; the value of 5.6K plays a role in pulling up in order to increase the driving capability) is connected with 3.3V, and the other end of the resistor R21 is connected with a pin 11 of the micro control unit U7.

The D end of the MOS transistor Q1 is connected with +3.3V and a capacitor C27 (the value range is 0.01-0.1; the value is 0.1, the filtering effect is achieved in the circuit), the S end is connected with the power supply 3.3V and one end of a resistor R24 (the resistor is not attached), and the G end and the S end are connected with one pin of a main control IC U7 and one end of a resistor R24 (the resistor is not attached).

One end of the resistor R7 is connected with a power supply C-3.3V, the other end is connected with one end of a power supply 3.3V and one end of a capacitor C26 (the value ranges from 1UF to 4.7 UF; the value of 4.7UF plays a role of filtering in a circuit), and the other end of the capacitor C26 is grounded.

Operating environment temperature range of voltage regulator integrated circuit unit IC Q5(XC6206P 332): 40-85 degrees, a storage temperature range is-40-125 degrees, a second pin is connected with one end of the capacitor C110 (the value range is 1 UF-10 UF; the value range is 4.7 UF: high and low frequency signals are filtered in the circuit, and input ripples and noise are reduced), the other end of the capacitor C8 (the value range is 0.01 UF-0.1 UF; the value range is 0.1 UF: high frequency signals are filtered in the circuit, and input ripples and noise are reduced), the other end of the capacitor C110 and the other end of the capacitor C8 are grounded, a third pin is connected with one end of the capacitor C29 (the value range is 1 UF-10 UF; the value range is 4.7 UF: high and low frequency signals are filtered in the circuit, and input ripples and noise are reduced), the capacitor C104 (the value range is 0.01 UF-0.1 UF: high frequency signals are filtered in the circuit, and input ripples and noise are reduced), one end of.

One end of an inductor L1 (taking the value of 10UH, playing the role of power supply sudden change protection and filtering in the circuit) is connected with a power supply 3.3V and a capacitor C110 and a capacitor C8 thereof, and the other end of the inductor L1 is connected with a power supply VBUS5V and a capacitor C29 and a capacitor C104 thereof.

Operating environment temperature range of unstable voltage negative output voltage IC U3(TPS60403DBVRG 4): 40-85 degrees, a storage temperature range is-40-125 degrees, a second pin is connected with a capacitor C107 (the value range is 1 UF-10 UF; the value is 4.7 UF: high and low frequency signals are filtered in the circuit, and input ripples and noise are reduced), a capacitor C108 (the value range is 0.01 UF-0.1 UF; the value is 0.1 UF: high frequency signals are filtered in the circuit, and input ripples and noise are reduced), and a power supply is + 3.3V; the other ends of the capacitor C107 and the capacitor C108 are grounded, the first pin is connected with a capacitor C69 (value range: 1 UF-10 UF; value 4.7 UF: filtering high and low frequency signals in the circuit and reducing input ripples and noise) and a capacitor C70 (value range: 0.01 UF-0.1 UF; value 0.1 UF: filtering high frequency signals in the circuit and reducing input ripples and noise), an inductor L4 (value 10UH, playing a role in power supply sudden change protection and filtering in the circuit) is connected with one end of an AVCC, a capacitor C69 and a capacitor C70, the other ends of the capacitor C69 and the capacitor C70 are grounded, the third pin is connected with one end of the capacitor C2, the fourth pin is grounded, and the fifth pin is connected with the other end of the capacitor C2.

One end of a capacitor C61 (the value range is 1 UF-10 UF; the value range is 4.7 UF: filtering high and low frequency signals in a circuit and reducing input ripples and noise), one end of a capacitor C20 (the value range is 0.01 UF-0.1 UF; the value range is 0.1 UF: filtering high frequency signals in the circuit and reducing input ripples and noise), one end of a capacitor C10 (the value range is 0.01 UF-0.1 UF; the value range is 0.1 UF: filtering high frequency signals in the circuit and reducing input ripples and noise) are connected with a negative power supply terminal-AVCC, and the other ends of the capacitor C61, the capacitor C20 and the capacitor C10 are grounded.

The capacitance control module comprises a capacitance main control unit, a plurality of connectors and a plurality of capacitive reactance units, wherein after the capacitive reactance units are connected with the capacitance main control unit, the capacitance main control unit is subjected to operation of filtering high and low frequency signals, and input ripples and noise are reduced; the connector is connected with the capacitor main control unit and is an external interface of the control panel.

The capacitance control module comprises a capacitance main control unit U4, a connector J1, a resistor R8, a resistor R9, a resistor R12, a capacitor C4, a capacitor C5, a capacitor C17 and a capacitor C23, wherein,

the 1 st pin of the capacitance main control unit U4 is suspended by a free pin, the 2 nd pin is a grounding terminal CGND, the 3 rd, 4 th, 5 th and 6 th pins are suspended by a free pin, the 26 th pin of the 7 th pin connector J1, the 27 th pin of the 8 th pin connector J1, the 28 th pin of the 9 th pin connector J1, the 29 th pin of the 10 th pin connector J1, the 30 th pin of the 11 th pin connector J1, the 31 th pin of the 12 th pin connector J1, the 32 th pin of the 13 th pin connector J1, the 33 th pin of the 14 th pin connector J1, the 34 th pin of the 15 th pin connector J1, the 35 th pin of the 16 th pin connector J1, the 36 th pin of the 17 th pin connector J1, the 37 th pin of the 18 th pin connector J1, the 38 th pin connector J1, the 39 th pin of the 20 th pin J1, the 21 th pin connector J1, the 40 th pin 40 th, the 22 th pin connector J22 nd, the grounding terminal CGND 23 and the J1, the 42 th pin of the 24 th pin connector J1, the 43 th pin of the 25 th pin connector J1, the 44 th pin of the 26 th pin connector J1, the 45 th pin of the 27 th pin connector J1, the 46 th pin of the 28 th pin connector J1, the 47 th pin of the 29 th pin connector J1, the 48 th pin of the 30 th pin connector J1, the 49 th pin of the 31 th pin connector J1, the 50 th pin of the 32 th pin connector J1, the 51 st pin of the 33 th pin connector J1, the 52 th pin of the 34 th pin connector J1, the 53 th pin of the 35 th pin connector J1, the 54 th pin of the 36 th pin connector J1, the 55 th pin of the 37 th pin connector J1, the 38 th pin connector J1, the 57 th pin of the 39 th pin J1, the 58 th pin of the 40 th pin J6, the 59 th pin of the 41 th pin connector J1, the J73742 th pin connector J27 th pin connector J3661, the 3643 th pin connector J1 1 th pin connector J3661, pin 44 of connector J1 at pin 62, pin 45 at one end of capacitor C23, pin 46 at one end of capacitor C17, pin 47 at ground connection CGND2, pin 48 at one end of capacitor C5, pin 49 at TEST point TEST, pin 50 at pin 15 of mcu U7, pin 51 at pin 14 of mcu U7, pin 52 at pin 11 of mcu U7, pin 53 at TEST point P1.1, pin 54 at pin 10 of mcu U7, pin 55 at TEST point P1.3, pin 56 at TEST point C-RST connected to pin 7 of CON2, pin 57 at empty pin, pin 58 at TEST point C-INT 6 of CON2, pin 59 at empty pin 60 at one end of C4, pin 3, pin 62, pin 7376 at pin 3884, pin 1 at pin 3884, pin 84 of connector J7375, the 6 th pin of the 65 th pin connector J1, the 7 th pin of the 66 th pin connector J1, the 8 th pin of the 67 th pin connector J1, the 9 th pin of the 68 th pin connector J1, the 10 th pin of the 69 th pin connector J1, the 11 th pin of the 70 th pin connector J1, the 12 th pin of the 71 th pin connector J1, the 13 th pin of the 72 th pin connector J1, the 14 th pin of the 73 th pin connector J1, the 15 th pin of the 74 th pin connector J1, the 16 th pin of the 75 th pin connector J1, the 17 th pin of the 76 th pin connector J1, the 18 th pin of the 77 th pin connector J1, the 19 th pin of the 78 th pin connector J1, the 79 th pin connector J1, the 21 st pin of the 80 th pin connector J1, the 22 th pin of the 81 th pin J1, the 23 th pin 1, the 23 th pin 638, the 24 th pin connector J1 5, 86. 87 and 88 pins are suspended in the air;

pins 1, 2, 25 and 67 of the connector J1 are grounded and connected with CGND, and pins 64, 65 and 66 are suspended; pin 6 of the connector CON2 is connected to pin 58 of U4 and to one end of the resistor R9, and pin 7 is connected to pin 56 of the capacitor main control unit U4 and to one end of the resistor R8;

one end of the resistor R8 is connected to the 7 th pin of the CON2 and simultaneously connected to the 56 th pin of the capacitor main control unit U4, the other end of the resistor R8 is connected to the 3.3V power supply terminal, one end of the resistor R9 is connected to the 6 th pin of the CON2 and simultaneously connected to the 58 th pin of the capacitor main control unit U4, and the other end of the resistor R9 is connected to the 3.3V power supply terminal. One end of the resistor R12 is connected with CGND, and the other end of the resistor R12 is connected with CGND 2;

one end of a capacitor C4 is connected with a pin 61 of a capacitor main control unit U4 and is simultaneously connected with a 3.3V power supply end, the other end of a capacitor C4 is connected with CGND, one end of a capacitor C5 is connected with a pin 47 of the capacitor main control unit U4, the other end of a capacitor C5 is connected with CGND2, one end of a capacitor C17 is connected with a pin 46 of the capacitor main control unit U4, the other end of a capacitor C17 is connected with CGND2, one end of a capacitor C23 is connected with a pin 45 of the capacitor main control unit U4, and the other end of a capacitor C23 is connected with CGND 2.

As shown in fig. 4, specifically, the capacitance control module includes a capacitance main control unit U4, a connector J1(67PIN), a connector CON2(10PIN), a resistor R8, a resistor R9, a resistor R12, a capacitor C4, a capacitor C5, a capacitor C17, and a capacitor C23, where the chip U4 is WS 8711H. The working temperature of the chip is-40 ℃ to85 ℃, and the humidity is less than or equal to 95 percent RH; the storage temperature is-55 ℃ to110 ℃;

the connector CON2 is an external interface of the control board, and only the pins 6 and 7 are used in the capacitance control part. The pin 6 of the connector CON2 is connected to the pin 58 of the U4 and simultaneously connected to one end of the R9, and the pin 7 is connected to the pin 56 of the U4 and simultaneously connected to one end of the R8.

One end of the resistor R8 is connected to the 7 th pin of CON2 and simultaneously connected to the 56 th pin of U4, and the other end of the resistor R8 is connected to the power supply terminal of 3.3V. One end of R9 is connected to the 6 th pin of CON2 and the 58 th pin of U4, and the other end of R9 is connected to the 3.3V power supply terminal. One end of R12 is connected to CGND and the other end is connected to CGND 2. R8 and R9 are pull-up resistors (with the value range of 2K to 10K and the circuit value of 5K6, and have the function of limiting current in the circuit). R12 is a common ground CGND and ground CGND2 connection resistance, and takes 0 ohm according to the common ground single point connection principle.

One end of a capacitor C4 is connected with the 61 st pin of the U4 and is simultaneously connected with a power supply terminal of C3.3V, the other end of the C4 is connected with CGND, one end of the C5 is connected with the 47 th pin of the U4 and is connected with CGND2, one end of the C17 is connected with the 46 th pin of the U4 and is connected with CGND2, and one end of the C23 is connected with the 45 th pin of the U4 and is connected with CGND 2. Capacitors C4, C5, C17 and C19 (the value ranges are 0.01UF to 1UF, and capacitors C4 (the value ranges are 0.01UF to 0.1 UF; the value is 0.1 UF: high-frequency signals are filtered in a circuit, and input ripples and noises are reduced), and capacitors C5, C17 and C23 (the value ranges are 0.01UF to1 UF; the value is 1 UF: low-frequency signals are filtered in the circuit, and input ripples and noises are reduced).

The electromagnetic control module comprises an electromagnetic main control unit, a connector, a capacitive reactance unit and an inductive reactance unit, wherein after the capacitive reactance unit is connected with the electromagnetic main control unit, the electromagnetic main control unit is filtered to remove high-frequency signals, and input ripples and noises are reduced; and after the inductive reactance unit is connected with the electromagnetic main control unit, the electromagnetic main control unit is subjected to filtering and rectifying operations.

As shown in fig. 5, specifically, the electromagnetic control module includes an electromagnetic main control unit U10, a connector J2, an inductor L6 and a capacitor C15, wherein the 1 st pin of the electromagnetic main control unit U10 is connected to one end of the inductor L6 while the 2 nd pin is floating, the 3 rd pin is connected to the 1 st pin of the connector J2, the 4 th pin is connected to the 2 nd pin of the connector J2, the 5 th pin is connected to the 3 rd pin of the connector J2, the 6 th pin is connected to the 4 th pin of the connector J2, the 7 th pin is connected to the 5 th pin of the connector J2, the 8 th pin is connected to the 6 th pin of the connector J2, the 9 th pin is connected to the 7 th pin of the connector J2, the 10 th pin is connected to the 8 th pin of the connector J2, the 11 th pin is connected to the 6869 th pin of the connector J8, the 12 th pin is connected to the 10 th pin of the J6 th pin, the 13 th pin is connected to the J2, the 11 th pin is connected to the 2 th pin 3615, the connecting pin 3615 th pin of the connector, the 16 th pin is connected with the 14 th pin of the J2, the 17 th pin is connected with the 15 th pin of the J2, the 18 th pin is connected with the 16 th pin of the J2, the 19 th pin is connected with the 17 th pin of the J2, the 20 th pin is connected with the 18 th pin of the J2, the 21 st pin is connected with the 19 th pin of the J2, the 22 th pin is connected with the 20 th pin of the J2, the 23 th pin is connected with the 21 st pin of the J2, the 24 th pin is connected with the 22 nd pin of the J2, the 25 th pin is connected with the 23 th pin of the J2, the 26 th pin is connected with the 24 th pin of the J2, the 27 th pin is connected with the 25 th pin of the J2, the 28 th pin is connected with the 26 th pin of the J2, the 29 th pin is connected with the 27 th pin of the J2 th pin, the 30 th pin is connected with the 28 th pin of the J2, the 31 th pin is connected with the 29 th pin of the J638, the 32 th pin of the J2, the J33 th pin of the J68632, the 35 th pin is connected with the 33 th pin of the connector J2, the 36 th pin is connected with the 34 th pin of the connector J2, the 37 th pin is connected with the 35 th pin of the connector J2, the 38 th pin is connected with the 36 th pin of the connector J2, the 39 th pin is connected with the AGND terminal, the 40 th pin is suspended, the 41 th pin is suspended, the 42 th pin is connected with the 37 th pin of the connector J2, the 43 th pin is connected with the 38 th pin of the connector J2, the 44 th pin is connected with the 39 th pin of the connector J2, the 45 th pin is connected with the 40 th pin of the connector J2, the 46 th pin is connected with the 41 th pin of the connector J2, the 47 th pin is connected with the 22 th pin of the micro-control unit U7, the 48 th pin is connected with the 21 st pin of the micro-control unit U7, the 49 th pin is connected with the 7 th pin of the micro-control unit U7, the 50 th pin is connected with the 6 th pin of the U3, the 51 th pin is connected with the micro-control unit U7, the 53 th pin is connected with the AGND terminal, the 54 th pin is connected with the AVCC terminal, the 55 th pin is a COM output terminal, the 56 th pin is connected with the 42 th pin of the connector J2, the 57 th pin is connected with the 43 th pin of the connector J2, the 57 th pin is connected with the 44 th pin of the connector J2, the 59 th pin is connected with the 45 th pin of the connector J2, the 60 th pin is suspended, the 61 st pin is connected with the 46 th pin of the connector J2, the 62 th pin is connected with the 47 th pin of the connector J2, the 63 rd pin is connected with the 48 th pin of the connector J2, the 64 th pin is connected with the 49 th pin of the connector J2, the 65 th pin is connected with the 50 th pin of the connector J2, the 66 th pin is connected with the 51 th pin of the connector J2, the 67 th pin is connected with the 52 th pin of the connector J2, the 68 th pin is connected with the 53 th pin of the connector J2, the 54 th pin of the J6369 th pin is connected with the 54 th pin of the J2, the 55 th pin of the J2, the 73 th pin is connected with the 58 th pin of the connector J2, the 74 th pin is connected with the 59 th pin of the connector J2, the 75 th pin is connected with the 60 th pin of the connector J2, and the 76 th to 80 th pins are suspended;

one end of the inductor L6 is connected with the 1 st pin of the electromagnetic main control unit U10 and is also connected with one end of the capacitor C15, and the other end of the inductor L6 is connected with + 3.3V; the other terminal of the capacitor C15 is AGND. L6 and C15 form an LC filter circuit.

The solenoid control module includes an electromagnetic master control unit U10, a connector J2(67PIN), an inductance L6, and a capacitance C15. The chip U10 is WS8898E, the working temperature of the chip is-25 ℃ to75 ℃; the storage temperature was-50 ℃ to125 ℃.

Pins 1 through 60 of connector J2 correspond to the pins of chip U10 as described above. The No. 61, 62, 63 and 65 pins are empty pins and are suspended. Pins 64, 66, 67 are connected to AGND.

One end of the inductor L6 is connected with the 1 st pin of the chip U10 and is also connected with one end of the C15, and the other end of the inductor L6 is connected with + 3.3V; c15 is connected to pin 1 of U10 and L6, and the other end is AGND. L6 and C15 form an LC filter circuit, L6 (the value range is 2.2 UH-22 UH; the value of the whole circuit is L6 is 10UH, which mainly plays the role of filtering and rectifying in the circuit), and a capacitor C15 (the value range is 0.01 UF-0.1 UF; the value is 0.1UF, which filters high-frequency signals in the circuit and reduces input ripples and noise.

The signal control module includes: the integrated operational amplifier comprises an integrated operational amplifier unit and a plurality of impedance units, wherein the input end of the integrated operational amplifier unit is connected with the impedance units, so that the impedance matching of the integrated operational amplifier unit is improved, and the output of a previous-stage signal is stabilized; and the output end of the integrated operational amplifier unit is connected with an impedance unit, so that the output impedance of the integrated operational amplifier unit is improved.

The signal control module includes: an integrated operational amplifier unit U5, an integrated operational amplifier unit U6, a digital potentiometer U1, a resistor R73, a resistor 75, a resistor R74, a capacitor C50, an inductor L5, a resistor R77, a capacitor C77, a resistor R77, a capacitor C77, a capacitor R77, a resistor R77, a capacitor C77, a resistor R77, a diode D77, a capacitor C77, a triode Q36q 72, a resistor R36r 77, a resistor R77, a diode D77, a diode R36q,

a 12 th pin of the integrated operational amplifier unit U5 is in positive feedback connection with one end of a resistor R74 and one end of a capacitor C50, the other end of the resistor R74 is grounded, the other end of the capacitor C50 is connected with a 55 th pin of the electromagnetic main control unit U10 and a test point TP1, and a 13 th pin of the integrated operational amplifier unit U5 is in negative feedback connection with one end of the resistor R75 and one end of a resistor R73; the other end of the resistor R73 is connected with the output pin of the 14 th pin of the integrated operational amplifier unit U5, the other end of the resistor R73 is grounded, the output end of the 14 th pin of the integrated operational amplifier unit U5 is connected with the other end of the resistor R75 and one end of the resistor R76, the other end of the resistor R76 is connected with the positive feedback of the 10 th pin of the integrated operational amplifier unit U5 and one end of the capacitor C51, and the negative feedback of the 9 th pin of the integrated operational amplifier unit U5 is connected with one end of the resistor R82 and one end of the resistor R77; the other end of the resistor R77 is grounded, the output end of the 8 th pin of the integrated operational amplifier unit U5 is connected with the other end of the resistor R82 and one end of the resistor R32, the other end of the resistor R32 is connected with one end of the capacitor C19 and one end of the resistor R4, the other end of the capacitor C19 is grounded, the other end of the resistor R4 is connected with the 6 th pin of the digital positioner U1 and the 6 th pin of the integrated operational amplifier unit U5 for negative feedback, the 6 th pin of the integrated operational amplifier unit U5 is connected with the resistor R4 and the 6 th pin of the digital positioner U1, the 5 th pin of the integrated operational amplifier unit U5d for positive feedback grounding, the 7 th pin of the integrated operational amplifier unit U5 is connected with one end of the resistor R5, the other end of the resistor R5 is connected with one end of the capacitor C5, the 3 rd pin of the integrated operational amplifier unit U5 is connected with one end of the resistor R5 and one end of the integrated operational amplifier unit U5; the other end of the resistor R62 is grounded, the output end of the 1 st pin of the integrated operational amplifier unit U5 is connected with the other end of the resistor R64 and one end of the resistor R20, and the other end of the resistor R20 is connected with the resistor R19;

the 5 th pin of the integrated operational amplifier unit U6 is connected to the resistor R19, the other end of the capacitor C3 is grounded, the negative feedback of the 6 th pin of the integrated operational amplifier unit U6 is connected to one end of the resistor R30 and one end of the resistor R11, the other end of the resistor R11 is connected to ground, the other end of the resistor R11 is connected to the 7 th pin of the integrated operational amplifier unit U11, the output end of the 7 th pin of the integrated operational amplifier unit U11 is connected to the other end of the resistor R11, one end of the capacitor C11 and one end of the capacitor C11, the other end of the capacitor C11 is connected to one end of the capacitor C11 and one end of the resistor R11, the 9 th pin of the integrated operational amplifier unit U11 is connected to the resistor R11 and the output end of the 8 th pin of the integrated operational amplifier unit U11, the 130 th pin of the integrated operational amplifier unit U11 is connected to one end of the resistor R11 and the negative feedback of the capacitor C11, and the output end of the integrated operational amplifier unit U11 and the capacitor C11 are connected to the output end of the capacitor C11. The 12 th pin of the integrated operational amplifier unit U6 is positively feedback connected with the cathode of the diode D1, the anode of the diode D1 is connected with the resistor R10, the 13 th pin of the integrated operational amplifier unit U6 is negatively feedback connected with one end of the resistor R15 and one end of the resistor R14, the other end of the resistor R15 is grounded, the output end of the 14 th pin of the integrated operational amplifier unit U6 is connected with the resistor R14, the TP14 of the test point and the 5 th pin of the micro control unit U7, the 2 nd pin of the integrated operational amplifier unit U6 is negatively feedback connected with the capacitor R29, the other end of the resistor R29 is connected with the 8 th pin of the integrated operational amplifier unit U6, the 3 rd pin of the integrated operational amplifier unit U6 is positively feedback connected with one end of the resistor R33 and one end of the resistor R37, the other end of the resistor R33 is grounded, the other end of the resistor R37 is connected with the output end of the 1 st pin of the integrated operational amplifier unit U6.

As shown in fig. 6-1, 6-2, 6-3, and 6-4, specifically, the signal control module includes an integrated operational amplifier U5(TL084CPWR), an integrated operational amplifier U6(TL084CPWR), a digital potentiometer U1, a resistor R73, a resistor 75, a resistor R73, a capacitor C73, an inductor L73, a resistor R73, a capacitor C73, a resistor R73, a capacitor C73, a resistor R73, resistor R38.

Operational amplifier U5(TL084CPWR) operating ambient temperature range: -55-125 DEG, storage temperature range-40-125 DEG, positive feedback connecting resistance R74 of 12 th pin of operational amplifier U5 (value range 2K-10K; value 5.6K in circuit is mainly to let bias current flow through unbalanced signal source, generate a detuning error, if none of input signal source has large resistance and no resistive path is communicated with power ground, input common mode power supply rises until instrument amplification is in saturation state, only high resistance is connected to ground input end), and capacitance C50 (value range 0.01-0.1 UF; value 0.1UF in circuit is mainly to filter out direct current limit signal of signal source through capacitive coupling action, only alternating current signal is retained), resistance R74 is grounded, capacitance C50 is connected with 55 pin of inductance IC U10 and test point 1, negative feedback connecting resistance R75 of 13 th pin of U5 (value range 4.7K-10K; value 10K in circuit is designed to satisfy design Gain of 6 times, and amplification of gain can be completed only by matching with the resistor R73) and one end of the resistor R73; the other end of a resistor R73 (the value range is 1K-2K; the value of 2K in the circuit is to satisfy that the gain reaches 6 times when in design and the amplification factor of the gain can be completed only by matching with a resistor R75), the output pin of the 14 th pin of the operational amplifier U5 is connected, the other end of the resistor R73 is grounded, the output end of the 14 th pin of the operational amplifier U5 is connected with the other end of a resistor R75 and one end of a resistor R76 (the value range is 2K-5.6K; the value of 3K in the circuit is 3K, a resistor is connected in series at the output end to improve the output impedance of the operational amplifier), the other end of a resistor 76 is connected with the positive feedback of the 10 th pin and one end of a capacitor C51, the 10 th pin of the operational amplifier U5 is connected with a resistor R76 (the value range is 2K-5.6K; in the circuit, a resistor is connected in series at the input end to improve the impedance matching of the operational amplifier and a capacitor C51 (the value range is 200 PF-220, and the filter signal source of the direct current, only alternating current signals are reserved), a negative feedback connecting resistor R82 (the value range is 4.7K-10K; the value of 5.1K in the circuit is to satisfy the requirement that the gain reaches 2.7 times during design, and the amplification factor of the gain can be completed only by matching with the resistor R77) and one end of the resistor R77; the other end of a resistor R77 (the value range is 1K-5.6K; the value of 3K in the circuit is to satisfy the requirement that the gain reaches 2.7 times during design, and the amplification factor of the gain can be completed only by matching with a resistor R82), the other end of a resistor R82 is connected with the 8 th pin of the operational amplifier, the output end of the 8 th pin of the operational amplifier U5 is connected with the other end of a resistor R82 and a resistor R32 (the value range is 1K-5.6K; the value of 1K in the circuit is 1K, a resistor is connected in series at the output end to improve the output impedance of the operational amplifier), the other end of a resistor R32 is connected with a capacitor C19 (the value range is 200 PF-220 PF, the value of 220PF in the circuit is mainly used for filtering the circuit and filtering the direct current limit signals of a signal source, only alternating current signals are reserved) and a resistor R4 (the value range is 1K-5.6K; the value of 1K in the circuit is 1K, the value of 1K, the other end of the capacitor C19 is grounded, the other end of the resistor R4 is connected with the 6 th pin of the digital positioner U1 and the negative feedback of the 6 th pin of the operational amplifier U5, the 6 th pin of the operational amplifier U5 is connected with the resistor R4 (the value range is 1K-5.6K; the value is 1K in the circuit, a resistor is connected in series at the input end for improving the impedance matching of the operational amplifier) and the 6 th pin of the digital positioner U1, the 5 th pin of the operational amplifier U5 is grounded in positive feedback, the output end of the 7 th pin of the operational amplifier U5 is connected with the resistor R6 (the value range is 2K-5.6K; the value is 3K in the circuit, the resistor is connected in series at the output end for improving the output impedance of the operational amplifier), the other end of the resistor R6 is connected with the capacitor C48 (the value range is 0.01-0.1.1 UF; the value of 0.1UF in the circuit, the value is mainly used for keeping the direct current of a signal source through the coupling effect of the capacitor, only one end of the alternating current is filtered, the value of the amplifier is connected with the Mainly in order to make bias current flow through unbalanced signal source, produce a error of maladjustment, if there is not a very big and resistive route of input signal source resistance and power ground channel, the common mode power of input rises, until the instrument amplification is in saturation state, only resistance of the high resistance value grounds the input end) and electric capacity C48 (the range of value is 0.01-0.1 UF; the value of 0.1UF in the circuit is mainly that direct current limit signals of a signal source are filtered through the coupling effect of a capacitor, only alternating current signals are reserved, the other end of a resistor R61 is grounded, a capacitor C48 is connected with the other end of a resistor R6, and negative feedback of a No. 2 pin of an operational amplifier U5 is connected with a resistor R64 (the value range is 4.7K-10K; the value of 10K in the circuit is to satisfy the requirement that the gain reaches 4.3 times during design and the amplification factor of the gain can be completed only by matching with the resistor R62) and one end of the resistor R62; the other end of a resistor R62 (the value range is 1K-3K; the value of 3K in the circuit is to satisfy that the gain reaches 4.3 times when in design and the amplification factor of the gain can be completed only by matching with a resistor R64), the other end of a resistor R64 is connected with the output pin of the 1 st pin of U5, the output end of the 1 st pin of U5 of the operational amplifier is connected with the other end of a resistor R64 and a resistor R20 (the value range is 2K-5.6K; the value of 3.3K in the circuit, one end of a resistor is connected in series at the output end to improve the output impedance of the operational amplifier), and the other end of the resistor is connected with a resistor R19.

Operational amplifier U6(TL084CPWR) operating ambient temperature range: -55-125 degrees, a storage temperature range-40-125 degrees, an operational amplifier U6 pin 5 is connected with a resistor R19 (value range 2K-5.6K; value 3K in the circuit, a resistor is connected in series at the input end to improve impedance matching of operational amplifier) and a capacitor C3 (value range 120 PF-200 PF, value 120PF in the circuit is mainly used for filtering the circuit and filtering the direct current limit signal of the signal source, only the alternating current signal is reserved), the other end of the capacitor C3 is grounded, the negative feedback of the pin 6 of the operational amplifier U6 is connected with a resistor R30 (value range 1K-2K; value 2K in the circuit is used for meeting the requirement that the gain reaches 1.35 times during design and simultaneously the gain amplification factor can be completed by matching with the resistor R11) and one end of a resistor R11 (value range 1K-10K; value 5.6K in the circuit is used for meeting the requirement that the gain reaches 1.35 times during design, and simultaneously, the amplification factor of the gain can be completed only by matching with the resistor R30), the other end of the resistor R11 is connected to the ground, the other end of the resistor R30 is connected to the 7 th pin of the operational amplifier U6, and the output end of the 7 th pin of the operational amplifier U6 is connected to the other end of the resistor R30 and the capacitor C47 (the value range is 470 PF-560 PF; the value 470PF in the circuit is mainly to filter the direct current limit number of the signal source through the coupling effect of the capacitor and only keep the alternating current signal) and one end of the capacitor C7 (the value range is 470 PF-560 PF; the value 560PF in the circuit is mainly to filter the direct current limit number of the signal source through the coupling effect of the capacitor, only to retain the alternating current signal), the other end of the capacitor C70 is connected with one end of the resistor R19, the other end of the capacitor C47 is connected with one end of the capacitor C61 and one end of the resistor R68, and the 9 th pin of the operational amplifier U6 is connected with the resistor R68 (the value range is 150R-180R; the value of the circuit is 180R, a resistor is connected in series with an input end to improve impedance matching of operational amplifier and stabilize output of a signal of a previous stage) and an output end of a pin 8 of an operational amplifier U6, and a pin 130 of the operational amplifier U6 is connected with a resistor R67 (the value range is 20K to 22K; the value of 20K in the circuit is mainly to generate an offset error when bias current flows through an unbalanced signal source, if no input signal source has large resistance and no resistive path is communicated with a power supply ground, an input common-mode power supply rises until the amplification of the instrument is in a saturation state, and only a resistor with a high resistance value is used for grounding an input end) and a capacitor C61 (the value range is 470 PF-560 PF; the 470PF value in the circuit is mainly to filter the direct current limit number of the signal source through the coupling effect of the capacitor, only the alternating current signal is reserved), the other end of the resistor R67 is grounded, the other end of the capacitor C61 is connected with the resistor R68 and the capacitor C47, and the 8 th pin output end of the operational amplifier U6 is connected with the resistor R10 (the value range is 1K-2K; the value of the circuit is 2K, and a resistor is connected in series with the input end to improve the impedance matching of the operational amplifier and stabilize the output of a previous-stage signal and a resistor R29 (the value range is 30K-50K; the value of the operational amplifier U6 is 30K in the circuit, a resistor is connected in series at the output end to improve impedance matching of the operational amplifier and stabilize output of a signal of a previous stage), the 12 th positive feedback of the operational amplifier U6 is connected with the cathode of a diode D1(RB521CS-30) (used as a rectifier diode and a small signal detection diode in the circuit), the anode of a diode D1(RB521CS-30) is connected with a resistor R10, and the 13 th pin negative feedback of the operational amplifier U6 is connected with a resistor R15 (the value range is 20K-30K; the value of 22K in the circuit is to satisfy the requirement that the gain reaches 2.35 times during design, and the amplification factor of the gain can be completed only by matching with the resistor R14) and the resistor R14 (the value range is 20K-30K; the value of 30K in the circuit is to satisfy that the gain reaches 2.35 times when the circuit is designed, and simultaneously, the gain is matched with the resistor R15 to finish the amplification factor of the gain), the other end of the resistor R15 is grounded, the other end of the resistor R14 is connected with the output end of the 14 th pin of the operational amplifier U6, the output end of the 14 th pin of the operational amplifier U6 is connected with the resistor R14, the TP14 of the test point and the 5 th pin of the MCU U7, and the 2 nd pin of the operational amplifier U6 is connected with the capacitor R29 in negative feedback (the value range is 30K-50K; the value of the circuit is 30K, a resistor is connected in series at the input end to improve impedance matching of the operational amplifier and stabilize output of a signal of a previous stage, the other end of the resistor R29 is connected with the 8 th pin of the operational amplifier U6, and the 3 rd pin of the operational amplifier U6 is positively fed back and connected with a resistor R33 (the value range is 1K-4.7K; the value of 3K in the circuit is to satisfy that the gain reaches 34.3 times when the circuit is designed, and simultaneously, the gain amplification factor is matched with the resistor R37) and the resistor R37 (the value range is 100K-120K; the value of 100K in the circuit is to satisfy that the gain reaches 34.3 times during design, and simultaneously, the gain is matched with the resistor R33 to complete the amplification factor of the gain), the other end of the resistor R33 is grounded, the other end of the resistor R37 is connected with the output end of the 1 st pin of the operational amplifier U6, and the output end of the 1 st pin of the operational amplifier U6 is connected with the anode of a diode D1(RB521CS-30) (used as a rectifier diode and a small signal detection diode in the circuit).

The cathode of the diode D1(RB521CS-30) is connected with the resistor R38, the tested TP2 and the 17 th pin of the micro control unit U7.

The base electrode of a triode Q3(MMBT2222 AM; when the triode of the circuit is saturated, the collector electrode of the triode is opened to play a role of switching the circuit) is connected with a resistor R28 (the value range is 1K-4.7K, the value range of 4.7K in the circuit is mainly used for limiting current), the other end of the resistor R28 is connected with the 16 th pin of the MCUU7, the collector electrode of a triode Q3 is connected with a capacitor C9 (the value range is 560 PF-680 PF; the value range is 680PF in the circuit is used for filtering, rectifying and filtering the direct current limit number of a signal source, only an alternating current signal is reserved), the other end of the capacitor C9 is connected with the ground, and the triode Q3 is connected with.

One end of a capacitor C24 (the value range is 1 UF-10 UF; the value range is 4.7 UF: filtering high and low frequency signals in a circuit and reducing input ripples and noises), one end of a capacitor C22 (the value range is 0.01 UF-0.1 UF; the value range is 0.1 UF: filtering high frequency signals in the circuit and reducing input ripples and noises), one end of a capacitor C78 (the value range is 0.01 UF-0.1 UF; the value range is 0.1 UF: filtering high frequency signals in the circuit and reducing input ripples and noises) are connected with one end of a power supply + AVCC, and the other ends of the capacitor C24, the capacitor C22 and the capacitor C78 are connected with the ground.

Temperature range of working environment of digital potentiometer U1(MCP40D 17): the No. 1 pin of 40-125 degrees, the storage temperature range of-40-125 degrees is connected with one end of a power supply + AVCC and a capacitor C12 (the value range is 0.01 UF-0.1 UF; the value of 0.1 UF: high-frequency signals are filtered in a circuit, input ripples and noise are reduced), the other end of the power supply + AVCC is grounded, the No. 2 pin is grounded, the No. 3 pin is connected with the No. 29 pin of the micro-control unit U7, the No. 4 pin is connected with the No. 28 pin of the micro-control unit U7, the No. 5 pin is connected with a resistor R31, and the No. 6 pin is connected with the No. 6 pin of.

The electromagnetic capacitance dual-mode touch device can comprise a screen body substrate and a screen body cover plate covering the screen body substrate, wherein two surfaces of the screen body substrate are respectively provided with a capacitive inductor and an electromagnetic induction loop which are arranged in an array to form an upper layer and a lower layer of induction devices, one surface of the screen body substrate is provided with the capacitive inductor and the electromagnetic induction loop along the X direction, the other surface of the screen body substrate is provided with the capacitive inductor and the electromagnetic induction loop along the Y direction, and the X direction and the Y direction are arranged in a crossed mode.

The touch screen body is provided with capacitive sensors arranged in an array;

the touch screen body is provided with electromagnetic induction loops which are arranged into an array;

the capacitive sensors and the electromagnetic induction loops arranged on the touch screen body are sequentially arranged on one surface of the glass, and the induction devices are respectively placed on the two surfaces of the screen body substrate to form an upper layer induction device and a lower layer induction device.

The electromagnetic induction loop comprises an X-direction electromagnetic induction loop arranged on the upper layer of the screen body base material and a Y-direction electromagnetic induction loop arranged on the lower layer of the screen body base material, and coils which are regularly arranged and intersected in the X direction and the Y direction are used as a transmitting circuit and a receiving circuit of an electromagnetic induction device in the electromagnetic capacitance dual-mode touch device, and are used for transmitting electromagnetic signals and receiving signals sent by an electromagnetic pen, and position information such as coordinates, pressure, inclination angles and the like of the electromagnetic pen on the electromagnetic induction loop is calculated according to the strength of the signals.

The capacitive sensor comprises an X-direction capacitive sensor arranged on the upper layer of a screen body substrate and a Y-direction capacitive sensor arranged on the lower layer of the screen body substrate, the functions of the capacitive touch device in the electromagnetic capacitance dual-mode touch device are realized by regularly arranging the capacitive sensors intersected in the X direction and the Y direction, and when a user touches a screen body cover plate of the electromagnetic capacitance dual-mode touch device, due to the fact that a human body electric field and a high-frequency alternating current signal connected to a working layer, a coupling capacitor formed by a finger of the user and the working layer absorbs away an alternating current. The current flows from the electrodes at the four corners or the four sides of the screen, and theoretically, the current flowing through the four electrodes is proportional to the distance from the finger to the four corners, and the position of the touch point is obtained by precisely calculating the proportion of the four currents.

The screen body substrate can be ITO conductive glass, and the ITO conductive glass is manufactured by coating a layer of indium tin oxide (commonly called ITO) film on the basis of soda-lime-based or silicon-boron-based substrate glass by various methods such as sputtering, evaporation and the like. When the ITO layer is sputtered, different characteristics of the obtained ITO layer can be obtained between different targets and glass under different temperatures and motion modes.

The X direction and the Y direction in the screen body of the electromagnetic capacitance dual-mode touch device do not need to be vertically intersected physically but are adjusted according to a routing matching algorithm, and the vertical mode is the simplest and reliable implementation method for the algorithm and is the optimal implementation mode of the invention, which is not limited at all.

The embodiments in the present specification are generally described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

The application may be described in the general context of computer-executable instructions, such as program modules, or units, being executed by a computer. Generally, program modules or units may include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Generally, program modules or units may be implemented by software, hardware or a combination of both. The application may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules or units may be located in both local and remote computer storage media including memory storage devices.

In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description. The algorithms and displays presented herein are not inherently related to any particular computer, virtual machine, or other apparatus. Various general purpose systems may also be used with the teachings herein. The required structure for constructing such a system will be apparent from the description above. Moreover, the present invention is not directed to any particular programming language. It is appreciated that a variety of programming languages may be used to implement the teachings of the present invention as described herein, and any descriptions of specific languages are provided above to disclose the best mode of the invention.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that the invention as claimed requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.

The various component embodiments of the invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. It will be appreciated by those skilled in the art that a microprocessor or Digital Signal Processor (DSP) may be used in practice to implement some or all of the functions of some or all of the components of a playback device for video in a web page according to embodiments of the present invention. The present invention may also be embodied as apparatus or device programs (e.g., computer programs and computer program products) for performing a portion or all of the methods described herein. Such programs implementing the present invention may be stored on computer-readable media or may be in the form of one or more signals. Such a signal may be downloaded from an internet website or provided on a carrier signal or in any other form.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.

Claims

1. A control method of an electromagnetic capacitance dual-mode touch device comprises the following steps:

2. The method of claim 1,

3. The method of claim 1,

4. The method of claim 3,

5. The method of claim 4,

6. The method of claim 5,

7. The method of claim 6,