CN106324395B - A kind of electrification reset test method and system - Google Patents
A kind of electrification reset test method and system Download PDFInfo
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- CN106324395B CN106324395B CN201610682169.9A CN201610682169A CN106324395B CN 106324395 B CN106324395 B CN 106324395B CN 201610682169 A CN201610682169 A CN 201610682169A CN 106324395 B CN106324395 B CN 106324395B
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- sample
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- electrification reset
- oscillograph
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
Abstract
The invention discloses electrification reset test method and systems, electrification reset test method, electrification reset test is carried out applied to sample, include the following steps: that switching on and shutting down fixture is connected between the power supply of the sample and the sample by S1., the switching on and shutting down fixture provides a default Test Strategy, and the Test Strategy includes power-on time, power down time and switching on and shutting down number；Second probe of the oscillograph, is connected the second test point of the sample by the first test point that S2. the first probe of oscillograph is connected to the sample, and the oscillograph provides a default triggering mode；S3. start the switching on and shutting down fixture and electrification reset test is carried out to the sample according to the Test Strategy, the upper electrical waveform of the sample is obtained by the oscillograph.
Description
Technical field
The present invention relates to testing field more particularly to a kind of electrification reset test methods and system.
Background technique
In general, all there is a reset signal source in system, by the reset signal source as input, after processing of circuit
Distribute reset signals at different levels out again, eventually as the input reset signal of each IC chip.Electrification reset test is signal integrity
Essential test item in test, it is mainly used to verify the quality of reset signal during system electrification, it is ensured that powers on
Reset signal quality meets hardware design requirement in the process.Electrification reset needs to pay close attention to from waveform integrality, timing integrality
Signal quality.Wherein waveform integrality is that whether waveform has back ditch, step, burr, ring, overshoot phenomenon in measurement power up
Etc.；And timing integrality is then primarily upon whether the electrical waveform in necessary time reset signal reaches specific level value.
It is usually required in electrification reset test while measuring multiple signals, most commonly measure two paths of signals simultaneously,
Need at this time simultaneously with two probe vertical points in corresponding test point, then press again plug wire switching plate to tested single board into
Row powers on, and a people is too busy to do it at all.But if specially there is the personal waste for going to will cause manpower again by switch, cause to test
Inefficiency.
Summary of the invention
The existing above problem is tested for existing electrification reset, one kind is now provided and aims at saving manpower, is tested
High-efficient electrification reset test method and system.
Specific technical solution is as follows:
A kind of electrification reset test method is applied to carry out electrification reset test to sample, include the following steps:
S1. switching on and shutting down fixture is connected between the power supply of the sample and the sample, it is described to open
The fixture that shuts down provides a default Test Strategy, and the Test Strategy includes power-on time, power down time and switching on and shutting down number；
S2., the first test point that first probe of oscillograph is connected to the sample, by the second of the oscillograph
Probe connects the second test point of the sample, and the oscillograph provides a default triggering mode；
S3. start the switching on and shutting down fixture and electrification reset test carried out to the sample according to the Test Strategy,
The upper electrical waveform of the sample is obtained by the oscillograph.
Preferably, the triggering mode includes: triggering mode, trigger position, triggers edge type, level magnitudes and when
Base.
Preferably, the power supply of the sample is 220V.
Preferably, first test point is reference signal input terminal pin.
Preferably, second test point is reset signal pin.
A kind of electrification reset test macro is applied to carry out electrification reset test to sample, comprising:
One oscillograph, the first probe of the oscillograph connect the first test point of the sample, the oscillograph
The second probe connect the second test point of the sample, the oscillograph provides a default triggering mode, the oscillography
Upper electrical waveform of the device to the sample according to the triggering pattern acquiring；
One switching on and shutting down fixture, is connected between the power supply of the sample and the sample, the switch
Mechanism tool provides a default Test Strategy, and the Test Strategy includes power-on time, power down time and switching on and shutting down number；
The switching on and shutting down fixture passes through to carry out electrification reset test to the sample according to the Test Strategy
The oscillograph obtains the upper electrical waveform of the sample.
Preferably, the triggering mode includes: triggering mode, trigger position, triggers edge type, level magnitudes and when
Base.
Preferably, the power supply of the sample is 220V.
Preferably, first test point is reference signal input terminal pin.
Preferably, second test point is reset signal pin.
Above-mentioned technical proposal the utility model has the advantages that
Electrification reset test method saves manpower by the power on and off that switching on and shutting down fixture automatically controls sample, together
When improve testing efficiency；
Electrification reset test macro is for supporting electrification reset test method to carry out automatic electrification reset to sample
Test.
Detailed description of the invention
Fig. 1 is a kind of method flow diagram of embodiment of electrification reset test method of the present invention；
Fig. 2 is a kind of connection figure of embodiment of electrification reset test macro of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art without creative labor it is obtained it is all its
His embodiment, shall fall within the protection scope of the present invention.
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
The present invention will be further explained below with reference to the attached drawings and specific examples, but not as the limitation of the invention.
As shown in Figs. 1-2, a kind of electrification reset test method is applied to carry out sample 3 electrification reset test, packet
Include following step:
S1. switching on and shutting down fixture 2 is connected between the power supply 1 of sample 3 and sample 3, switching on and shutting down fixture 2
A default Test Strategy is provided, Test Strategy includes power-on time, power down time and switching on and shutting down number；
S2. by the first test point of the first probe connection sample 3 of oscillograph 4, the second probe of oscillograph 4 is connected
The second test point of sample 3 is connect, oscillograph 4 provides a default triggering mode；
S3. it starts switch mechanism tool 2 and electrification reset test is carried out to sample 3 according to Test Strategy, pass through oscillograph 4
Obtain the upper electrical waveform of sample 3.
Further, the first test point is reference signal input terminal pin, and the second test point is reset signal pin.
In the present embodiment, switching on and shutting down fixture 2 is connected between sample 3 and power supply 1；Preset oscillography
The indication range of device 4 sets triggering mode using a certain channel as trigger source；According to the demand of sample 3 to switching on and shutting down
The Test Strategy of fixture 2 is arranged accordingly, so that sample 3 can carry out switching on and shutting down (powering on, power down) behaviour automatically
Make；Test point is chosen, by probe (such as 1 channel) vertical point of oscillograph 4 in reference signal input terminal pin, by oscillograph
Reset signal pin of 4 another probe (such as 2 channels) vertical point in sample 3；After sample 3 powers on, oscillograph 4
Test waveform can be automatically grabbed, to obtain the abscissa distance between two signals (as reset pulsewidth).Electrification reset test
Method automatically controls that the powering on of sample 3, power down saves manpower by switching on and shutting down fixture 2, while improving testing efficiency.
In a preferred embodiment, triggering mode includes: triggering mode, and trigger position triggers edge type, level magnitudes
And Shi Ji.
In a preferred embodiment, the power supply 1 of sample 3 is 220V.
In the present embodiment, the power supply line of sample 3 is connect with a wiring board, can be by the fire in the power supply line of wiring board
Line disconnects in switching on and shutting down fixture 2 on the port of relay, and the attaching plug of wiring board is connected to the power supply 1 of 220V
On；12V power supply power supply can be used in switching on and shutting down fixture 2, and switching on and shutting down fixture 2 can be connect by serial ports with a client, passes through client
The Test Strategy in switching on and shutting down fixture 2 is tested at end accordingly, and the IP address of setting sample 3, setting are tested
The testing time (testing time need to guarantee determine sample 3 whether start normally) of each test operation of sample 3, on
Electric time (i.e. the time interval of electrification reset, several seconds more than the testing time of test operation), setting power down time are (i.e. every
Secondary source is disconnected to the time that power supply powers on again)；The switching on and shutting down number (3-5 times usual) of sample 3 is set.
As shown in Fig. 2, a kind of electrification reset test macro, is applied to carry out sample 3 electrification reset test, packet
It includes:
One oscillograph 4, the first test point of the first probe connection sample 3 of oscillograph 4, the second of oscillograph 4 are visited
Second test point of head connection sample 3, oscillograph 4 provide a default triggering mode, and oscillograph 4 is to according to triggering mode
Obtain the upper electrical waveform of sample 3；
One switching on and shutting down fixture 2, is connected between the power supply 1 of sample 3 and sample 3, and switching on and shutting down fixture 2 mentions
For a default Test Strategy, Test Strategy includes power-on time, power down time and switching on and shutting down number；
Switching on and shutting down fixture 2 is obtained to carry out electrification reset test to sample 3 according to Test Strategy by oscillograph 4
Take the upper electrical waveform of sample 3.
Further, the first test point is reference signal input terminal pin, and the second test point is reset signal pin.
In the present embodiment, switching on and shutting down fixture 2 is connected between sample 3 and power supply 1；Preset oscillography
The indication range of device 4 sets triggering mode using a certain channel as trigger source；According to the demand of sample 3 to switching on and shutting down
The Test Strategy of fixture 2 is arranged accordingly, so that sample 3 can carry out switching on and shutting down (powering on, power down) behaviour automatically
Make；Test point is chosen, by probe (such as 1 channel) vertical point of oscillograph 4 in reference signal input terminal pin, by oscillograph
Reset signal pin of 4 another probe (such as 2 channels) vertical point in sample 3；After sample 3 powers on, oscillograph 4
Test waveform can be automatically grabbed, to obtain the abscissa distance between two signals (as reset pulsewidth).Electrification reset test
Method automatically controls that the powering on of sample 3, power down saves manpower by switching on and shutting down fixture 2, while improving testing efficiency.
In a preferred embodiment, triggering mode includes: triggering mode, and trigger position triggers edge type, level magnitudes and Shi Ji.
In a preferred embodiment, the power supply 1 of sample 3 is 220V.
In the present embodiment, the power supply line of sample 3 is connect with a wiring board, can be by the fire in the power supply line of wiring board
Line disconnects in switching on and shutting down fixture 2 on the port of relay, and the attaching plug of wiring board is connected to the power supply 1 of 220V
On；12V power supply power supply can be used in switching on and shutting down fixture 2, and switching on and shutting down fixture 2 can be connect by serial ports with a client, passes through client
The Test Strategy in switching on and shutting down fixture 2 is tested at end accordingly, and the IP address of setting sample 3, setting are tested
The testing time (testing time need to guarantee determine sample 3 whether start normally) of each test operation of sample 3, on
Electric time (i.e. the time interval of electrification reset, several seconds more than the testing time of test operation), setting power down time are (i.e. every
Secondary source is disconnected to the time that power supply powers on again)；The switching on and shutting down number (3-5 times usual) of sample 3 is set.
The foregoing is merely preferred embodiments of the present invention, are not intended to limit embodiments of the present invention and protection model
It encloses, to those skilled in the art, should can appreciate that all with made by description of the invention and diagramatic content
Equivalent replacement and obviously change obtained scheme, should all be included within the scope of the present invention.
Claims (10)
1. a kind of electrification reset test method is applied to carry out electrification reset test to sample, which is characterized in that including under
State step:
S1. switching on and shutting down fixture is connected between the power supply of the sample and the sample, the switching on and shutting down
Fixture provides a default Test Strategy, and the Test Strategy includes power-on time, power down time and switching on and shutting down number；
S2., the first test point that first probe of oscillograph is connected to the sample, by the second probe of the oscillograph
The second test point of the sample is connected, the oscillograph provides a default triggering mode；
S3. start the switching on and shutting down fixture and electrification reset test is carried out to the sample according to the Test Strategy, pass through
The oscillograph obtains the upper electrical waveform of the sample.
2. electrification reset test method as described in claim 1, which is characterized in that the triggering mode includes: triggering mode,
Trigger position triggers edge type, level magnitudes and Shi Ji.
3. electrification reset test method as described in claim 1, which is characterized in that the power supply of the sample
For 220V.
4. electrification reset test method as described in claim 1, which is characterized in that first test point is that reference signal is defeated
Enter end pipe foot.
5. electrification reset test method as described in claim 1, which is characterized in that second test point is reset signal pipe
Foot.
6. a kind of electrification reset test macro is applied to carry out electrification reset test to sample characterized by comprising
One oscillograph, the first probe of the oscillograph connect the first test point of the sample, and the of the oscillograph
Two probes connect the second test point of the sample, and the oscillograph provides a default triggering mode, and the oscillograph is used
With the upper electrical waveform of the sample according to the triggering pattern acquiring；
One switching on and shutting down fixture, is connected between the power supply of the sample and the sample, the switching mechanism
Tool provides a default Test Strategy, and the Test Strategy includes power-on time, power down time and switching on and shutting down number；
The switching on and shutting down fixture is to carry out electrification reset test to the sample according to the Test Strategy, by described
Oscillograph obtains the upper electrical waveform of the sample.
7. electrification reset test macro as claimed in claim 6, which is characterized in that the triggering mode includes: triggering mode,
Trigger position triggers edge type, level magnitudes and Shi Ji.
8. electrification reset test macro as claimed in claim 6, which is characterized in that the power supply of the sample
For 220V.
9. electrification reset test macro as claimed in claim 6, which is characterized in that first test point is that reference signal is defeated
Enter end pipe foot.
10. electrification reset test macro as claimed in claim 6, which is characterized in that second test point is reset signal
Pin.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610682169.9A CN106324395B (en) | 2016-08-17 | 2016-08-17 | A kind of electrification reset test method and system |
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| CN201610682169.9A CN106324395B (en) | 2016-08-17 | 2016-08-17 | A kind of electrification reset test method and system |
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| CN106324395B true CN106324395B (en) | 2019-09-13 |
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Families Citing this family (8)
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| CN108627715B (en) * | 2017-03-21 | 2022-09-02 | 中兴通讯股份有限公司 | Method and device for detecting single board state |
| EP3444747A4 (en) | 2017-06-13 | 2019-08-14 | Shenzhen Goodix Technology Co., Ltd. | Optical biological recognition module, display device, and electronic equipment |
| CN109863410B (en) * | 2017-09-19 | 2021-03-05 | 深圳市汇顶科技股份有限公司 | Method and system for measuring power-on reset time |
| CN108132434A (en) * | 2017-12-14 | 2018-06-08 | 上海贝岭股份有限公司 | The test system and integrated circuit of por circuit |
| CN109030989B (en) * | 2018-06-22 | 2020-11-10 | 深圳市金泰克半导体有限公司 | Test method for verifying power-down protection function of solid state disk |
| CN109116266B (en) | 2018-09-05 | 2020-05-26 | 苏州浪潮智能科技有限公司 | Power module testing method |
| CN109581124A (en) * | 2018-12-24 | 2019-04-05 | 西南技术物理研究所 | A kind of switching on and shutting down pilot system for focus planar detector test |
| CN113704039A (en) * | 2021-09-03 | 2021-11-26 | 北京同方信息安全技术股份有限公司 | Auxiliary test equipment, system and method for computer product test |
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| CN101435841A (en) * | 2007-11-16 | 2009-05-20 | 鸿富锦精密工业（深圳）有限公司 | Test system and method |
| CN105093094A (en) * | 2015-09-16 | 2015-11-25 | 中国人民解放军国防科学技术大学 | Automatic chip power-on reliability detection device and detection method |
| CN105699788A (en) * | 2016-04-27 | 2016-06-22 | 浪潮电子信息产业股份有限公司 | Power supply time sequence measurement method, oscilloscope and system thereof |
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| TWI225933B (en) * | 2003-09-01 | 2005-01-01 | Faraday Tech Corp | Universal test platform and test method for latch-up |
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| CN101435841A (en) * | 2007-11-16 | 2009-05-20 | 鸿富锦精密工业（深圳）有限公司 | Test system and method |
| CN105093094A (en) * | 2015-09-16 | 2015-11-25 | 中国人民解放军国防科学技术大学 | Automatic chip power-on reliability detection device and detection method |
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Effective date of registration: 20200710 Address after: 313000 no.179-210, Zhizhou Avenue, Huaxi street, Changxing County, Huzhou City, Zhejiang Province Patentee after: CHANGXING TAIHU NENGGU TECHNOLOGY Co.,Ltd. Address before: 201600 Shanghai city Songjiang District Sixian Road No. 3666 Patentee before: Phicomm (Shanghai) Co.,Ltd. |
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