CN106301293B - D flip-flop and its method for transmitting signals - Google Patents
D flip-flop and its method for transmitting signals Download PDFInfo
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- CN106301293B CN106301293B CN201510256949.2A CN201510256949A CN106301293B CN 106301293 B CN106301293 B CN 106301293B CN 201510256949 A CN201510256949 A CN 201510256949A CN 106301293 B CN106301293 B CN 106301293B
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Abstract
This application discloses a kind of D flip-flop and its method for transmitting signals.Wherein, which includes: the reversed unit In of delay, for exporting the reversed clock signal after being delayed；First phase inverter I4, input terminal connect the input terminal of data-signal；First PMOS transistor M1.Second PMOS transistor M2；First NMOS transistor M3, drain electrode and the drain electrode of the first PMOS transistor M1 are connected to first node；Second NMOS transistor M4, drain electrode and the drain electrode of the second PMOS transistor M2 are connected to second node, and grid is connected with the grid of the first NMOS transistor M3 and receives clock signal；Third NMOS transistor M5, source electrode are connected with the input terminal of the first phase inverter I4；And the 4th NMOS transistor M6, grid are connected with third NMOS transistor M5 and are connected to the output end for the reversed unit In that is delayed.Present application addresses increase chip area while shortening the clock cycle in the prior art.
Description
Technical field
This application involves semiconductor fields, in particular to a kind of D flip-flop and its method for transmitting signals.
Background technique
As shown in Figure 1, being a data transmission path, data-signal D1 enters trigger DFF1 in the failing edge of clock,
Then trigger DFF1 is triggered in rising edge clock, data-signal D1 must be transferred to the output Q1 of trigger DFF1, then pass through
Combinational logic reaches trigger DFF2, and sets up before the arrival of the rising edge of next clock.In data transmission route
Diameter can transmit data-signal after establishing, and therefore, the clock cycle has to meet: T >=tcq1+tlogic+tsetup2, wherein tcq1
Indicate the time of clock signal clk to Q1 in first trigger DFF1, tlogicIt is the biography of combinational logic between two triggers
Defeated delay, tsetup2Indicate the settling time of second trigger DFF2.
If further to shorten the clock cycle, system frequency is improved, then will start in terms of above three, one
It is to speed up the t of DFF1cq1, one is the transmission delay t for shortening combinational logiclogic, one is to speed up the t of DFF2setup2。
Most common trigger structure is as shown in Fig. 2, the settling time (setup time) usually said is clock letter
Number reach before, data must keep the stable time.Trigger structure in Fig. 2, settling time are that data-signal D passes through instead
The time of phase device I2, I3, I4 and transmission gate T1, i.e. tsetup=tI4+tI2+tI3+tT1, in order to shorten settling time, believe in clock
The input terminal of number CK adds the arrival time of level-one phase inverter (I1) Lai Yanhuan clock.Be added phase inverter I1 after settling time be
tsetup=tI4+tI2+tI3+tT1-tI1, the transmission time (t of clockcq) the delay t that can also increase accordinglyI1, due to the transmission of clock
Delay can only impact next stage data path, so the delay of current data access can be accelerated.It thus can be with
The delay in the more nervous path of time margin (slack), it is moved in the more relaxed path of time margin, but simultaneously
Do not shorten the clock cycle really, increases the area of device occupancy due to increasing phase inverter instead.
For above-mentioned problem, currently no effective solution has been proposed.
Summary of the invention
The embodiment of the present application provides a kind of D flip-flop and its method for transmitting signals, at least to solve in the prior art
The technical issues of increasing chip area while shortening the clock cycle.
According to the one aspect of the embodiment of the present application, a kind of D flip-flop is provided, comprising: be delayed reversed unit, connection
It is used for input clock signal in the input terminal of clock signal input terminal, the reversed unit of delay, output end to be for exporting delay
Reversed clock signal afterwards；First phase inverter, input terminal connect the input terminal of data-signal；First PMOS transistor, source electrode connect
Connect high level；Second PMOS transistor, source electrode connect high level；First NMOS transistor, drain electrode and the first PMOS crystal
The drain electrode of pipe is connected to first node；Second NMOS transistor, drain electrode and the drain electrode of second PMOS transistor are connected to the
Two nodes, grid are connected with the grid of first NMOS transistor and receive the clock signal；Third NMOS transistor,
Drain electrode is connected with the source electrode of first NMOS transistor, and source electrode is connected with the input terminal of the first phase inverter；And the 4th
NMOS transistor, drain electrode are connected with the source electrode of second NMOS transistor, the output end of source electrode and first phase inverter
It is connected, grid is connected with the grid of the third NMOS transistor and is connected to the output end of the reversed unit of the delay,
Wherein, the first node is connected with the grid of second PMOS transistor, for exporting forward data signal, described
Two nodes are connected with the grid of first PMOS transistor, for exporting anti-data-signal.
Further, the D flip-flop further include: the second phase inverter, input terminal are connected to the second node, output
End is for exporting forward data signal.
Further, the D flip-flop further include: third phase inverter, output end are connected to the second node；4th
Phase inverter, input terminal are connected to the second node, and output end is connected to the input terminal of the third phase inverter.
Further, the D flip-flop further include: third phase inverter, output end are connected to the first node；4th
Phase inverter, input terminal are connected to the first node, and output end is connected to the input terminal of the third phase inverter, wherein described
First node is for exporting the data-signal.
Further, the delay time of the reversed unit of delay is more than or equal to first phase inverter and the described 4th
The delay summation of NMOS transistor.
Further, the reversed unit of delay is one or more phase inverters.
Further, the multiple phase inverter joins end to end, and the input terminal of the multiple phase inverter is anti-as the delay
To the input terminal of unit, output end of the output end of the multiple phase inverter as the reversed unit of delay.
According to the another aspect of the embodiment of the present application, a kind of method for transmitting signals of D flip-flop, the D are additionally provided
D-flip flop includes the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, the second NMOS transistor, third
NMOS transistor and the 4th NMOS transistor, the method for transmitting signals include: to control the third when clock signal is 0
NMOS transistor and the 4th NMOS transistor conducting, control first NMOS transistor and second NMOS transistor
Shutdown；When clock signal becomes 1 from 0, first NMOS transistor and the conducting of the second NMOS transistor, delay control are first controlled
Make the third NMOS transistor and the 4th NMOS transistor shutdown；In first NMOS transistor and described second
NMOS transistor is in the conductive state, and the state that the third NMOS transistor and the 4th NMOS transistor are also not turned off
Under, control data-signal is exported by second NMOS transistor and the 4th NMOS transistor, wherein in the third
After NMOS transistor and the 4th NMOS transistor shutdown, by first PMOS transistor and second PMOS transistor
Latch the data-signal.
Further, when clock signal becomes 1 from 0, first NMOS transistor and the 2nd NMOS crystal are first controlled
Pipe conducting, it includes: that the clock signal is defeated that delay, which controls the third NMOS transistor and the 4th NMOS transistor shutdown,
Enter the grid to first NMOS transistor and second NMOS transistor, to control first NMOS transistor and institute
State the conducting of the second NMOS transistor；The clock signal be input to after being delayed reversed unit the third NMOS transistor and
The grid of 4th NMOS transistor, to control the third NMOS transistor (M5) and the 4th NMOS transistor delay
Shutdown.
Further, in the conductive state and described in first NMOS transistor and second NMOS transistor
In the state that third NMOS transistor and the 4th NMOS transistor are also not turned off, control data-signal is brilliant by the 2nd NMOS
After body pipe and the 4th NMOS transistor output, the method for transmitting signals further include: compensate described the using latch
The loss of the threshold value of bi-NMOS transistor and the 4th NMOS transistor.
In the embodiment of the present application, a pair of NMOS transistors is controlled by positive clock signal, the clock letter being reversely delayed
Number control another pair of NMOS transistor, and the transmission forward direction number of a pair of NMOS transistors of reversed time delayed signal control
It is believed that number, another transmitting reverse data signal.Due to the presence of delay, data-signal is transmitted by two pair nmos transistors
To a pair pmos transistor, a pair of transistor of reversed time delayed signal control transmits forward data signal and reverse data letter respectively
Number, therefore, is latched by the data-signal that pair pmos transistor docking receives, make up data-signal in transmission process
The threshold value of NMOS is lost, and ensure that the accuracy of data signal transmission, meanwhile, reduce electronic component compared with prior art
Setting, reduces chip area, and then solves the skill for increasing chip area while shortening the clock cycle in the prior art
Art problem.
Detailed description of the invention
The drawings described herein are used to provide a further understanding of the present application, constitutes part of this application, this Shen
Illustrative embodiments and their description please are not constituted an undue limitation on the present application for explaining the application.In the accompanying drawings:
Fig. 1 is a kind of schematic diagram of data transfer path according to prior art；
Fig. 2 is a kind of circuit diagram of trigger according to prior art；
Fig. 3 is the circuit diagram according to a kind of optional D flip-flop of the embodiment of the present application；And
Fig. 4 is according to a kind of flow chart of the method for transmitting signals of optional D flip-flop of the embodiment of the present application.
Specific embodiment
In order to make those skilled in the art more fully understand application scheme, below in conjunction in the embodiment of the present application
Attached drawing, the technical scheme in the embodiment of the application is clearly and completely described, it is clear that described embodiment is only
The embodiment of the application a part, instead of all the embodiments.Based on the embodiment in the application, ordinary skill people
Member's every other embodiment obtained without making creative work, all should belong to the model of the application protection
It encloses.
It should be noted that the description and claims of this application and term " first " in above-mentioned attached drawing, "
Two " etc. be to be used to distinguish similar objects, without being used to describe a particular order or precedence order.It should be understood that using in this way
Data be interchangeable under appropriate circumstances, so as to embodiments herein described herein can in addition to illustrating herein or
Sequence other than those of description is implemented.In addition, term " includes " and " having " and their any deformation, it is intended that cover
Cover it is non-exclusive include, for example, the process, method, system, product or equipment for containing a series of steps or units are not necessarily limited to
Step or unit those of is clearly listed, but may include be not clearly listed or for these process, methods, product
Or other step or units that equipment is intrinsic.
Fig. 3 is the circuit diagram according to a kind of optional D flip-flop of the embodiment of the present application.As shown in figure 3, the D type touches
Hair device includes: the reversed unit In of delay, the first phase inverter I4, the first PMOS transistor M1, the second PMOS transistor M2, first
NMOS transistor M3, the second NMOS transistor M4, third NMOS transistor M5 and the 4th NMOS transistor M6, in which:
Be delayed reversed unit In, is connected to clock signal input terminal, and the input terminal for the reversed unit that is delayed is used for input clock
Signal, output end are used to export the reversed clock signal after delay.First phase inverter I4, input terminal connect the input of data-signal
End.First PMOS transistor M1, source electrode connect high level.Second PMOS transistor M2, source electrode connect high level.First NMOS is brilliant
Body pipe M3, drain electrode and the drain electrode of the first PMOS transistor M1 are connected to first node.Second NMOS transistor M4, drain electrode and second
The drain electrode of PMOS transistor M2 is connected to second node, and grid is connected with the grid of the first NMOS transistor M3 and receives clock
Signal.Third NMOS transistor M5, drain electrode are connected with the source electrode of the first NMOS transistor M3, source electrode and the first phase inverter I4's
Input terminal is connected.And the 4th NMOS transistor M6, drain electrode are connected with the source electrode of the second NMOS transistor M4, source electrode and the
The output end of one phase inverter I4 is connected, and grid is connected with the grid of third NMOS transistor M5 and is connected to the reversed list of delay
The output end of first In, wherein first node is connected with the grid of the second PMOS transistor M2, for exporting forward data letter
Number, second node is connected with the grid of the first PMOS transistor M1, for exporting reverse data signal.
Clock signal CK points are two-way, are directly conducted to the first NMOS transistor M3's and the second NMOS transistor M4 all the way
In addition grid passes through conduction after the delay for the reversed unit In that is delayed to third NMOS transistor M5 and the 4th NMOS transistor all the way
The grid of M6.Wherein, the clock signal all the way for being directly conducted to transistor can control the first NMOS transistor M3 and second
The turn-on and turn-off of NMOS transistor M4 can control the by the delay clock signal of be delayed reversed cell conducts to transistor
Three NMOS transistor M5's and the 4th NMOS transistor M6 is switched on and off.When clock signal CK controls the first NMOS transistor M3
When with the second NMOS transistor M4 shutdown, the clock signal CKN control third NMOS transistor M5 of delay and the 4th NMOS crystal
Pipe M6 conducting；After clock signal CK reversion, control the first NMOS transistor M3 and the second NMOS transistor M4 is connected immediately, and
Third NMOS transistor M5 and the 4th NMOS transistor M6 is closed after a period of time can be connected again due to the delay for the reversed unit that is delayed
It is disconnected.In the first NMOS transistor M3 and the second NMOS transistor M4 conducting and third NMOS transistor M5 and the 4th NMOS crystal
When pipe M6 is also not turned off, data-signal D is transferred to first node N1 from the first NMOS transistor M3 and third NMOS transistor M5,
Reverse data signal DN is transferred to second node N2 from the second NMOS transistor M4 and the 4th NMOS transistor M6.Wherein, first
The data letter of the grid output positive of the data-signal DN, the second PMOS transistor M2 of the grid output reverse phase of PMOS transistor M1
Number D.Due to having a threshold value loss in the second NMOS transistor M4 and the 4th NMOS transistor M6 transmission high level, still
Since low level signal is by controlling the second PMOS transistor M2 after the first NMOS transistor M3 and third NMOS transistor M5
It can open, voltage is stretched to supply voltage, so that the data-signal to second node latches.
Due to the settling time t of this circuitsetup=t4+tM6-ton, wherein t4 is the delay of phase inverter I4, tM6It is the 4th
The transmission delay of NMOS transistor M6, tonFor the delay for the reversed unit of being delayed, and tonDelay be greater than phase inverter I4 and the 4th
The delay of NMOS transistor M6, then the settling time t of circuitsetupFor negative value, thus the first NMOS transistor M3 and the 2nd NMOS
After transistor M4 is opened, third NMOS transistor M5 and the 4th NMOS transistor M6 will not be immediately turned off, and in the forward pass of shutdown
Transmission of data signal.In addition, passing through the first PMOS transistor M1, the second PMOS transistor M2, the first NMOS transistor M3 and second
The differential configuration that NMOS transistor M4 is constituted compensates for the threshold value loss because of the 4th NMOS transistor M6 transmission high level, from
And solve the problems, such as the settling time for shortening trigger in the prior art and increase the area of domain, compared with prior art obviously
The area for reducing domain.
Optionally, D flip-flop further include: the second phase inverter I7, input terminal are connected to second node, and output end is for defeated
Forward data signal out.Data-signal D and reverse data signal DN are transmitted to first node and the second section from two paths respectively
Point connects a phase inverter in second node, i.e. the second phase inverter I7 will to export forward data signal from second node
The reverse data signal DN of second node output is converted to data-signal D.
Optionally, D flip-flop further include: third phase inverter I5, output end are connected to second node.4th phase inverter
I6, input terminal are connected to second node, and output end is connected to the input terminal of third phase inverter.Third phase inverter I5 and the 4th reverse phase
Device I6 joins end to end, and is connected at second node, for latching the data at second node.Especially mended in low frequency
It repays, avoid the data-signal loss for being transferred to second node or loses.
Optionally, D flip-flop further include: third phase inverter I5, output end are connected to first node.4th phase inverter
I6, input terminal are connected to first node, and output end is connected to the input terminal of third phase inverter I5, wherein first node is for defeated
Data-signal out.If from first node outputting data signals, by end to end third phase inverter I5 and the 4th phase inverter
I6 is connected at first node, for latching the data at first node.It is especially compensated in low frequency, avoids being transferred to
The data-signal of first node is lost or loses.
Optionally, the reversed unit In that is delayed is one or more phase inverters, and the delay time for the reversed unit In that is delayed is greater than
Equal to the delay summation of the first phase inverter I4 and the 4th NMOS transistor M6.Multiple phase inverters join end to end, multiple phase inverters
Input terminal of the input terminal as the reversed unit In that is delayed, output end of the output end of multiple phase inverters as the reversed unit that is delayed.
Clock signal CK is after the reversed unit of delay being made up of multiple phase inverters (showing three phase inverters in Fig. 3), by clock
Signal CK is converted to reversed signal CKN always, and is delayed to clock signal CK so that delay time be greater than etc.
In the delay summation of the first phase inverter I4 and the 4th NMOS transistor M6, thus ensure that control the first NMOS transistor M3 and
When the clock signal CK of second NMOS transistor M4 controls its conducting, it is brilliant that reversed clock signal CKN delay reaches the 3rd NMOS
Body pipe M5 and the 4th NMOS transistor M6, in the first NMOS transistor M3, the second NMOS transistor M4, third NMOS transistor
In the case that M5 and the 4th NMOS transistor M6 is both turned on, forward data signal and reverse data signal are transmitted.
In the present embodiment, a pair of NMOS transistors is controlled by positive clock signal, the clock signal control being reversely delayed
Another pair of NMOS transistor, and the transmission forward data letter of a pair of NMOS transistors of reversed time delayed signal control
Number, another transmitting reverse data signal.Due to the presence of delay, data-signal is transmitted to one by two pair nmos transistors
A pair of transistor of pair pmos transistor, reversed time delayed signal control transmits forward data signal and reverse data signal respectively,
Therefore, it is latched by the data-signal that pair pmos transistor docking receives, makes up data-signal in transmission process
The threshold value of NMOS is lost, and ensure that the accuracy of data signal transmission, meanwhile, reduce electronic component compared with prior art
Setting, reduces chip area.
The embodiment of the present application also provides a kind of method for transmitting signals of D flip-flop.The signal of the D flip-flop transmits
Method carries out signal transmission by above-mentioned D flip-flop, as shown in figure 4, the method for transmitting signals of the D flip-flop includes such as
Lower step:
Step S102 controls third NMOS transistor M5 and the 4th NMOS transistor M6 conducting when clock signal is 0,
Control the first NMOS transistor M3 and the second NMOS transistor M4 shutdown.
Step S104 first controls the first NMOS transistor M3 and the second NMOS transistor when clock signal becomes 1 from 0
M4 conducting, delay control third NMOS transistor M5 and the 4th NMOS transistor M6 shutdown.
Step S106, it is in the conductive state in the first NMOS transistor M3 and the second NMOS transistor M4, and the 3rd NMOS
In the state that transistor M5 and the 4th NMOS transistor M6 is also not turned off, control data-signal by the second NMOS transistor M4 and
4th NMOS transistor M6 output, wherein after third NMOS transistor M5 and the 4th NMOS transistor M6 shutdown, by first
PMOS transistor M1 and the second PMOS transistor M2 latch data signal.
Optionally, when clock signal becomes 1 from 0, the first NMOS transistor M3 and the second NMOS transistor M4 are first controlled
Conducting, delay control third NMOS transistor M5 and the 4th NMOS transistor M6 shutdown include: clock signal input to first
The grid of NMOS transistor M3 and the second NMOS transistor M4, to control the first NMOS transistor M3 and the second NMOS transistor M4
Conducting.Clock signal is input to the grid of third NMOS transistor M5 and the 4th NMOS transistor M6 after being delayed reversed unit
Pole, to control third NMOS transistor M5 and the 4th NMOS transistor M6 time delayed turn-off.
The present embodiment is illustrated for 0 → 1, data-signal D 0 below with reference to Fig. 3, and with clock signal.
Clock signal CK is connected to the first NMOS transistor M3, the grid end of second two NMOS tubes of NMOS transistor M4, and
And pass through phase inverter I1, the grid end of I2, I3 connection two NMOS tubes of M5, M6.
When data-signal D is 0, and clock signal CK is 0, the first NMOS transistor M3, the second NMOS transistor M4 shutdown,
Third NMOS transistor M5, the 4th NMOS transistor M6 unlatching, wherein third NMOS transistor M5 transmission 0, the 4th NMOS crystal
Pipe M6 transmission 1, due to being NMOS tube, M6 transmission high level has a threshold value loss.
When clock signal CK by 0 overturning for 1 when, the first NMOS transistor M3, the second NMOS transistor M4 are connected immediately, and
Third NMOS transistor M5, the 4th NMOS transistor M6 are still suffered from one section and are opened due to phase inverter I1, the transmission delay of I2, I3
The time ton=t1+t2+t3 opened, wherein t1, t2, t3 respectively correspond phase inverter I1, the transmission delay of I2, I3.Data are believed at this time
Number D and the first NMOS transistor M3, third NMOS transistor M5 and second are passed through by the reverse data signal DN after I4 respectively
NMOS transistor M4, the 4th NMOS transistor M6 are transferred to the grid end of the second PMOS transistor M2 and the first PMOS transistor M1.
Second NMOS transistor M4, the 4th NMOS transistor M6 have a threshold value loss in transmission high level, but since data are believed
Number D is 0, passes through the first NMOS transistor M3, controls the second PMOS transistor M2 after third NMOS transistor M5 and open, can handle
Voltage is stretched to supply voltage.When data-signal D is 1, reverse data signal DN is 0 directly by the second NMOS transistor
M4, the 4th NMOS transistor M6 are transferred to the grid end of the first PMOS transistor M1, are then transferred to Q by phase inverter I7.
The settling time tsetup=t4+tM6-ton of this circuit structure, wherein t4 indicates the delay of phase inverter I4, tM6 table
Be shown as the transmission delay of the 4th NMOS transistor M6 of transmission gate, when clock signal CK is from 0 → 1, this rising edge by I1,
I2, I3 are converted into the failing edge from 1 → 0, this failing edge and M5, the cut-off signals of M6, as long as arriving in this cut-off signals
Up to before, data-signal D can then be successfully established connection by phase inverter I4 and the 4th NMOS transistor M6.Due to anti-
Phase device I1, I2, the sum of delay of I3 ton, hence it is evident that greater than the delay of phase inverter I4 and the 4th NMOS transistor M6, so tsetup
It is a negative value, its significance lies in that, the clock signal CK after overturning reaches the first NMOS transistor M3 and the second NMOS transistor
After M4, data-signal D still can be transmitted.
Optionally, in the conductive state in the first NMOS transistor M3 and the second NMOS transistor M4, and the 3rd NMOS is brilliant
In the state that body pipe M5 and the 4th NMOS transistor M6 is also not turned off, control data-signal passes through the second NMOS transistor M4 and the
After four NMOS transistor M6 output, method for transmitting signals further include: compensate the second NMOS transistor M4 and the using latch
The threshold value of four NMOS transistor M6 is lost.By the first PMOS transistor M1 and the second PMOS transistor M2 latch first node and
The data-signal of second node, to compensate the threshold value loss of the second NMOS transistor M4 and the 4th NMOS transistor M6.Meanwhile benefit
The data of second node are latched, with phase inverter I5 and phase inverter I6 to guarantee to be transmitted to second node in low frequency clock signal
Data-signal correctly can be latched and be exported.
In the present embodiment, a pair of NMOS transistors is controlled by positive clock signal, the clock signal control being reversely delayed
Another pair of NMOS transistor, and the transmission forward data letter of a pair of NMOS transistors of reversed time delayed signal control
Number, another transmitting reverse data signal.Due to the presence of delay, data-signal is transmitted to one by two pair nmos transistors
A pair of transistor of pair pmos transistor, reversed time delayed signal control transmits forward data signal and reverse data signal respectively,
Therefore, it is latched by the data-signal that pair pmos transistor docking receives, makes up data-signal in transmission process
The threshold value of NMOS is lost, and ensure that the accuracy of data signal transmission, meanwhile, reduce electronic component compared with prior art
Setting, reduces chip area.
It in above-described embodiment of the application, all emphasizes particularly on different fields to the description of each embodiment, without detailed in some embodiment
The part stated, reference can be made to the related descriptions of other embodiments.
The above is only the preferred embodiment of the application, it is noted that for the ordinary skill people of the art
For member, under the premise of not departing from the application principle, several improvements and modifications can also be made, these improvements and modifications are also answered
It is considered as the protection scope of the application.
Claims (10)
1. a kind of D flip-flop characterized by comprising
Be delayed reversed unit (In), is connected to clock signal input terminal, the input terminal of the reversed unit (In) of delay is for defeated
Enter clock signal, output end is used to export the reversed clock signal after delay；
First phase inverter (I4), input terminal connect the input terminal of data-signal；
First PMOS transistor (M1), source electrode connect high level；
Second PMOS transistor (M2), source electrode connect high level；
First NMOS transistor (M3), drain electrode and the drain electrode of first PMOS transistor (M1) are connected to first node；
Second NMOS transistor (M4), drain electrode and the drain electrode of second PMOS transistor (M2) are connected to second node, grid
It is connected with the grid of first NMOS transistor (M3) and receives the clock signal；
Third NMOS transistor (M5), drain electrode are connected with the source electrode of first NMOS transistor (M3), and source electrode and first is instead
The input terminal of phase device (I4) is connected；And
4th NMOS transistor (M6), drain electrode are connected with the source electrode of second NMOS transistor (M4), source electrode and described the
The output end of one phase inverter (I4) is connected, and grid is connected with the grid of the third NMOS transistor (M5) and is connected to institute
The output end for the reversed unit (In) that is delayed is stated,
Wherein, the first node is connected with the grid of second PMOS transistor (M2), for exporting forward data letter
Number, the second node is connected with the grid of first PMOS transistor (M1), for exporting anti-data-signal.
2. D flip-flop according to claim 1, which is characterized in that the D flip-flop further include:
Second phase inverter (I7), input terminal are connected to the second node, and output end is for exporting forward data signal.
3. D flip-flop according to claim 1 or 2, which is characterized in that the D flip-flop further include:
Third phase inverter (I5), output end are connected to the second node；
4th phase inverter (I6), input terminal are connected to the second node, and output end is connected to the third phase inverter (I5)
Input terminal.
4. D flip-flop according to claim 1, which is characterized in that the D flip-flop further include:
Third phase inverter (I5), output end are connected to the first node；
4th phase inverter (I6), input terminal are connected to the first node, and output end is connected to the third phase inverter (I5)
Input terminal, wherein the first node is for exporting the data-signal.
5. D flip-flop according to claim 1, which is characterized in that the delay time of the reversed unit (In) of delay
More than or equal to the delay summation of first phase inverter (I4) and the 4th NMOS transistor (M6).
6. D flip-flop according to claim 1 or 5, which is characterized in that the reversed unit (In) of the delay be one or
Multiple phase inverters.
7. D flip-flop according to claim 6, which is characterized in that the multiple phase inverter joins end to end, the multiple
Input terminal of the input terminal of phase inverter as the reversed unit (In) of the delay, described in the output end of the multiple phase inverter is used as
Be delayed the output end of reversed unit (In).
8. a kind of method for transmitting signals of D flip-flop, which is characterized in that pass through D described in any one of claims 1 to 7
D-flip flop carry out signal transmission, the D flip-flop include the first PMOS transistor (M1), the second PMOS transistor (M2),
First NMOS transistor (M3), the second NMOS transistor (M4), third NMOS transistor (M5) and the 4th NMOS transistor (M6),
The method for transmitting signals includes:
When clock signal is 0, the third NMOS transistor (M5) and the 4th NMOS transistor (M6) conducting, control are controlled
Make first NMOS transistor (M3) and second NMOS transistor (M4) shutdown；
When clock signal becomes 1 from 0, first controls first NMOS transistor (M3) and the second NMOS transistor (M4) is led
Logical, delay controls the third NMOS transistor (M5) and the 4th NMOS transistor (M6) shutdown；
It is in the conductive state in first NMOS transistor (M3) and second NMOS transistor (M4), and the third
In the state that NMOS transistor (M5) and the 4th NMOS transistor (M6) are also not turned off, control data-signal passes through described the
Bi-NMOS transistor (M4) and the 4th NMOS transistor (M6) output,
Wherein, after the third NMOS transistor (M5) and the 4th NMOS transistor (M6) shutdown, by described first
PMOS transistor (M1) and second PMOS transistor (M2) latch the data-signal.
9. the method for transmitting signals of D flip-flop according to claim 8, which is characterized in that become in clock signal from 0
When 1, first NMOS transistor (M3) and the second NMOS transistor (M4) conducting are first controlled, delay controls the 3rd NMOS
Transistor (M5) and the 4th NMOS transistor (M6) shutdown include:
The clock signal input to first NMOS transistor (M3) and second NMOS transistor (M4) grid, with
Control first NMOS transistor (M3) and second NMOS transistor (M4) conducting；
The clock signal is input to the third NMOS transistor (M5) and the 4th NMOS after being delayed reversed unit
The grid of transistor (M6) is closed with controlling the third NMOS transistor (M5) and the 4th NMOS transistor (M6) delay
It is disconnected.
10. the method for transmitting signals of D flip-flop according to claim 8 or claim 9, which is characterized in that described first
NMOS transistor (M3) and second NMOS transistor (M4) are in the conductive state, and the third NMOS transistor (M5) and
In the state that 4th NMOS transistor (M6) is also not turned off, control data-signal passes through the second NMOS transistor (M4) and institute
After stating the output of the 4th NMOS transistor (M6), the method for transmitting signals further include:
It is lost using the threshold value that latch compensates second NMOS transistor (M4) and the 4th NMOS transistor (M6).
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050106577A (en) * | 2004-05-04 | 2005-11-10 | 삼성전자주식회사 | Latch and flip-flop having the latch |
| CN102156502A (en) * | 2010-12-24 | 2011-08-17 | 无锡更芯集成科技有限公司 | Zero static power consumption circuit device for different voltage domains of analogue integrated circuit |
| CN104124943A (en) * | 2010-04-12 | 2014-10-29 | 联发科技股份有限公司 | Flip-flop |
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| JP2007006463A (en) * | 2005-05-25 | 2007-01-11 | Toshiba Corp | Semiconductor integrated circuit device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050106577A (en) * | 2004-05-04 | 2005-11-10 | 삼성전자주식회사 | Latch and flip-flop having the latch |
| CN104124943A (en) * | 2010-04-12 | 2014-10-29 | 联发科技股份有限公司 | Flip-flop |
| CN102156502A (en) * | 2010-12-24 | 2011-08-17 | 无锡更芯集成科技有限公司 | Zero static power consumption circuit device for different voltage domains of analogue integrated circuit |
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