CN106298892A - The manufacture method of VDMOS device - Google Patents
The manufacture method of VDMOS device Download PDFInfo
- Publication number
- CN106298892A CN106298892A CN201510278374.4A CN201510278374A CN106298892A CN 106298892 A CN106298892 A CN 106298892A CN 201510278374 A CN201510278374 A CN 201510278374A CN 106298892 A CN106298892 A CN 106298892A
- Authority
- CN
- China
- Prior art keywords
- layer
- mask layer
- grid
- manufacture method
- vdmos device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000000463 material Substances 0.000 claims description 12
- 238000000407 epitaxy Methods 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 description 17
- 238000001259 photo etching Methods 0.000 description 11
- 238000000151 deposition Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000007792 gaseous phase Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The present invention provides the manufacture method of a kind of VDMOS device, including: in substrate, form mask layer；With described mask layer as mask, carry out ion implanting, form the channel region of the JFET of high concentration；The channel region of described JFET is formed oxide layer；Described oxide layer is formed grid；Remove described mask layer；With described grid as mask, carry out ion implanting, form body district.The manufacture method of the VDMOS device according to the present invention, it is possible to save production cost.
Description
Technical field
The present invention relates to semiconductor technology, particularly relate to the manufacture method of a kind of VDMOS device.
Background technology
VDMOS (Vertical Double Diffused Metal Oxide Semiconductor, vertical DMOS) device has bipolar transistor and common MOS (Metal Oxide Semiconductor concurrently, metal-oxide semiconductor (MOS)) advantage of device, either switch application or linear application, VDMOS device is all preferable power device.The application of VDMOS device is widely at present, such as electric machine speed regulation, inverter, uninterrupted power source, electrical switch, high-fidelity music center, car electrics and electric ballast etc..
In prior art, the manufacture process of VDMOS device is: first, in one layer of N-type epitaxy layer of heavy doping N+ Grown, then, the grid above gate oxide and gate oxide is formed by photoetching process, being formed raceway groove by the difference of p-type base Yu twice horizontal proliferation junction depth of N+ source region the most respectively, the two region is all to form mask by photoetching process in ion implantation process, and injects respective impurity in the case of mask is sheltered.Wherein, the grid of two i.e. JFET of p-type doped region, the N-type semiconductor district i.e. raceway groove of JFET between Liang GePXing Ti district, the two ends of N-type semiconductor are respectively source electrode and the drain electrode of JFET.
The width of the grid reducing VDMOS device can improve the integrated level of VDMOS device, but also bring the problem that JFET (Junction Field Effect Transistor, junction field effect transistor) district's resistance increases simultaneously.The problem that the JFET district resistance brought in order to avoid reducing the width of the grid of VDMOS increases, before forming gate oxide, can carry out the ion implanting of high concentration in JFET district.But, such that increase a photoetching when making VDMOS, and then add the production cost of VDMOS.
Summary of the invention
The present invention provides the manufacture method of a kind of VDMOS device, the problem increased with the production cost solving to bring owing to JFET district carrying out the ion implanting of high concentration in prior art.
The present invention provides the manufacture method of a kind of VDMOS device, including:
Substrate is formed mask layer；
With described mask layer as mask, carry out ion implanting, form the channel region of the JFET of high concentration；
The channel region of described JFET is formed oxide layer；
Described oxide layer is formed grid；
Remove described mask layer；
With described grid as mask, carry out ion implanting, form body district.
The manufacture method of VDMOS device as above, alternatively, forms grid in described oxide layer and includes:
Described mask layer and described oxide layer form gate material layers by depositional mode；
Using chemically mechanical polishing mode to remove the described mask layer part higher than the described gate material layers in described oxide layer, form described grid, the top of described mask layer flushes with the top of described grid.
The manufacture method of VDMOS device as above, alternatively, forms oxide layer on the channel region of described JFET and includes:
Thermal oxide mode is used to form described oxide layer on the channel region of described JFET.
The manufacture method of VDMOS device as above, alternatively, removes described mask layer and includes:
Wet method mode is used to remove described mask layer.
The manufacture method of VDMOS device as above, alternatively, described substrate includes N-type substrate and the N-type epitaxy layer being formed in described N-type substrate.
The manufacture method of VDMOS device as above, alternatively, the described mask layer that formed in substrate includes:
Formation of deposits mask layer on the substrate；
Etch described mask layer, have figuratum described mask layer to be formed.
The manufacture method of VDMOS device as above, alternatively, after described formation body district, also includes:
Described substrate is carried out ion implanting, the both sides of described grid and in described body district formed source region；
Forming dielectric layer on described grid, the width of described dielectric layer is more than the width of described grid；
Described body district and described dielectric layer form described metal level.
As shown from the above technical solution, the manufacture method of the VDMOS device that the present invention provides, by being initially formed the channel region of the JFEP of high concentration, then grid and the formation process in body district are carried out, it can be avoided that JFEP to be carried out the photoetching process that high concentration ion needs individually to carry out, and then avoid the increase of production cost.And the mask owing to being used when forming the channel region of JFEP of high concentration can apply to form grid, therefore, can reduce by a photoetching process further, and then save production cost further.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, the accompanying drawing used required in embodiment or description of the prior art will be briefly described below, apparently, accompanying drawing in describing below is some embodiments of the present invention, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the schematic flow sheet of the manufacture method of the VDMOS device according to one embodiment of the invention；
Fig. 2 A to 2G show the structural representation of each step of the manufacture method of VDMOS device according to another embodiment of the present invention.
Detailed description of the invention
Embodiment one
The present embodiment provided the manufacture method of a kind of VDMOS device, was used for making VDMOS device.As it is shown in figure 1, be the schematic flow sheet of the manufacture method of the VDMOS device according to the present embodiment.The manufacture method of the VDMOS device of the present embodiment includes:
Step 101, forms mask layer in substrate.
Specifically in the way of using chemical gaseous phase deposition, mask layer can be formed in substrate or use the mode of oxidation to form mask layer, such as, substrate be aoxidized, to form oxide layer on the top layer of substrate, using this oxide layer as mask layer.Then this mask layer is carried out photoetching process, forms mask layer.
Step 102, with mask layer as mask, carries out ion implanting, forms the channel region of the JFET of high concentration.
This JFET district is specifically formed in substrate.The ion concentration of the channel region of JFET need to be more than or equal to 9 × 1011Atom/square centimeter.
Step 103, forms oxide layer on the channel region of JFET.
In the way of using oxidation, specifically can form oxide layer on the raceway groove of JFEP.
Step 104, forms grid in oxide layer.
The present embodiment can first deposition of gate material layer on the device that step 103 is formed, then carry out photoetching process or CMP process, only retain the grid of oxide layer.
Step 105, removes mask layer.
Etching technics specifically can be used to remove mask layer.
Step 106, with grid as mask, carries out ion implanting, forms body district.
In this step, with grid as mask, carry out ion implanting in substrate, form body district.
Then, subsequently forming the subsequent techniques such as source region, dielectric layer and metal level, to complete the making of whole VDMOS device, subsequent technique is prior art, does not repeats them here.
In the present embodiment, by being initially formed the channel region of the JFEP of high concentration, then carry out grid and the formation process in body district, it is possible to avoid JFEP is carrying out the photoetching process that high concentration ion needs individually to carry out, and then avoid the increase of production cost.And the mask owing to being used when forming the channel region of JFEP of high concentration can apply to form grid, therefore, can reduce by a photoetching process further, and then save production cost further.
Embodiment two
The manufacture method of the VDMOS device of above-described embodiment is done supplementary notes further by the present embodiment.
As shown in Fig. 2 A to 2G, for the structural representation of each step of the manufacture method of the VDMOS device according to the present embodiment.
As shown in Figure 2 A, substrate 201 forms mask layer 202.
The substrate 201 of the present embodiment includes N-type substrate 2011 and is formed at the N-type epitaxy layer 2012 on N-type substrate 2011.Oxidation 202 can be formed on N-type epitaxy layer 2012 layer by layer by the way of deposition or oxidation.The mask layer 202 of the present embodiment can be specifically silicon nitride, silicon oxide etc..
As shown in Figure 2 B, etching oxidation layer 201 has figuratum mask layer 203 to be formed, and with mask layer 203 as mask, carries out ion implanting, forms the channel region 204 of the JFET of high concentration.
Etching mask layer 202, until exposing substrate 201, i.e. exposes N-type epitaxy layer 2012.Additionally, N-type epitaxy layer 2012 is carried out ion implanting, to form channel region 204.
As shown in Figure 2 C, the channel region 204 of JFET is formed oxide layer 205, mask layer 203 and mask layer 202 form gate material layers 206 by depositional mode.
Such as, use the mode of thermal oxide, channel region 204 is aoxidized, to form oxide layer 205.Specifically, in the way of chemical gaseous phase deposition, forming gate material layers 206 on the surface of the device shown in Fig. 2 C, this gate material layers 206 can be specifically polysilicon.
As shown in Figure 2 D, using chemically mechanical polishing mode to remove the mask layer 203 part higher than the gate material layers 206 on mask layer 202, form grid 207, the top of mask layer 203 flushes with the top of grid 207.
Can be seen that from Fig. 2 D, use chemically mechanical polishing mode not only except the part of the gate material layers 206 in oxide layer 205, i.e. stay is that in oxide layer 205, gate material layers 206, as grid 207, and also been removed the part of the mask layer 203 higher than grid 207.
As shown in Figure 2 E, wet method mode is used to remove mask layer 203.
As shown in Figure 2 F, with grid 207 as mask, carry out ion implanting, form body district 208.
Specifically, N-type epitaxy layer 2012 is carried out p-type ion implanting, and carries out high temperature expulsion technique, to form body district 208.
As shown in Figure 2 G, substrate 201 is carried out ion implanting, the Qie Ti district, both sides 208 of grid 207 is formed source region 209, grid 207 is formed dielectric layer 210, the width of dielectric layer 210, more than the width of grid 207, Bing Ti district 208 and dielectric layer 210 forms metal level 211.
Specifically, first N-type epitaxy layer 2012 is carried out ion implantation technology, form N-type source region 209.Then, using depositing operation to form layer of dielectric material, and layer of dielectric material carries out photoetching process to form dielectric layer 210 on grid 207, dielectric layer 210 need to be completely covered grid 207.Then, body district 208 and dielectric layer 210 form metal level 211 in the way of deposition.
The manufacture method of the VDMOS device according to the present embodiment, both the size of polycrystalline grid can have been reduced, the channel region 204 of denseer JFET, without the problem bringing JFET district too high in resistance, the channel region 204 that can also avoid JFET carries out the photoetching process during ion implanting of high concentration, it is greatly saved cost, thus promotes competitiveness.
One of ordinary skill in the art will appreciate that: all or part of step realizing said method embodiment can be completed by the hardware that programmed instruction is relevant, aforesaid program can be stored in a computer read/write memory medium, this program upon execution, performs to include the step of said method embodiment；And aforesaid storage medium includes: the various media that can store program code such as ROM, RAM, magnetic disc or CDs.
Last it is noted that above example is only in order to illustrate technical scheme, it is not intended to limit；Although the present invention being described in detail with reference to previous embodiment, it will be understood by those within the art that: the technical scheme described in foregoing embodiments still can be modified by it, or wherein portion of techniques feature is carried out equivalent；And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (7)
1. the manufacture method of a VDMOS device, it is characterised in that including:
Substrate is formed mask layer；
With described mask layer as mask, carry out ion implanting, form the channel region of the JFET of high concentration；
The channel region of described JFET is formed oxide layer；
Described oxide layer is formed grid；
Remove described mask layer；
With described grid as mask, carry out ion implanting, form body district.
The manufacture method of VDMOS device the most according to claim 1, it is characterised in that described
Form grid in oxide layer to include:
Described mask layer and described oxide layer form gate material layers by depositional mode；
Chemically mechanical polishing mode is used to remove described mask layer higher than the described grid material in described oxide layer
The part of the bed of material, forms described grid, and the top of described mask layer flushes with the top of described grid.
The manufacture method of VDMOS device the most according to claim 1, it is characterised in that described
Form oxide layer on the channel region of JFET to include:
Thermal oxide mode is used to form described oxide layer on the channel region of described JFET.
The manufacture method of VDMOS device the most according to claim 1, it is characterised in that remove institute
State mask layer to include:
Wet method mode is used to remove described mask layer.
The manufacture method of VDMOS device the most according to claim 1, it is characterised in that described substrate
Including N-type substrate and the N-type epitaxy layer being formed in described N-type substrate.
The manufacture method of VDMOS device the most according to claim 1, it is characterised in that described
Form mask layer in substrate to include:
Formation of deposits mask layer on the substrate；
Etch described mask layer, have figuratum described mask layer to be formed.
The manufacture method of VDMOS device the most according to claim 1, it is characterised in that described
After forming body district, also include:
Described substrate is carried out ion implanting, the both sides of described grid and in described body district formed source region；
Forming dielectric layer on described grid, the width of described dielectric layer is more than the width of described grid；
Described body district and described dielectric layer form described metal level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510278374.4A CN106298892A (en) | 2015-05-27 | 2015-05-27 | The manufacture method of VDMOS device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510278374.4A CN106298892A (en) | 2015-05-27 | 2015-05-27 | The manufacture method of VDMOS device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106298892A true CN106298892A (en) | 2017-01-04 |
Family
ID=57634797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510278374.4A Pending CN106298892A (en) | 2015-05-27 | 2015-05-27 | The manufacture method of VDMOS device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106298892A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6084268A (en) * | 1996-03-05 | 2000-07-04 | Semiconductor Components Industries, Llc | Power MOSFET device having low on-resistance and method |
| CN1244160C (en) * | 2002-03-29 | 2006-03-01 | 株式会社东芝 | Semiconductor devices |
| US20070132020A1 (en) * | 2005-12-14 | 2007-06-14 | De Fresart Edouard D | Superjunction power MOSFET |
| CN102403230A (en) * | 2010-09-17 | 2012-04-04 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device structure |
-
2015
- 2015-05-27 CN CN201510278374.4A patent/CN106298892A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6084268A (en) * | 1996-03-05 | 2000-07-04 | Semiconductor Components Industries, Llc | Power MOSFET device having low on-resistance and method |
| CN1244160C (en) * | 2002-03-29 | 2006-03-01 | 株式会社东芝 | Semiconductor devices |
| US20070132020A1 (en) * | 2005-12-14 | 2007-06-14 | De Fresart Edouard D | Superjunction power MOSFET |
| CN102403230A (en) * | 2010-09-17 | 2012-04-04 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI543301B (en) | Formation of self-aligned source for split-gate non-volatile memory cell | |
| CN103137685B (en) | Semiconductor device and manufacture method thereof | |
| CN104733531A (en) | Dual oxide trench gate power mosfet using oxide filled trench | |
| JP2010135791A (en) | Semiconductor device and method of manufacturing the same | |
| CN104078364A (en) | Method of manufacturing a super-junciton semiconductor device | |
| CN103137686A (en) | Semiconductor device and manufacturing method thereof | |
| CN107004701A (en) | Tunnel field-effect transistor and its manufacture method | |
| CN103413763A (en) | Super junction transistor and forming method thereof | |
| CN104051319B (en) | Semiconductor element and its manufacture method | |
| US10181513B2 (en) | Power device configured to reduce electromagnetic interference (EMI) noise | |
| CN103794610B (en) | Non-volatile memory cell and manufacture method thereof | |
| US20140302645A1 (en) | Methods of forming a field effect transistor, including forming a region providing enhanced oxidation | |
| CN103904117A (en) | Semiconductor device and method for fabricating the same | |
| CN104916539A (en) | Method for producing semiconductor devices | |
| CN104409334A (en) | Method for preparing super junction device | |
| CN102738001A (en) | Method for manufacturing power transistor with super interface | |
| CN106449404A (en) | Semiconductor structure and formation method thereof | |
| JP6538190B2 (en) | Laterally diffused metal oxide semiconductor field effect transistor and method of manufacturing the same | |
| CN106298892A (en) | The manufacture method of VDMOS device | |
| JP5865751B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN105990152A (en) | VDMOS device and manufacturing method thereof | |
| CN106158653B (en) | The production method of plane VDMOS | |
| US20150123195A1 (en) | Recessed channel access transistor device and fabrication method thereof | |
| CN104916540B (en) | A kind of strained channel transistor and preparation method thereof | |
| CN104934471B (en) | Trench power metal-oxide semiconductor field-effect transistor and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170104 |
|
| RJ01 | Rejection of invention patent application after publication |