CN106298781B - Memory device and its manufacturing method - Google Patents
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- CN106298781B CN106298781B CN201510240687.0A CN201510240687A CN106298781B CN 106298781 B CN106298781 B CN 106298781B CN 201510240687 A CN201510240687 A CN 201510240687A CN 106298781 B CN106298781 B CN 106298781B
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Abstract
The present invention provides a kind of memory device and its manufacturing methods, wherein the memory device includes: a substrate；Multiple bit lines extend in parallel in the substrate along a first direction；One first isolation structure and one second isolation structure, extend in the substrate and those bit lines along a second direction；Multiple bottom contact structures, are set between those bit lines along the second direction, and first isolation structure and second isolation structure is made to be set to the two sides of those bottom contact structures in the first direction；And multiple top contact structures, it is set in those bottom contact structures, and the top surface that respectively there is the top contact structure shoulder to be resisted against first isolation structure.
Description
Technical field
The invention relates to memory device and its manufacturing methods, and in particular to contact structures and its manufacturer
Method.
Background technique
With the progress of integrated circuit processing technique, all kinds of electronic components towards high integration, high-speed running and it is micro-
Smallization development.For accessing memory (dynamic random access memories, DRAM) for stochastic and dynamic, due to
Memory capacity increases, and technique is constantly miniature, it is therefore necessary to the capacitance of each storage unit (memory cell) is promoted, and
Preventing capacitor from toppling over contact leads to short-circuit failure, can just meet the growth requirement of the following DRAM.
The technique of DRAM can be divided mainly into plough groove type and two kinds of stack.Wherein, it because technology difficulty is lower, stacks at present
Formula capacitor has been the mainstream for being commercialized DRAM, and successful development goes out various stacking patterns, such as: plate (planner), column
Type (pillar), fin (fin-type) and drum type (cylinder) etc..However, in limited cellar area, stack
Capacitor needs comparable capacitor height to ensure to have enough capacitors to store charge, this additional increased height also results in
The promotion of difficulty in technique, still there are many problem needs to overcome at present.
Summary of the invention
The present invention provides a kind of memory device, comprising: a substrate；Multiple bit lines, along a first direction extend in parallel in
In the substrate；One first isolation structure and one second isolation structure, extend in the substrate and those bit lines along a second direction；
Multiple bottom contact structures, are set between those bit lines along the second direction, make first isolation structure and second isolation
Structure is set to the two sides of those bottom contact structures in the first direction；And multiple top contact structures, it is set to those bottoms and connects
It touches in structure, and the top surface that respectively there is the top contact structure shoulder to be resisted against first isolation structure.
The present invention separately provides a kind of manufacturing method of memory device, comprising the following steps: a substrate is provided, in the substrate
Include: multiple bit lines, is extended in parallel in the substrate along a first direction；One first isolation structure and one second isolation structure,
It is extended in the substrate and those bit lines along a second direction；And multiple bottom contact structures, this is set to along the second direction
Between a little bit lines, first isolation structure and second isolation structure is made to be set to those bottom contact structures in the first direction
Two sides；Compliance forms an etching stopping layer in the substrate；An insulating layer is formed on the etching stopping layer；One is formed to connect
Touching is opened in first isolation structure and the corresponding bottom contact structures, wherein the contact openings exposed portion first isolation
The corresponding bottom contact structures of structure and part；A top contact structure is formed in the contact openings, wherein the top contact structure
The top surface of first isolation structure is resisted against with a shoulder.
Memory device proposed by the present invention and its manufacturing method can be effectively improved asking for leakage current and bit line coupled interference
Topic.
Detailed description of the invention
Fig. 1 depicts a kind of capacitance terminal contact structures.
Fig. 2A -2C, Fig. 3 A-3B, Fig. 4 A-4C, Fig. 5 A-5C, Fig. 6 A-6B, Fig. 7 A-7B are according to one embodiment of the invention
The technique diagrammatic cross-section of contact structures.
Fig. 2 D is the technique schematic top plan view according to the contact structures of one embodiment of the invention.
Fig. 2 E is the technique diagrammatic cross-section according to the contact structures of one embodiment of the invention.
Fig. 8 is the part-structure diagrammatic cross-section according to the memory device of one embodiment of the invention.
Drawing reference numeral explanation:
Substrate~100；
Isolation structure~110；
Bottom contact structures~120,122,310；
Top contact structure~130,710；
Shoulder~132,712；
End~134,714；
Top surface~120S, 310S；
Distance~D；
Substrate~210；
Bit line~220,222,224；
Isolation structure~230,232；
Top surface~230S；
Gate structure~240；
Regions and source/drain~241/242；
Dielectric layer~2201/2401,510；
Grid layer~2202/2402；
Cap rock~2203/2403；
Direction~X, Y；
Upper layer~230A, 232A；
Lower layer~230B, 232B；
Etching stopping layer~410；
Insulating layer~420；
Contact openings~610；
Capacitor~810；
Peripheral contact structure~CS；And
Conductive layer~M0.
Specific embodiment
Illustrate the structure and production of the embodiment of the present invention below.The embodiment of the present invention many suitable concept of the invention are provided and
Various specific backgrounds can be widely implemented on.Revealed specific embodiment, which is merely to illustrate, to be made with ad hoc approach and uses this
Invention, not to limit to the scope of the present invention.
In addition, duplicate reference symbol may be used in various embodiments of the present invention and/or use word.These replicators or use
Word is the relationship being not limited between each embodiment and/or the surface structure in order to simplify with clearly purpose.
Fig. 1 is painted a kind of capacitance terminal contact structures.In stacked storage device, because build stack and IC design, electricity
Container and capacitance terminal contact structures can not be often aligned completely, and be to facilitate capacitor connection capacitance terminal contact structures, common
The practice be that other contact structures are additionally formed between capacitor and capacitance terminal contact structures as connection.Also that is, such as Fig. 1 institute
Show, includes the isolation structure 110 of multiple spaced-apart relations on substrate 100.Capacitance terminal contact structures may include bottom contact structures
120 and top contact structure 130, bottom contact structures 120 are formed between adjacent isolation structure 110, and 130 shape of top contact structure
In the bottom Cheng Yu contact structures 120, wherein top contact structure 130 is to connect capacitor (not being painted) and bottom contact structures 120.
In Fig. 1, top contact structure 130 misses one another with bottom contact structures 120, and wherein top contact structure 130 has shoulder
Portion 132 is resisted against bottom contact structures 120, and the end 134 of top contact structure 130 is lower than the top surface of bottom contact structures 120
120S.However, it is found by the inventors that there are some potential problems for such configuration, and such as: when the forming position of top contact structure 130
When generating offset slightly, contact structures 130 (or end 134 of top contact structure) and another adjacent bottom contact structures are contacted
When 122 distance D is too short, be easy to happen leakage current (cell to cell leakage) or generate bit line coupled interference etc..
Contact structures manufacturing method of the invention is to introduce etching stopping layer in the technique for forming top contact structure, by
The depth and profile of this limitation contact openings etching, so that the top contact structure needed for being formed, may be dived with improving above structure
The problem of.
The manufacturing method of this case contact structures described further below.Fig. 2 D is according in one embodiment of the invention, and storage is single
The technique schematic top plan view of the contact structures in first area；Fig. 2A -2C, Fig. 3 A-3B, Fig. 4 A-4C, Fig. 5 A-5C, Fig. 6 A-6B, Fig. 7 A-
7B is according to the technique diagrammatic cross-section of the contact structures of one embodiment of the invention, and it is transversal in Fig. 2 D that wherein figure number, which is " A " person,
The sectional view of A-A；Figure number is the sectional view that " B " person is transversal B-B in Fig. 2 D；Figure number is that " C " person is cuing open for substrate border area last week
Face schematic diagram.Fig. 2 E is the sectional view of transversal E-E in Fig. 2 D.
As shown in Figure 2 D, the manufacture of contact structures, which starts from, provides substrate 210, and substrate 210 may include memory cell areas and week
Border area (not shown).There is multiple bit lines 220/222/224 and isolation structure 230/232 on the memory cell areas of substrate 210,
In, multiple bit lines 220/222/224 are extended in parallel in substrate 210 in along direction Y spaced-apart relation and along direction X；And it is isolated
Structure 230/232 is then extended in parallel along direction X spaced-apart relation and along direction Y in substrate 210 and bit line 220/222/224
On.More precisely, as shown in Figure 2 E, isolation structure 230/232 is covered on part bit line 220/222/224 and part is inserted
Between bit line 220/222/224.Fig. 2A is the sectional view of transversal A-A in Fig. 2 D, and display is located at the bit line 220/ on substrate 210
222/224；Fig. 2 B is the sectional view of transversal B-B in Fig. 2 D, and display is located at the isolation structure 230/232 on substrate 210；Separately
Outside, as shown in Figure 2 C, there is gate structure 240 and regions and source/drain 241/242 on the peripheral region of substrate 210.
Substrate 210 can be semiconductor base, such as: the elemental semiconductor other than silicon base or wafer or silicon, such as:
Germanium (Ge)；Semiconducting compound, comprising: silicon carbide (SiC), GaAs (GaAs), gallium phosphide (GaP), indium phosphide (InP), arsenic
Change indium (InAs) and/or indium antimonide (InSb)；Semiconducting alloy, comprising: SiGe (SiGe), gallium arsenic phosphide (GaAsP), aluminium indium arsenic
(AlInAs), aluminum gallium arsenide (AlGaAs), GalnAs (GaInAs), gallium indium phosphorus (GaInP) and/or GalnAs phosphorus (GaInAsP)；And
Combinations of the above.Alternatively, substrate can be semiconductor on insulator (semiconductiveor-on-insulator, SOI) base
Bottom, gradient (gradient) substrate, blendes together orientation (hybrid orientation) substrate etc. at multi-layer substrate.This substrate may
It is doped, such as: p-type and N-shaped.
A and Fig. 2 C referring to figure 2. can form bit line 220/222/224 and grid via any existing technology and material
Structure 240.Such as: it can be prior to deposited in sequential dielectric layer 2201/2401, conductive layer 2202/2402 and cap rock in substrate 210
2203/2403, it is then etched to complete bit line and gate stack, is finally formed on the side wall of bit line and gate stack
Clearance wall 2204/2404.
B referring to figure 2. can form isolation structure 230/232 via any existing technology and material, such as: it can be prior to
Deposited oxide layer in substrate, then it is patterned to isolation structure.In an embodiment, as shown in Figure 2 B, isolation structure
It may include upper layer 230A/232A and lower layer 230B/232B.Wherein, the material on upper layer includes spin-on glasses (spin-on
Glass, SOG) material；And the material of lower layer include low temperature oxide (LTO), ultralow temperature oxide (ULTO) or with silicate or
Siloxanes is the oxide that predecessor is formed.
Then A-3B referring to figure 3., in formed in substrate 210 multiple bottom contact structures 310 in bit line 220/222/224 it
Between.Bottom contact structures 310 are set between bit line 220/222/224 along direction Y.Isolation structure 230/232 is then arranged along direction X
In the two sides of bottom contact structures 310, also that is, bottom contact structures 310 are set between bottom contact structures 310 along direction X.Yu Yishi
It applies in example, when in isolation structure 230/232 including upper layer 230A/232A and lower layer 230B/232B, lower layer 230B/232B high
In bottom contact structures 310.It is to be understood that this, which forms the step of bottom contact structures, is not directed to peripheral region, therefore peripheral region
Structure, which does not change, (to be maintained such as Fig. 2 C).
The material of bottom contact structures 310 for example selected from suitable conductive material, may include but be not limited to: doped is more
Crystal silicon (doped polysilicon), aluminium (Al), copper (Cu), tungsten (W), golden (Au), silver-colored (Ag), above-mentioned alloy or above-mentioned gold
Belong to the combination of material.In an embodiment, the material that can first deposit bottom contact structures forms bottom contact structures through etch-back again
310。
Then A-4C referring to figure 4., sequentially in forming etching stopping layer 410 and insulating layer 420 on substrate.In an embodiment
In, first compliance forms etching stopping layer 410 in substrate 210, then blanket forms insulating layer 420 in etching stopping layer 410
On.Therefore, etching stopping layer 410 and insulating layer 420 are sequentially covered in bit line 220/222/224, isolation structure 230/232, bottom
In contact structures 310 and peripheral region.
It should be noted that etching stopping layer 410 can be used as the stop-layer of subsequent, to protect in etching process
Under the isolation structure 230 that covers, and adjustment etching step is formed by the shape of opening whereby, reaches and changes top contact structure configuration
Purpose (being detailed in subsequent discussion).The material of etching stopping layer 410 may include but be not limited to: silicon nitride (SiN), silicon carbide, nitrogen
SiClx carbon (SiCN), silicon oxynitride (SiON), silicon oxide carbide (SiOC) or combinations of the above.The material of insulating layer 420 is, for example,
Advanced low-k materials, it may include but be not limited to: silica (SiO2), Pyrex (BSG), phosphorosilicate glass (PSG), boron phosphorus silicon
Glass (BPSG) or spin-on glasses silica, low temperature oxide (LTO), ultralow temperature oxide or with silicate or siloxanes
The oxide formed for predecessor.
After forming etching stopping layer 410 and insulating layer 420, as shown in Figure 5 C, periphery is formed in the peripheral region on substrate and is connect
Touch structure C S and conductive layer M0.It is to be understood that these steps are not directed to memory cell areas.In an embodiment, periphery is connect
Touch structure C S break-through-etch stop-layer 410 and insulating layer 420 and the regions and source/drain 241/242 for contacting peripheral region.
Peripheral contact structure C S and conductive layer M0 can be formed by different suitable materials, such as: metallic element, metal alloy
Or conductive metallic compound or other conductive materials.For example, the material for forming peripheral contact structure C S and conductive layer M0 can
Including but not limited to: doped polysilicon, aluminium, copper, tungsten, gold, silver, above-mentioned alloy or combination of above-mentioned metal material etc..
Peripheral contact structure C S and conductive layer M0 can be formed via any suitable technique, such as: it can first be etched through etching stopping layer
410 and insulating layer 420 and expose the regions and source/drain 241/242 of peripheral region with formed peripheral contact opening, then deposition lead
Electric layer insert peripheral contact opening in and insulating layer 420 on, finally again patterned conductive layer with formed peripheral contact structure C S and
Conductive layer M0.
In an embodiment, as shown in figures 5a-5c, after forming peripheral contact structure C S and conductive layer M0, Jie can be formed
Electric layer 510 is covered in memory cell areas and peripheral region, wherein dielectric layer 510 is covered on insulating layer 420 and conductive layer M0.Extremely
This, the configuration of peripheral region temporarily comes to an end, and subsequent step is not directed to peripheral region technique, therefore is no longer illustrated in figure.Dielectric
Layer 510 material may include but be not limited to: advanced low-k materials, doping/undoped silicate glass or other commonly use
Material.For example, the material of dielectric layer 510 can be silica, Pyrex, phosphorosilicate glass, boron-phosphorosilicate glass or spin coating
Formula glass.
In Fig. 6 A-6B, contact openings 610 are formed in bit line 220/222, isolation structure 230 and bottom contact structures 310
On, wherein 610 exposed portion isolation structure 230 of contact openings and part bottom contact structures 310.In other words, contact openings 610 reveal
The top surface 230S of the portions of isolation structure 230 and top surface 310S of part bottom contact structures 310 out.It, can in an embodiment
It first carries out the first etching step and removes insulating layer 420, then execute the second etching step and remove etching stopping layer 410, connect with being formed
Touching opening 610.
Above-mentioned first etch process can include: dry-etching；Second etch process can include: dry-etching, wet etching,
Other suitable modes and/or a combination thereof.Wherein, dry-etching may be, for example: plasma etching (plasma etching),
Sputter etching (sputter etching), ion beam milling (ion beam etching) or reactive ion etching
(reactive ion etching,RIE)；Wet etching can for example utilize hydrogen peroxide and sulfuric acid mixture liquid, phosphoric acid, acetic acid and nitre
Sour mixed liquor or other suitable etching solutions are etched.
In Fig. 7 A-7B, top contact structure 710 is formed in contact openings 610.Top can be formed by various suitable materials
Contact structures 710, such as: metallic element, metal alloy or conductive metallic compound or other conductive materials.For example, shape
It may include but be not limited at the material of top contact structure 710: doped polysilicon, aluminium, copper, tungsten, gold, silver, above-mentioned alloy
Or combinations of the above etc..
In an embodiment, barrier can be conformally formed in contact openings 610 before forming contact structures 710
Layer (not shown), to promote the adhesion of conductive layer, and avoids the diffusion of conductive.Formed barrier layer material may include
But it is not limited to: titanium (Ti), zirconium nitride (ZrN), tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN) or combinations of the above.
It should be noted that contact openings 610 can be limited to by the way that etching stopping layer 410 is arranged as shown in Fig. 6 B and Fig. 7 B
Profile and etch depth stop at etching step on the top surface 230S of isolation structure 230, it is ensured that will not be right in etching process
Isolation structure 230 causes overetch, and then forms the configuration of required top contact structure 710.Therefore, as shown in Figure 7 B, this case
The shoulder 712 of the top contact structure 710 is resisted against on the top surface 230S of isolation structure 230, and the end of top contact structure 710
Portion 714 is resisted against on the top surface 310S of bottom contact structures 310.
Fig. 8 is the partial structure diagram according to the memory device of one embodiment of the invention.In Fig. 8, capacitor 810
It is formed on top contact structure 710, wherein top contact structure 710 can be used to connect bottom contact structures 310 and capacitor 810.
Any existing material and technique can be used to form capacitor 810.Such as: capacitor can be formed via etching and deposition technique
810.For example, electricity then can be sequentially deposited in capacitor openings prior to forming capacitor openings in top contact structure 710
Electrode, capacitance dielectric layer and capacitor top electrode are under container to complete the preparation of capacitor 810.Other capacitor techniques can refer to
US 6,137,179 A, US 6,159,820 United States Patent (USP)s or other relevant technical literatures such as A or 6,174,769 B1 of US.
As shown in figure 8, memory device of the present invention comprising: isolation structure 230, bottom contact structures 310, top
Contact structures 710 and capacitor 810, wherein top contact structure 710 is set in isolation structure 230 and bottom contact structures 310,
And the top surface 230S that there is top contact structure 710 shoulder 712 to be resisted against isolation structure 230.Top contact structure 710 is to even
Connect bottom contact structures 310 and the capacitor 810 above top contact structure 710.In an embodiment, top contact structure 710
The top surface 310S of bottom contact structures 310 is resisted against with one end 714.In an embodiment, the end of top contact structure 710
714 are lower than the top surface 310S of bottom contact structures 310.In an embodiment, etching stopping layer 410 is set to bottom contact structures
On 310 portion top surface 310S, and extend over along the side wall of isolation structure 230 to the portion top surface of isolation structure 230
230S.In an embodiment, etching stopping layer 410 is not formed between isolation structure 230 and top contact structure 710.
The present invention limits the profile of contact openings by setting etching stopping layer in the step of etching contact openings, makes
There is the top contact structure being subsequently formed a shoulder to be resisted against the configuration on isolation structure top surface, therefore, even if forming apical grafting
The position of touching structure has and deviates slightly, will not directly influence significantly between top contact structure and adjacent bottom contact structures away from
From, therefore the problem of aforementioned electrical leakage stream and bit line coupled interference can be effectively improved.
Though the present invention is disclosed above in the preferred embodiment, the range that however, it is not to limit the invention, any this field
Technical staff, without departing from the spirit and scope of the present invention, when can do a little change and retouching, therefore protection of the invention
Range is subject to view as defined in claim.
Claims (10)
1. a kind of memory device characterized by comprising
One substrate；
Multiple bit lines are extended in parallel along a first direction in the substrate；
One first isolation structure and one second isolation structure, extend in the substrate and the bit line along a second direction；
Multiple bottom contact structures, are set between the bit line along the second direction, make first isolation structure and institute
State the two sides that the second isolation structure is set to the bottom contact structures in the first direction；
One etching stopping layer is extended over along the side wall of first isolation structure to the part top table of first isolation structure
Face；And
Multiple top contact structures are set in the bottom contact structures, and there is each top contact structure a shoulder to be resisted against
The top surface of first isolation structure.
2. memory device as described in claim 1, which is characterized in that each top contact structure is resisted against with one end
The top surface of the corresponding bottom contact structures.
3. memory device as claimed in claim 2, which is characterized in that the end covering pair of each top contact structure
The portion top surface for the bottom contact structures answered.
4. memory device as described in claim 1, which is characterized in that
The etching stopping layer is more set on the portion top surface of each bottom contact structures.
5. memory device as described in claim 1, which is characterized in that the etching stopping layer is not formed in described first
Between isolation structure and the top contact structure.
6. memory device as described in claim 1, which is characterized in that further include:
One capacitor, be located at the top contact structure on, and the top contact structure to connect the bottom contact structures and
The capacitor.
7. memory device as described in claim 1, which is characterized in that first isolation structure is including a upper layer and once
Layer, and the lower layer is higher than the bottom contact structures.
8. a kind of manufacturing method of memory device, which comprises the following steps:
One substrate is provided, includes: in the substrate
Multiple bit lines are extended in parallel along a first direction in the substrate；
One first isolation structure and one second isolation structure, extend in the substrate and the bit line along a second direction；With
And
Multiple bottom contact structures, are set between the bit line along the second direction, make first isolation structure and institute
State the two sides that the second isolation structure is set to the bottom contact structures in the first direction；
Compliance forms an etching stopping layer and extends over along the side wall of first isolation structure to first isolation structure
Portion top surface；
An insulating layer is formed on the etching stopping layer；
A contact openings are formed on first isolation structure and the corresponding bottom contact structures, wherein the contact openings
The corresponding bottom contact structures of first isolation structure and part described in exposed portion；
A top contact structure is formed in the contact openings, wherein there is the top contact structure shoulder to be resisted against described the
The top surface of one isolation structure.
9. the manufacturing method of memory device as claimed in claim 8, which is characterized in that further include:
A capacitor is formed on the top contact structure.
10. the manufacturing method of memory device as claimed in claim 8, which is characterized in that form the step of the contact openings
Suddenly include:
It executes one first etching step and removes the insulating layer；And
It executes one second etching step and removes the etching stopping layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510240687.0A CN106298781B (en) | 2015-05-13 | 2015-05-13 | Memory device and its manufacturing method |
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| CN201510240687.0A CN106298781B (en) | 2015-05-13 | 2015-05-13 | Memory device and its manufacturing method |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6248636B1 (en) * | 1998-05-28 | 2001-06-19 | Samsung Electronics Co., Ltd. | Method for forming contact holes of semiconductor memory device |
| CN104025263A (en) * | 2011-12-30 | 2014-09-03 | 英特尔公司 | Self-enclosed asymmetric interconnect structures |
-
2015
- 2015-05-13 CN CN201510240687.0A patent/CN106298781B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6248636B1 (en) * | 1998-05-28 | 2001-06-19 | Samsung Electronics Co., Ltd. | Method for forming contact holes of semiconductor memory device |
| CN104025263A (en) * | 2011-12-30 | 2014-09-03 | 英特尔公司 | Self-enclosed asymmetric interconnect structures |
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