CN106298564B - A kind of measurement structure and measurement method, electronic device of FinFET interfacial state - Google Patents
A kind of measurement structure and measurement method, electronic device of FinFET interfacial state Download PDFInfo
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- 238000005259 measurement Methods 0.000 title claims abstract description 41
- 238000000691 measurement method Methods 0.000 title claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 29
- 239000000463 material Substances 0.000 claims description 15
- 125000006850 spacer group Chemical group 0.000 claims description 7
- 229920006395 saturated elastomer Polymers 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 3
- 238000005086 pumping Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 23
- 238000012360 testing method Methods 0.000 abstract description 18
- 238000005516 engineering process Methods 0.000 description 6
- 238000001514 detection method Methods 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 239000003795 chemical substances by application Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000010998 test method Methods 0.000 description 2
- 241000486679 Antitype Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
The present invention relates to a kind of measurement structure of FinFET interfacial state and measurement methods, electronic device.The measurement structure, comprising: well region is located in semiconductor substrate；Fin, positioned at the top of the well region；Gate structure is located above the fin of part and around the fin；Clock is connected with the gate structure；First kind doped region, in the fin that the gate structure side is exposed；Second Type doped region, in the fin that the gate structure other side is exposed；Ammeter is connected between the first kind doped region and the Second Type doped region.Test structure of the present invention can evade (circumvent) described FinFET and contact weak problem with semiconductor substrate, can also measure interfacial state by the method for charge pump.
Description
Technical field
The present invention relates to semiconductor fields, in particular it relates to a kind of measurement structure of FinFET interfacial state
And measurement method, electronic device.
Background technique
With the continuous development of semiconductor technology, in order to improve the performance of device, need constantly to reduce integrated circuit device
Size promote three dimensional design such as FinFET (FinFET) with the continuous diminution of cmos device size
Development.
Relative to existing planar transistor, the FinFET is in the side such as channel control and reduction short-channel effect
Face has more superior performance；Planar gate is set to above the channel, and the grid described in FinFET is surround
The fin setting, therefore electrostatic can be controlled from three faces, the performance in terms of Electrostatic Control is also more prominent.
With the continuous diminution of FinFET, due to the crystal orientation (crystal of the fin side
It orientation), may be comprising more relative to the interface between FinFET and gate dielectric described in planar device
Interfacial state, it is therefore necessary under longtime running state these interfacial states and influence characterize, due to compared with planar device
With weaker substrate contact, the charge pump method (method-Charge pumping) of prior art interface states characterization is simultaneously
It is not suitable for the FinFET.
Further, it is also possible to C-V method is selected to characterize interfacial state, but the accuracy specific capacitance of the test method
Method CP is lower, while needing greater area of Test Constructure of, is not particularly suited for the semiconductor devices.
Therefore it needs to the test structure of current FinFET interfacial state and test method is further is improved, with
Just the above problem is eliminated.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
In order to solve the problems in the existing technology the present invention, provides a kind of measurement knot of FinFET interfacial state
Structure, comprising:
Well region is located in semiconductor substrate；
Fin, positioned at the top of the well region；
Gate structure is located above the fin of part and around the fin；
Clock is connected with the gate structure；
First kind doped region, in the fin that the gate structure side is exposed；
Second Type doped region, in the fin that the gate structure other side is exposed；
Ammeter is connected between the first kind doped region and the Second Type doped region.
Optionally, the measurement structure still further comprises variable condenser, the variable condenser and the ammeter
It is connected in series.
Optionally, the variable condenser is grounded after connecting with the ammeter.
Optionally, the first kind doped region is N+ doped region, and the Second Type doped region is P+ doping
Region.
Optionally, the well region is P type trap zone.
Optionally, the well region is N-type well region.
Optionally, deep n-type well region is also formed further in the lower section of the N-type well region.
Optionally, it is also formed with spacer material layer on the semiconductor substrate, the spacer material layer covers the fin
The bottom of piece.
The present invention also provides a kind of measurement methods based on above-mentioned measurement structure, comprising:
Step S1: applying the pulse power on the gate structure, keeps the channel region of the gate structure anti-from running up to
Type constantly switches, and is saturated pump electric current to generate；
Step S2: the saturation in the step S1 is measured by the ammeter and pumps electric current；
Step S3: electric current is pumped by the saturation in the step S2 and calculates the average surface density of states, with obtained institute
State FinFET interfacial state number.
The present invention also provides a kind of electronic device, the measurement structure including above-mentioned FinFET interfacial state.
In order to solve the problems in the existing technology the present invention, provides a kind of interfacial state of detection FinFET
Gate control diode tests structure, and the test structure measures interfacial state by the method for charge pump.The test structure can be with
For based on NMOS structure, wherein the N+ doped region P+ doped region of the gate structure side replaces, i.e., the described test structure
N+ and P+ doped region or the test structure for the P- substrate in the NMOS, and positioned at gate structure two sides are
The PMOS structure, including N- substrate, and N+ the and P+ doped region positioned at gate structure two sides, still further comprise and are located at
Deep N-well (DNW IMP) between well region and substrate.
Test structure of the present invention can evade (circumvent) described FinFET and contact with semiconductor substrate
Weak problem can also measure interfacial state by the method for charge pump.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, device used to explain the present invention and principle.In the accompanying drawings,
Fig. 1 is the interfacial state detection structure schematic diagram of FinFET described in embodiments of the present invention；
Fig. 2 is the interfacial state detection structure sectional view of FinFET described in embodiments of the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that spatial relation term intention further includes making other than orientation shown in figure
With the different orientation with the device in operation.For example, then, being described as " under other elements if the device in attached drawing is overturn
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
Embodiment 1
In order to solve the problems in the existing technology the present invention, provides a kind of measurement knot of FinFET interfacial state
Structure, the measurement structure solve the drawbacks of existing measurement structure cannot be measured by charge pump, can pass through measurement charge pump
Method measures the FinFET interfacial state, can be improved measurement accuracy, and the measurement structure is as illustrated in fig. 1 and 2, wherein
Fig. 1 is the interfacial state detection structure schematic diagram of FinFET described in embodiments of the present invention；Fig. 2 is implementation of the invention
The interfacial state detection structure sectional view of FinFET described in mode.
As illustrated in fig. 1 and 2, the measurement structure includes:
Semiconductor substrate；
Well region 101 is located in the semiconductor substrate；
Fin 103 is located above the well region；
Gate structure 104 is located at 103 top of fin and is arranged around the fin；
Clock is connected with the gate structure；
First kind doped region 1031, in the fin of the gate structure side；
Second Type doped region 1032, in the fin of the gate structure other side；
Ammeter, the ammeter both ends are connected to the first kind doped region and the Second Type doped region
Domain.
In a specific embodiment of the invention, the measurement structure is based on NMOS structure, wherein the semiconductor lining
Bottom 101 can be following at least one of the material being previously mentioned: silicon is laminated on insulator in silicon, silicon-on-insulator (SOI)
(SSOI), SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator are laminated on insulator
(GeOI) etc..
Optionally, the semiconductor substrate is N-type semiconductor substrate, and forms p-well in the N-type semiconductor substrate,
Such as p type impurity is lightly doped in the semiconductor substrate, such as B, Ga, to spread p type island region in N-type substrate, form the P
Well region.Wherein, the ion injection method, energy, dosage can select method commonly used in the art, and details are not described herein.
Wherein, the fin 103 is located in the p-well, and specific forming method includes: that hard mask layer is formed in p-well
(not shown) forms the various suitable techniques that the hard mask layer can be familiar with using those skilled in the art, example
Such as chemical vapor deposition process, the hard mask layer can be the oxide skin(coating) and silicon nitride layer being laminated from bottom to top；Patterning
The hard mask layer forms multiple exposure masks being isolated from each other that fin is formed on for etching semiconductor substrate 101,
In one embodiment, using patterning process described in self-aligned double patterning case (SADP) process implementing；P-well is etched to be formed on
Fin structure.
Optionally, spacer material layer 102 is also formed in the p-well, the spacer material layer fills the fin week
The gap and part enclosed cover the bottom of the fin 103, to form the fin of object height.
Specifically, the forming method of the depositing isolation material layer 102 may include: depositing isolation material layer 102, with complete
Gap between full packing fin structure.In one embodiment, real using the chemical vapor deposition process with flowability
Apply the deposition.The material of spacer material layer 102 can choose oxide, such as HARP.Then isolated material described in etch-back
Layer 102, until the object height of the fin.Specifically, spacer material layer 102 described in etch-back, with fin described in exposed portion,
And then form the fin with certain height.
Wherein, the gate structure 104 is all around gate, is arranged around the fin, as shown in Figure 1, institute in the longitudinal direction
It states gate structure 104 to surround and the fin is completely covered, horizontally, the two of fin are still exposed in the two sides of the gate structure
End.
Wherein, the gate structure can select semiconductor material commonly used in the art, such as polysilicon can be selected etc.,
It is not limited to a certain kind, will not enumerate herein.
First kind doped region 1031 and Second Type doped region are also formed in the two sides of the gate structure
1032.Wherein, the first kind doped region 1031 is N+ doped region, and the Second Type doped region 1032 is mixed for P+
Miscellaneous region.
Wherein, in order to be suitable for measuring the interfacial state of FinFET, the accuracy of measurement result is improved, by institute in the application
The source-drain area for stating the N-type of gate structure two sides is changed, by the wherein ion doping type of gate structure side change
For p-type, to be used to replace semiconductor substrate (body area), as shown in Figure 2.
In addition, the measurement structure still further comprises variable condenser, the variable condenser and the ammeter phase
Series connection is connected to the first kind doped region and the Second Type doped region after series connection.
Further, the other end ground connection after the variable condenser is connected with the ammeter.
The working principle of the measurement structure are as follows: in the measurement structure, on the gate structure 104 of the MOSFET
Apply pulse, high level Vgh is greater than the threshold voltage vt h of MOSFET, and low level Vgl is lower than its flat-band voltage Vfb.Pulse
Rise time tr, fall time tf are respectively less than the time constant of interfacial state transmitting.The channel during grid voltage is located at pulse high level
Surface is in anti-type state, and electronics flows to channel from source and drain, and a portion is captured by interfacial state.When grid voltage becomes low level
When, channel will become accumulated state, and channel movable electronic flows back to first kind doped region 1031, still, since tr, tf are small
In interfacial state launch time constant, those electronics captured by interfacial state, especially those are positioned at compared in deep energy level interfacial state
Electronics, will have little time to be transmitted back to conduction band, and the hole-recombination with Second Type doped region 1032.Similarly, in grid voltage by low
Level to when high level transition, have little time to be transmitted back in interfacial state the hole of valence band by with first kind doped region 1031
Electronics is compound.Therefore it from the point of view of whole cycle, is equivalent to and produces one first kind is flowed to by Second Type doped region 1032
The electric current of type doped region 1031 (to PMOS, then current direction is opposite).This electric current is known as saturated charge pump electric current Icp。
Wherein, Icp=qAGfDit, wherein the q is electron charge, the AGFor gate structure area, f is pulse frequency
Rate, DitFor the average surface density of states, the I can be seen that by the formulacpAnd DitIt is proportional, therefore charge pump current is straight
Connect the quantity for reflecting channel interface state.
In order to solve the problems in the existing technology the present invention, provides a kind of interfacial state grid for detecting FinFET
Test Diode structure is controlled, the test structure measures interfacial state by the method for charge pump.The test structure can be
Based on NMOS structure, wherein the N+ doped region P+ doped region of the gate structure side replaces, i.e., the described test structure is
P- substrate in the NMOS, and N+ and P+ doped region positioned at gate structure two sides or the test structure are institute
PMOS structure is stated, the N- substrate including in, and N+ the and P+ doped region positioned at gate structure two sides, still further comprise position
Deep N-well (DNW IMP) between well region and substrate.
Test structure of the present invention can evade (circumvent) described FinFET and contact with semiconductor substrate
Weak problem can also measure interfacial state by the method for charge pump.
Embodiment 2
In order to solve the problems in the existing technology the present invention, provides a kind of measurement knot of FinFET interfacial state
Structure, the measurement structure solve the drawbacks of existing measurement structure cannot be measured by charge pump, can pass through measurement charge pump
Method measures the FinFET interfacial state, and measurement accuracy can be improved.
The measurement structure includes:
Semiconductor substrate；
Well region is located in the semiconductor substrate；
Fin is located above the well region；
Gate structure is located above the fin and is arranged around the fin；
Clock is connected with the gate structure；
First kind doped region, in the fin of the gate structure side；
Second Type doped region, in the fin of the gate structure other side；
Ammeter, the ammeter both ends are connected to the first kind doped region and the Second Type doped region
Domain.
In a specific embodiment of the invention, the measurement structure is based on PMOS structure, and the semiconductor substrate is p-type
Semiconductor substrate, and N trap is formed in the P-type semiconductor substrate, such as lightly doped n type is miscellaneous in the semiconductor substrate
Matter, such as P, As form the N well region to spread N-type region in P type substrate.
Wherein, the ion injection method, energy, dosage can select method commonly used in the art, and details are not described herein.
Wherein, the source and drain of the gate structure two sides is P+ doping, will wherein one in order to be suitable for the FinFET
A source-drain area is adulterated by N+ and is replaced, to be used to replace semiconductor substrate (body area).
Unlike embodiment 1, deep N is also formed further with below the N well region in the semiconductor substrate
Well region, in addition to this other settings and implementation 1 are identical, are not repeated to describe herein.
The working principle of the measurement structure is identical with embodiment 1 in this embodiment, in addition to saturated charge pumps electric current Icp
Current direction, it is opposite with the current direction in embodiment 1 to PMOS current direction.But still meet following formula: Icp=
qAGfDit, wherein the q is electron charge, the AGFor gate structure area, f is pulse frequency, DitIt is close for average surface state
Degree, can be seen that the I by the formulacpAnd DitIt is proportional, therefore charge pump current directly reflects channel interface state
Quantity.
Embodiment 3
The present invention also provides a kind of measurement method of FinFET interfacial state, the measurement method selects embodiment 1
Or measurement structure as described in example 2, the measurement method include:
Step S1: applying a pulse on the gate structure, keeps the channel region of the gate structure anti-from running up to
Type constantly changes；
Step S2: electric current I is pumped by the saturation generated in the ammeter measuring process S1cp；Wherein, Icp=qAGfDit,
Wherein, the q is electron charge, the AGFor gate structure area, f is pulse frequency, DitFor the average surface density of states, by this
Formula can be seen that the IcpAnd DitIt is proportional, therefore charge pump current directly reflects the quantity of channel interface state.
Step S3: electric current is pumped by the saturation in step S2 and calculates the average surface density of states, described in obtaining
FinFET interfacial state number.
Embodiment 4
The present invention also provides a kind of electronic devices, including test structure described in embodiment 1 or 2.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment can also be
Any intermediate products including the test structure.The electronic device of the embodiment of the present invention, due to having used above-mentioned test knot
Structure, thus there is better performance.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
1. a kind of measurement structure of FinFET interfacial state, comprising:
Well region is located in semiconductor substrate；
Fin, positioned at the top of the well region；
Gate structure is located above the fin of part and around the fin；
Clock is connected with the gate structure；
First kind doped region, in the fin that the gate structure side is exposed；
Second Type doped region, in the fin that the gate structure other side is exposed；
Ammeter is connected between the first kind doped region and the Second Type doped region.
2. measurement structure according to claim 1, which is characterized in that the measurement structure still further comprises variable capacitance
Device, the variable condenser are connected in series with the ammeter.
3. measurement structure according to claim 2, which is characterized in that after the variable condenser is connected with the ammeter
Ground connection.
4. measurement structure according to claim 1, which is characterized in that the first kind doped region is N+ doped region
Domain, the Second Type doped region are P+ doped region.
5. measurement structure according to claim 1 or 4, which is characterized in that the well region is P type trap zone.
6. measurement structure according to claim 1 or 4, which is characterized in that the well region is N-type well region.
7. measurement structure according to claim 6, which is characterized in that be also further formed in the lower section of the N-type well region
There is deep n-type well region.
8. measurement structure according to claim 1, which is characterized in that be also formed with isolation material on the semiconductor substrate
The bed of material, the spacer material layer cover the bottom of the fin.
9. a kind of measurement method of the measurement structure based on one of claim 1 to 8, comprising:
Step S1: applying the pulse power on the gate structure, makes the channel region of the gate structure from running up to transoid not
Disconnected switching is saturated pump electric current to generate；
Step S2: the saturation in the step S1 is measured by the ammeter and pumps electric current；
Step S3: pumping electric current by the saturation in the step S2 and calculate the average surface density of states, described to obtain
The interfacial state number of FinFET.
10. a kind of electronic device, the measurement structure including FinFET interfacial state described in one of claim 1 to 8.
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| CN109300878B (en) * | 2018-09-11 | 2020-04-10 | 长江存储科技有限责任公司 | Forming method of interface defect characterization structure |
| CN108922857B (en) * | 2018-09-11 | 2023-12-08 | 长江存储科技有限责任公司 | Interface defect characterization structure and interface defect detection device |
| CN111584637B (en) * | 2020-05-28 | 2023-11-14 | 上海华力集成电路制造有限公司 | PIN structure based on FDSOI and manufacturing method thereof |
| CN113964202B (en) * | 2021-10-14 | 2023-01-24 | 上海集成电路制造创新中心有限公司 | Test method and system for gate-all-around device preparation |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101136347A (en) * | 2007-09-29 | 2008-03-05 | 上海集成电路研发中心有限公司 | MOS pipe interface state testing method |
| CN102163568A (en) * | 2011-03-07 | 2011-08-24 | 北京大学 | Method for extracting charge distribution of metal oxide semiconductor (MOS) tube along channel |
| US8039394B2 (en) * | 2009-06-26 | 2011-10-18 | Seagate Technology Llc | Methods of forming layers of alpha-tantalum |
| CN102621473A (en) * | 2012-04-13 | 2012-08-01 | 北京大学 | Test method generated by monitoring negative bias temperature instability (NBTI) effect interface states in real time |
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| CN101136347A (en) * | 2007-09-29 | 2008-03-05 | 上海集成电路研发中心有限公司 | MOS pipe interface state testing method |
| US8039394B2 (en) * | 2009-06-26 | 2011-10-18 | Seagate Technology Llc | Methods of forming layers of alpha-tantalum |
| CN102163568A (en) * | 2011-03-07 | 2011-08-24 | 北京大学 | Method for extracting charge distribution of metal oxide semiconductor (MOS) tube along channel |
| CN102621473A (en) * | 2012-04-13 | 2012-08-01 | 北京大学 | Test method generated by monitoring negative bias temperature instability (NBTI) effect interface states in real time |
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