CN106298539B - Method for manufacturing transistor - Google Patents
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- CN106298539B CN106298539B CN201510366383.9A CN201510366383A CN106298539B CN 106298539 B CN106298539 B CN 106298539B CN 201510366383 A CN201510366383 A CN 201510366383A CN 106298539 B CN106298539 B CN 106298539B
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
Abstract
A method of manufacturing a transistor, comprising: forming a substrate, wherein dummy gates and interlayer dielectric layers positioned between the dummy gates are formed in the substrate; removing the pseudo gate, and forming a groove at the original position of the pseudo gate; cleaning the substrate with a cleaning gas after forming the grooves, the cleaning gas comprising NF3(ii) a And filling a conductive material into the groove after cleaning is finished to form a grid. The invention adopts the structure that NF is included after the pseudo gate and the protective layer are removed3The cleaning gas of (a) cleans the substrate. Compared with the common CF in the prior art4By contrast, NF3The cleaning gas contains lower F content, so that the interlayer dielectric layer can be effectively prevented from being excessively etched in the pseudo gate removing process, the residual of the subsequently filled conductive material on the surface of the interlayer dielectric layer is avoided, the yield of the semiconductor device is improved, and the manufacturing cost of the device is reduced.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a manufacturing method of a transistor.
Background
With the continuous development of integrated circuit manufacturing technology, the feature size of the MOS transistor is smaller and smaller, and in order to reduce the parasitic capacitance of the gate of the MOS transistor and increase the device speed, a gate structure of a high-K gate dielectric layer and a metal gate is introduced into the MOS transistor.
The Gate-Last (Gate-Last) process is widely used in the manufacturing process of high-K Gate dielectric layers and metal Gate electrodes. Compared with the front Gate (Gate-First) process, the device manufactured by the back Gate process can avoid the influence of annealing of a source region or a drain region on other structures of the transistor. Therefore, the stability of the device manufactured by adopting the gate-last process is higher.
Referring to fig. 1-3, there are shown schematic diagrams of steps of a method of manufacturing a transistor in a prior art process.
Referring to fig. 1, a substrate 10 is formed, a dummy gate 12 and an interlayer dielectric layer 13 are formed in the substrate 10, the interlayer dielectric layer 13 is flush with the dummy gate 12, and a protective layer 14 is formed on the interlayer dielectric layer 13.
Referring to fig. 2, the dummy gate 12 and the protective layer 14 are sequentially removed to form a groove 15.
Referring to fig. 3, a conductive material is filled into the groove 15 to form a gate electrode 20.
However, in the transistor formed by the prior art, the interlayer dielectric layer 13 is easily removed excessively, so that the conductive material is remained on the surface of the interlayer dielectric layer 13.
Disclosure of Invention
The invention provides a manufacturing method of a transistor, which can reduce excessive removal of an interlayer dielectric layer in a dummy gate removal process.
In order to solve the above problems, the present invention provides a method for manufacturing a transistor, including:
forming a substrate, wherein dummy gates and interlayer dielectric layers positioned between the dummy gates are formed in the substrate;
removing the pseudo gate, and forming a groove at the original position of the pseudo gate;
cleaning the substrate with a cleaning gas after forming the grooves, the cleaning gas comprising NF3；
And filling a conductive material into the groove after cleaning is finished to form a grid.
Optionally, the step of cleaning the substrate with a cleaning gas comprises: the NF3The flow rate of the gas is 10-50 sccm.
Optionally, the step of cleaning the substrate with a cleaning gas comprises: in the presence of NF3Argon or helium is also introduced in the process of (2).
Optionally, the flow rate of the argon or helium is 50-300 sccm.
Optionally, the step of cleaning the substrate with a cleaning gas comprises: and cleaning by adopting a synchronous pulse plasma mode.
Optionally, the pulse frequency of the synchronously pulsed plasma is in the range of 5KHz to 20 KHz.
Optionally, the pulse duty cycle of the synchronously pulsed plasma is in the range of 30% to 75%.
Optionally, the material of the dummy gate is amorphous silicon.
Optionally, the interlayer dielectric layer is made of silicon oxide.
Optionally, the step of forming the substrate comprises: providing a substrate; forming a dummy gate on the substrate; forming an interlayer dielectric layer on the substrate between the dummy gates; and covering a protective layer on the surface of the interlayer dielectric layer.
Optionally, the step of covering a protective layer on the surface of the interlayer dielectric layer includes: the protective layer is made of photoresist.
Optionally, the step of removing the dummy gate includes: etching by taking the protective layer and the interlayer dielectric layer as masks to remove the pseudo gate; and removing the protective layer.
Optionally, the step of removing the dummy gate and the protection layer includes: and removing the pseudo gate and the protective layer by adopting a dry etching process.
Optionally, the step of removing the dummy gate by using a dry etching process includes: the etching gas comprises helium, oxygen and hydrogen bromide gas.
Optionally, the step of removing the protective layer includes: the etching gas comprises nitrogen.
Optionally, after the step of cleaning the substrate with the cleaning gas and before the step of filling the conductive material into the groove, the manufacturing method further includes: and cleaning the substrate by adopting an ashing or wet process.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the invention adopts the structure that NF is included after the pseudo gate and the protective layer are removed3The cleaning gas of (a) cleans the substrate. Compared with the common CF in the prior art4By contrast, NF3The cleaning gas contains lower F content, so that the interlayer dielectric layer can be effectively prevented from being excessively etched in the pseudo gate removing process, and the residual of the subsequently filled conductive material on the surface of the interlayer dielectric layer is avoidedThe yield of the semiconductor device is improved, and the manufacturing cost of the device is reduced.
Optionally, in an alternative of the present invention, after the step of dry cleaning the substrate with the cleaning gas, the substrate is further cleaned with ashing or a wet process. NF3The residual protective layer can be effectively removed by the N in the protective layer, and the F remained on the surface of the protective layer can be reduced, so that the removal of the interlayer dielectric layer caused by the F remained on the surface of the protective layer in the ashing or wet process is avoided, and the loss of the interlayer dielectric layer can be further reduced.
Optionally, in an alternative of the present invention, the cleaning gas is a synchronously pulsed plasma gas, that is, the cleaning gas is input in a synchronously pulsed manner. The synchronous pulse type input of the cleaning gas can ensure that the cleaning gas obtains sufficient relaxation time and can ensure that the cleaning gas fully reacts with residues on the substrate, thereby ensuring that the cleaning is more thorough and uniform.
Drawings
FIGS. 1-4 are schematic diagrams of steps in a method of fabricating a transistor in a prior art process;
fig. 5 to 9 are schematic structural diagrams of steps of a transistor manufacturing method according to an embodiment of the present invention.
Detailed Description
As can be seen from the background art, the prior art transistor manufacturing method is prone to the problem of over-etching the interlayer dielectric layer. The reason for the problem of the excessive etching of the interlayer dielectric layer is analyzed by combining the manufacturing process of the transistor in the prior art:
referring to fig. 1 to 3, in the process of manufacturing a transistor in the prior art, during the process of removing the dummy gate 12 and the protective layer 14, a residue is often formed on the surface of the interlayer dielectric layer 13, and in order to improve the performance of the manufactured transistor, after the step of removing the dummy gate 12 and the protective layer 14, before the step of filling a conductive material to form the gate 20, a process including CF is often adopted4The Post Etch Treatment (PET) is performed on the etched substrate. But due to CF4In (A) containsThe fluorine content is high, so that fluorine is easy to remain on the substrate surface, and the interlayer dielectric layer 13 is easy to be excessively removed in the post-etching treatment process.
As shown in fig. 4, in the prior art, the interlayer dielectric layer 13 is excessively removed in the cleaning process of the post-etching treatment, and a step-like structure is easily formed on the surface of the interlayer dielectric layer 13. After the gate 20 is formed by filling the conductive material, a thicker conductive material residue (as shown in a circle 21 in fig. 4) is easily formed on the surface of the interlayer dielectric layer 13, thereby affecting the electrical isolation performance of the interlayer dielectric layer 13, further affecting the performance of the manufactured transistor, and reducing the manufacturing yield of the device.
In addition, after the gate electrode is formed by filling the conductive material, a chemical mechanical polishing process is performed to planarize the gate electrode. The thicker conductive material residue also limits the process window for chemical mechanical polishing because a sufficient amount of Over Polish (Over Polish) is required to remove the conductive material residue, which limits the lower limit of chemical mechanical polishing.
In order to solve the technical problem, the invention provides a method for manufacturing a transistor, which comprises the following steps:
forming a substrate, wherein dummy gates and interlayer dielectric layers positioned between the dummy gates are formed in the substrate; removing the pseudo gate, and forming a groove at the original position of the pseudo gate; cleaning the substrate with a cleaning gas after forming the grooves, the cleaning gas comprising NF3(ii) a And filling a conductive material into the groove after cleaning is finished to form a grid.
The invention adopts the structure that NF is included after the pseudo gate and the protective layer are removed3The cleaning gas of (a) cleans the substrate. Compared with the common CF in the prior art4By contrast, NF3The cleaning gas contains lower F content, so that the interlayer dielectric layer can be effectively prevented from being excessively etched in the pseudo gate removing process, the residual of the subsequently filled conductive material on the surface of the interlayer dielectric layer is avoided, the yield of the semiconductor device is improved, and the manufacturing cost of the device is reduced.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 5 to 9, schematic structural diagrams of steps of an embodiment of a method for manufacturing a transistor according to the present invention are shown.
Referring to fig. 5, a substrate 100 is formed, and dummy gates 120 and an interlayer dielectric layer 130 between the dummy gates 120 are formed in the substrate 100.
Specifically, in this embodiment, the interlayer dielectric layer 130 is flush with the top of the dummy gate 120, and a protective layer 140 is further formed on the surface of the interlayer dielectric layer 130.
Therefore, in the present embodiment, the step of forming the substrate 100 includes:
providing a substrate 110;
forming a dummy gate 120 on the substrate 110;
forming an interlayer dielectric layer 130 on the substrate 110 between the dummy gates 120;
a protective layer 140 is formed on the interlayer dielectric layer 130.
The substrate 110 is a working platform for a subsequent semiconductor process. The material of the substrate 110 is selected from monocrystalline silicon, polycrystalline silicon or amorphous silicon; the substrate 110 may also be selected from silicon, germanium, gallium arsenide, or silicon germanium compounds; the substrate 110 may also have an epitaxial layer or a silicon-on-epitaxial layer structure; the substrate 110 may also be other semiconductor materials, which is not limited in this respect.
The dummy gate 120 is removed in a subsequent process, and a gate electrode is formed in situ on the dummy gate. The subsequent process of removing the dummy gate 120 and forming the gate again can avoid the influence of the process steps in the manufacturing process on other structures of the transistor. Specifically, in this embodiment, the material of the dummy gate 120 is amorphous silicon.
Specifically, the step of forming the dummy gate 120 includes: a dummy gate material layer is formed on the substrate 110 and then etched to form a dummy gate 120.
It should be noted that the step of etching the dummy gate material layer to form the dummy gate 120 includes forming a patterned photoresist on the dummy gate material layer, and etching the dummy gate material layer by using a dry process with the patterned photoresist as a mask to form the dummy gate 120.
After the etching is completed, a dummy gate 120 exposing the substrate 110 is formed.
The interlayer dielectric layer 130 is used to achieve electrical isolation between devices. In this embodiment, the interlayer dielectric layer 130 is made of silicon oxide. In addition, the interlayer dielectric layer 130 may also be a low-K dielectric material or an ultra-low-K dielectric material, such as doped silicon oxide or an organic polymer, which is not limited in the present invention. Specifically, the interlayer dielectric layer 130 may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or a furnace tube, which is not limited in the present invention.
The protection layer 140 is used to protect the interlayer dielectric layer 130 from being affected during the subsequent process of removing the dummy gate 120. Specifically, in this embodiment, the protection layer 140 is a photoresist, and the protection layer 140 may be formed on the interlayer dielectric layer 130 by a photoresist spin coating process.
In this embodiment, after the step of forming the interlayer dielectric layer 130 on the substrate 110 between the dummy gates 120 and before the step of forming the protective layer 140 on the interlayer dielectric layer 130, the manufacturing method further includes: and (3) leveling the surface of the interlayer dielectric layer 130 and the surface of the dummy gate 120 by adopting a chemical mechanical polishing method.
Referring to fig. 6 and 7, the dummy gate 120 is removed, and a recess 150 is formed at the original position of the dummy gate 120.
Specifically, the dummy gate 120 is removed by a dry etching process.
In this embodiment, a protection layer 140 is further formed on the surface of the interlayer dielectric layer 130. Accordingly, the step of removing the dummy gate 120 includes:
etching by taking the protective layer 140 and the interlayer dielectric layer 130 as masks to remove the dummy gate 120;
thereafter, the protective layer 140 is removed.
Specifically, referring to fig. 6, the protection layer 140 and the interlayer dielectric layer 130 are used as masks to perform etching, the dummy gate 120 is removed, and a groove 150 exposing the substrate 110 is formed in situ of the dummy gate 120.
Specifically, in this embodiment, a dry etching process is used to remove the dummy gate 120 to obtain the recess 150 with a higher vertical sidewall. The etching gas adopted in the dry etching process comprises helium, oxygen and hydrogen bromide gas.
The hydrogen bromide is used as main etching gas, and can perform chemical reaction with the dummy gate 120 made of amorphous silicon material in a plasma state, so that the dummy gate 120 is etched and removed; argon is used for vertically bombarding the surface of the pseudo gate 120 to achieve the purpose of anisotropic etching; in addition, oxygen introduced during the dry etching process may form a polymer 160 with silicon and hydrogen bromide, which adheres to the sidewall of the recess 150, so as to improve the anisotropic ability of the etching process for removing the dummy gate 120.
Referring to fig. 7 in combination, after the dummy gate 120 is removed, the protection layer 140 is removed.
Specifically, in this embodiment, the protective layer 140 is removed by a dry etching method. Specifically, the etching gas used in the dry etching process contains nitrogen.
It should be noted that, in the process of removing the protection layer 140, in addition to the need of removing the protection layer 140, the polymer 170 generated in the process of cleaning is also needed, since the polymer 170 may include silicon. Therefore, the balance between the polymer 170 and the etching gas can be effectively maintained by using nitrogen gas during the process of removing the protective layer 140, so that the polymer 170 can be cleaned.
Referring collectively to FIG. 8, after forming the grooves 150, the substrate 100 is cleaned using a cleaning gas 300 comprising NF3。
Specifically, in order to further remove the residues 170 generated in the process, after the step of removing the dummy gate 120 and the protection layer 140 and before the step of forming the gate electrode, the substrate 100 from which the dummy gate 120 and the protection layer 140 are removed needs to be subjected to post-etching treatment to obtain a cleaner substrate 100, so as to improve the performance of the formed device and the yield of the manufactured device.
In this embodiment, the substrate is post-etched with a cleaning gas 300 comprising NF3。
Compared with the common CF in the prior art4By contrast, NF3The content of fluorine in the dielectric layer is low, so that the loss of the interlayer dielectric layer 130 can be effectively reduced in the etching post-treatment process, the interlayer dielectric layer 130 is prevented from being excessively removed, the conductive material is prevented from remaining on the surface of the interlayer dielectric layer 130 after the gate is formed, and the yield of the manufactured transistor is improved.
Furthermore, NF3The N in (b) can more thoroughly remove the residue 170 to prevent the interlayer dielectric layer 130 from being removed by fluorine ions adsorbed on the surface of the residue 170 in the subsequent process, which is also beneficial to preventing the interlayer dielectric layer 130 from being excessively removed in the subsequent process. Specifically, after the step of performing the post-etching treatment on the substrate 100, in this embodiment, the manufacturing method further includes performing more thorough cleaning on the substrate 100 by using an ashing or a wet process. The fluorine ions in the cleaning gas 300 are more easily adsorbed on the surface of the residue 170, and when the subsequent wet cleaning process is performed, the fluorine ions adsorbed on the surface of the residue 170 are easily reacted with water vapor to form HF. HF is corrosive to interlayer dielectric layer 130, which may cause interlayer dielectric layer 130 to be removed in a subsequent more thorough cleaning process, resulting in excessive removal of interlayer dielectric layer 130. Thus, NF was used3The residue 160 is removed more thoroughly, so that the loss of the interlayer dielectric layer 130 can be reduced, and the manufacturing yield of the device can be improved.
In particular, the NF3The flow rate of the gas is 10-50 sccm, and the smaller NF3The gas flow rate enables the cleaning gas to react completely with the residue to improve the cleaning effect and the transistor performance.
In this embodiment, the step of cleaning the substrate 100 with the cleaning gas 300 further includes: the substrate 100 is cleaned by using a synchronized pulsed plasma (synchronized pulsed plasma). Specifically, during the cleaning of the substrate 100 using the cleaning gas 300, the source voltage and the bias voltage are simultaneously stopped to form a pulsed plasma. The advantage of using the synchronized pulsed plasma to perform post-etch processing on the etched substrate 100 is that when the source voltage and the bias voltage are both stopped, electrons and neutrons in the cleaning gas 300 can be fully relaxed, so that the cleaning gas 300 and the residue 160 react more fully, thereby improving the uniformity of post-etch processing and improving the cleaning effect of post-etch processing.
Specifically, the pulse frequency (pulse frequency) of the synchronous pulse plasma is in a range of 5KHz to 20KHz, and the pulse duty cycle (pulse duty cycle) is in a range of 30% to 75%. However, the pulse frequency and the pulse duty ratio of the synchronously pulsed plasma can be adjusted according to the actual situation of the manufacturing process to obtain better processing effect, which is not limited by the present invention.
It should be noted that, in this embodiment, the cleaning gas 300 may further include argon or helium. The addition of argon or helium can bombard the residue 170 to improve the cleaning effect of the post-etch treatment. Specifically, the flow rate of the argon or helium is 50-300 sccm.
Referring next to fig. 9, after cleaning is completed, the recess 150 is filled with a conductive material to form a gate electrode 200.
In this embodiment, after the step of cleaning the substrate 100 with the cleaning gas and before the step of filling the conductive material into the groove 150 to form the gate 200, the manufacturing method further includes: the substrate 100 is cleaned using an ashing or wet process.
The substrate 100 is further cleaned by ashing or wet process, so that residues on the substrate 100 in the etching process and the cleaning process can be further removed, the performance of the manufactured transistor is further improved, and the manufacturing yield of the device is improved.
In this embodiment, the conductive material may be a metal material, including one or more of aluminum, copper, silver, gold, platinum, nickel, titanium nitride, thallium carbide, thallium silicide nitride, tungsten nitride, and tungsten silicide. The method for forming the gate 200 is well known to those skilled in the art and will not be described in detail herein.
In summary, the invention adopts the structure including NF after removing the dummy gate and the protective layer3The cleaning gas of (a) cleans the substrate. Compared with the common CF in the prior art4By contrast, NF3The cleaning gas contains lower F content, so that the interlayer dielectric layer can be effectively prevented from being excessively etched in the pseudo gate removing process, the residual of the subsequently filled conductive material on the surface of the interlayer dielectric layer is avoided, the yield of the semiconductor device is improved, and the manufacturing cost of the device is reduced. In addition, in an alternative aspect of the present invention, after the step of dry cleaning the substrate using the cleaning gas, the substrate is further cleaned using ashing or a wet process. NF3The residual protective layer can be effectively removed by the N in the protective layer, and the F remained on the surface of the protective layer can be reduced, so that the removal of the interlayer dielectric layer caused by the F remained on the surface of the protective layer in the ashing or wet process is avoided, and the loss of the interlayer dielectric layer can be further reduced. Furthermore, in an alternative of the present invention, the cleaning gas is a synchronously pulsed plasma gas, i.e. the cleaning gas is fed in a synchronously pulsed manner. The synchronous pulse type input of the cleaning gas can ensure that the cleaning gas obtains sufficient relaxation time and can ensure that the cleaning gas fully reacts with residues on the substrate, thereby ensuring that the cleaning is more thorough and uniform.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (11)
1. A method of manufacturing a transistor, comprising:
forming the substrate includes: providing a substrate; forming a dummy gate on the substrate; forming an interlayer dielectric layer on the substrate between the dummy gates; covering a protective layer on the surface of the interlayer dielectric layer; the surface of the interlayer dielectric layer is completely covered by the protective layer; the protective layer is used for protecting the interlayer dielectric layer from being influenced in the subsequent process of removing the dummy gate;
etching by taking the protective layer and the interlayer dielectric layer as masks, and removing the pseudo gate by adopting a dry etching process; removing the protective layer by adopting a dry etching process, and forming a groove at the original position of the pseudo gate; the etching gas for removing the protective layer comprises nitrogen;
cleaning the substrate with a cleaning gas after forming the grooves, the cleaning gas comprising NF3Cleaning by adopting a synchronous pulse plasma mode to fully relax electrons and neutrons in the cleaning gas;
and filling a conductive material into the groove after cleaning is finished to form a grid.
2. The method of manufacturing of claim 1, wherein the step of cleaning the substrate with a cleaning gas comprises: the NF3The flow rate of the gas is 10-50 sccm.
3. The method of manufacturing of claim 1, wherein the step of cleaning the substrate with a cleaning gas comprises: in the presence of NF3Argon or helium is also introduced in the process of (2).
4. The method according to claim 3, wherein the flow rate of the argon gas or the helium gas is 50 to 300 sccm.
5. The method of manufacturing of claim 1 wherein said synchronously pulsed plasma is pulsed at a frequency in the range of 5KHz to 20 KHz.
6. The method of manufacturing of claim 1 wherein the pulsed duty cycle of the synchronously pulsed plasma is in the range of 30% to 75%.
7. The manufacturing method according to claim 1, wherein a material of the dummy gate is amorphous silicon.
8. The method of claim 1, wherein the interlayer dielectric layer is made of silicon oxide.
9. The method of claim 1, wherein the step of covering the surface of the interlayer dielectric layer with a protective layer comprises: the protective layer is made of photoresist.
10. The method of manufacturing of claim 1, wherein the step of removing the dummy gate using a dry etch process comprises: the etching gas comprises helium, oxygen and hydrogen bromide gas.
11. The method of manufacturing of claim 1, wherein after the step of cleaning the substrate with a cleaning gas and before the step of filling the recess with the conductive material, the method further comprises: and cleaning the substrate by adopting an ashing or wet process.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6300198B1 (en) * | 1997-03-19 | 2001-10-09 | Siemens Aktiengesellschaft | Method for producing a vertical MOS-transistor |
| CN103094180A (en) * | 2011-10-28 | 2013-05-08 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN104733303A (en) * | 2013-12-18 | 2015-06-24 | 中芯国际集成电路制造(上海)有限公司 | Dummy gate removing method and MOS transistor forming method |
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| CN101169600A (en) * | 2007-11-28 | 2008-04-30 | 上海宏力半导体制造有限公司 | Method for removing photoresist of titanium or titanium nitride layer in semiconductor production |
| CN101587833B (en) * | 2008-05-23 | 2010-11-10 | 中芯国际集成电路制造(北京)有限公司 | Method for removing residual photoresist |
| CN103137440B (en) * | 2011-11-21 | 2016-03-23 | 中芯国际集成电路制造(上海)有限公司 | Photoresist removing method |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6300198B1 (en) * | 1997-03-19 | 2001-10-09 | Siemens Aktiengesellschaft | Method for producing a vertical MOS-transistor |
| CN103094180A (en) * | 2011-10-28 | 2013-05-08 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN104733303A (en) * | 2013-12-18 | 2015-06-24 | 中芯国际集成电路制造(上海)有限公司 | Dummy gate removing method and MOS transistor forming method |
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