CN106257816B

CN106257816B - Control of a three-phase AC-to-DC power converter comprising three single-phase modules

Info

Publication number: CN106257816B
Application number: CN201510531074.2A
Authority: CN
Inventors: 奈杰尔·查尔斯·梅钦; 朱里安·德克特尔
Original assignee: Rectifier Technologies Pacific Pty Ltd
Current assignee: Rectifier Technologies Pacific Pty Ltd
Priority date: 2015-06-19
Filing date: 2015-08-26
Publication date: 2020-02-21
Anticipated expiration: 2035-08-26
Also published as: CN106257816A; AU2015203405B2; AU2015203405A1

Abstract

The present disclosure relates to a power converter and a method of controlling the power converter. An isolated AC to DC power converter operates from a three-phase AC power source without a neutral connection while providing a wide bandwidth output and eliminating high power supply impedance. The converter comprises three single-phase two-stage AC-to-DC converters, the inputs of which are star (or Y) connected and the outputs of which are connected in parallel. Three single-phase two-stage AC to DC converters are controlled in a new way to balance the star points and equalize the common power. The single-phase converter can be optimized for cost, efficiency and reliability.

Description

Control of a three-phase AC-to-DC power converter comprising three single-phase modules

Technical Field

The present invention is in the field of power electronics, and more particularly, to power conversion from a three-phase Alternating Current (AC) input to a single isolated Direct Current (DC) output and control thereof.

Background

In three-phase power conversion, it is desirable to extract power equally from all three phases to get the maximum output from the AC power source and to get the minimum loss in the AC power source. While there are many three-phase power converter topologies that can be considered, it is attractive to consider the use of three single-phase AC to DC converters that enjoy high efficiency, high reliability, low noise, and low cost. These single-phase converters are optimized with regard to the rating of their components for the phase to neutral voltage (phase to neutral voltage), so that phase connection to these single-phase converters is generally not possible (in this case 1.7 times this voltage occurs). These converters can simply be connected in a star configuration between the neutral point and each phase and their outputs connected in parallel for the purpose of balancing the phase power, but there is some objection to this practice.

In some aspects, the neutral connection is unreliable, and if a neutral disconnection occurs, the single phase converter will likely shut down due to AC over or under voltage, and likely fail. Also in some instances, the neutral point is not wired to the connection point of the equipment and sometimes cannot be derived from the mains supply transformer due to the delta-connected secondary winding.

For the above reasons, many users do not want a neutral connection in their three-phase power converters.

There are various solutions that allow the use of three single-phase converters in a star-like manner without a neutral connection. Three examples are described in the following references identified as D1 through D3, each of which is incorporated by cross-reference in its entirety into this disclosure.

In reference D1 ("A Three Phase Off-Lineswitching Power Supply with Unity Power Factor and Low TIF" by Gauger et al on INTELEC 1986), common control of all Three boost stages resulted in stable star points with or without a connected neutral point. The output of a boost power factor correction stage driving a small storage capacitor in front of a DCDC converter is controlled using hysteretic control, where the DCDC converter results in each single phase converter carrying 100Hz of ripple power, which reduces efficiency and produces noise on the output, and furthermore the low bandwidth of the output loop has little effect on attenuating the resulting 300Hz output ripple. This reference teaches that stable star points can be achieved using common control of the boost stages, but does not achieve low noise on the output and requires that each DCDC converter must be sized for peak power twice the average power, with a significant cost penalty.

In reference D2 ("Power Converter with starch configured Modules" by Tuch et al in US 5757637), an additional circuit compares the star point with an ideal neutral point formed by three resistors and provides a fast correction circuit for each boost stage. The stability of the arrangement was not analyzed. The complexity is high. This reference provides an alternative to reference 1 for achieving star point stability, which does not require any ripple power in the DCDC converter, but has considerable complexity and uncertain performance.

In reference D3 ("A Single Control StrategApplied to Three-Phase Rectifier Units for electronic communication application Using Single-Phase Rectifier Modules" on PESC 1999), a Single current demand was supplied to all Three DCDC stages that resulted in low output noise, but leaving the boost stage self-regulated. This arrangement is not stable at high power unless a neutral point is connected.

The inventors expect to use existing designs of single-phase two-stage converters in a three-phase configuration without sacrificing the performance of the converter in any way. New control methods and circuits have been developed for this purpose and are described below.

Disclosure of Invention

One aspect of the invention provides a three-phase AC to DC power converter operating without a neutral connection, the three-phase AC to DC power converter comprising:

a) three single-phase power converter modules, each single-phase power converter module comprising:

a Power Factor Correction (PFC) stage configured to extract an input current determined by multiplying its input voltage by a controllable input demand signal;

a storage capacitor connected to an output of the PFC stage; and

a DC-to-DC converter (DCDC) stage connected to the storage capacitor and having an output controllable by the output demand signal,

wherein three single phase power converter modules are star connected at their inputs and connected in parallel at their outputs; and

b) a control circuit for determining an input demand signal and an output demand signal such that, in use:

all three PFC stages are controlled together by an equal input demand signal determined by the average voltage across the three energy storage capacitors; and is

Each DCDC stage is individually controlled by an output demand signal comprising:

a common output demand current based on a total output current required by a load connected to the three-phase power converter, an

The required amount of correction is adjusted for the voltage across the associated storage capacitor of the respective module.

Another aspect of the invention provides a method of controlling a three-phase AC to DC power converter operating without a neutral connection, the converter comprising:

three single-phase power converter modules, each single-phase power converter module comprising:

a storage capacitor connected to an output of the power factor correction stage; and

a DC-to-DC converter stage (DCDC) connected to the storage capacitor and having an output controllable by the output demand signal,

wherein three single-phase power converter modules are star-connected at their inputs and parallel-connected at their outputs, an

The method comprises the following steps:

measuring the voltage across each storage capacitor;

determining an average capacitor voltage across the three storage capacitors;

generating an input demand signal that regulates the average capacitor voltage;

controlling all three power factor correction stages together by applying equal input demand signals;

measuring a current output from the DCDC stage of each module; and

generating an output demand signal for each DCDC stage, the output demand signal comprising:

a common output demand current based on a total output current required by a load connected to the three-phase power converter at a set output voltage, an

The correction required to adjust the voltage across the associated storage capacitor of the respective module; and

each DCDC stage is controlled based on a respective output demand signal.

Further preferred features of the invention may be as outlined in the appended claims, which are hereby incorporated by cross-reference as part of the present disclosure.

The equal input demand signals to the three PFC stages cause each of the input impedances of the PFC stages to behave as a resistor with equal value and this stabilizes the star point without the need to connect a neutral conductor.

Adjusting the average voltage of the three storage capacitors, rather than their individual values, allows for an equal input demand signal to be sent to the PFC stage and star point stability to be maintained despite phase imbalance or transient conditions. In a preferred embodiment, the closed loop bandwidth of the control loop may be made low (e.g. 5Hz), as typically occurs in single phase two-stage AC-DC power converters, which allows high impedance sources, such as motor generator sets, to be connected without stability problems.

Each storage capacitor is preferably sized to have a small ripple voltage at full power so that each DCDC stage experiences an almost constant conversion rate. In one embodiment, the voltage loop amplifier compares the output voltages of the three DCDC stages to a reference and generates a single common DCDC output current demand signal, suppressing any residual 100Hz and 300Hz ripple (assuming a 50Hz supply) at the output. This amplifier ensures low noise and good transient response at the output.

The common DCDC output demand signal is preferably fed into three separate output current loop amplifiers which compare the three output currents of the respective DCDC stages with the common demand and control each DCDC stage to achieve the required output current and suppress the 100Hz ripple present at each DCDC output. The three DCDC stages achieve equal output currents and have equal output voltages due to their parallel connection, thereby delivering equal output power.

In a preferred embodiment, each storage capacitor voltage is compared to the average storage capacitor voltage using a loop amplifier with a modest DC gain, and its output is added to or subtracted from the current feedback signal from each DCDC stage, enabling control of the respective storage capacitor voltage. Advantageously, these loops have a low closed loop bandwidth (e.g. 4Hz), or 100Hz ripple will be imposed on the output current of the DCDC stage. The DC gain of the loop amplifier is preferably made sufficient to achieve an acceptable match of the storage capacitor voltage but not higher so that saturation of the loop amplifier is avoided and the average output from the three loop amplifiers is zero, so that the presence of the storage capacitor control has little effect on the output of the voltage loop amplifier.

Where the specification concludes with claims or variations thereof, which include, but are not limited to, the presence of stated features, integers, steps or components or groups thereof, this is to be taken as specifying the presence of one or more other features, integers, steps, components or groups thereof, which may or may not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof.

Drawings

Fig. 1 shows a block diagram of a prior art single-phase two-stage AC-to-DC converter with a storage capacitor C.

Fig. 2 shows three single-phase converters as shown in fig. 1, which are star-connected at their inputs and connected to a three-phase power supply without a neutral point, and whose outputs are connected in parallel.

Fig. 3 shows in idealized form a preferred embodiment of the present invention using the circuits shown in fig. 1 and 2.

Fig. 4 shows one possible implementation of a single-phase converter of the type that can be used in the present invention. The converter includes a diode bridge, a boost circuit, a capacitor C, and an isolated LLC resonant stage. The boost controller includes a multiplier that varies the apparent input resistance with the control voltage.

Fig. 5 shows an implementation of an arrangement to stabilize the star point and maintain the average DC voltage across the three storage capacitors.

Fig. 6 shows an implementation of the present invention incorporating the stable star point arrangement of fig. 5 and sensing of the various output currents and output voltages and isolation control signals to the DCDC stage.

Fig. 7 shows an implementation of the control scheme according to a preferred embodiment of the invention.

Detailed Description

Referring now to the drawings, fig. 1 shows a single-phase converter having two power conversion stages. A Power Factor Correction (PFC) stage contains rectifying means and current control means, enabling the PFC stage to extract a current proportional to the input voltage and transfer the energy to the storage capacitor C. Since the AC input voltage is a sine wave at say 50Hz (depending on the mains frequency), the current delivered to the capacitor C will vary from zero to a double average at twice the input frequency or 100 Hz. The capacitor C must be sized to withstand 100Hz ripple current and also allow the voltage ripple at 100Hz to be acceptably small.

Typically in a single phase converter the input current demand is determined by regulating the voltage across the capacitor C and the bandwidth of the regulation is low (say 5Hz) so that the ripple voltage present on the capacitor does not significantly disturb the input current demand (which can lead to distortion of the input current and a reduced power factor). The power factor typically achieved by a PFC stage is close to 1 (typically 0.98-0.99) and the input current distortion is below 5%.

There are many possible implementations of a power factor correction stage that include a bridge rectifier before the boost stage, bridgeless boost including two boost stages and two diodes, a phase-leg input with two diodes, a full-bridge input, and others, all of which implement an input current that is proportional to the input voltage, thereby behaving like a resistor, thereby providing power factor correction.

The subsequent DCDC stage includes isolation means and typically contains regulation means with a loop amplifier to reduce the output noise below the output noise per unit ripple on C. There are also many possible implementations of the isolated DC-DC stage that include a phase-shifted full bridge and an LLC resonance that are useful for high efficiency.

Fig. 2 shows a star (or Y) connection at the inputs of three single-phase two-stage converters and a parallel connection of their outputs.

Fig. 3 shows in idealized form a preferred embodiment of the present invention utilising the circuit arrangement shown in fig. 1 and 2. The PFC stage is modeled as an input resistor Ri1, Ri2, Ri3 that extracts a current proportional to the input voltage AC in, and output current sources I1, I2, I3 that deliver current into capacitors C1, C2, C3 at voltages VC1, VC2, VC3, each delivering the same power as the input resistor extracts.

The value of each input resistor Ri1, Ri2, Ri3 is set by the input demand signals PFCdem1, PFCdem2, PFCdem3, wherein the input demand signals PFCdem1, PFCdem2, PFCdem3 are made equal so the input resistors have equal values.

The DCDC stage is modeled as current sinks Ii1, Ii2, Ii3 that extract power from the output of the PFC stage and current sources Io1, Io2, Io3 that deliver power to the output DC out, and the value of DC out is determined by the output demand signals dcdem1, dcdem2, DCDCdem 3. The power extracted by each DCDC input current sink Ii1, Ii2, Ii3 at capacitor voltages VC1, VC2, VC3 is equal to the power delivered by each output current source Io1, Io2, Io3 at output voltage Vout.

To control this arrangement, the average capacitor voltage is controlled by a loop amplifier G7, the individual capacitor voltages Vc1, Vc2, Vc3 are averaged at loop amplifier G7 to form VCave and compared to a reference VCaveref, the error signal is amplified by a gain G7 and sent equally as equal input demand signals PFCdem1, PFCdem2, PFCdem3 to control each PFC stage. These equal input demand signals guarantee equal power consumption from each stage and stable star point due to equal input resistance values. According to this control, only the average capacitor voltage VCave is controlled, so each capacitor can have a voltage different from the average value.

The output voltage Vout is regulated by a loop amplifier G8, the measured output voltage Vout is compared to a reference Voutref at loop amplifier G8, and the error is amplified by a gain G8 to form a common output current demand Ioutdem which is used as the output current demand for all three DCDC stages. Each output current is controlled by a respective output current loop amplifier G4, G5, G6, each output current Io1, Io2, Io3 is compared to a common output current demand Ioutdem at a respective output current loop amplifier G4, G5, G6, and the error signal is amplified by a gain G4, G5, G6 to form output current demand signals DCDCdem1, dcdem2, DCDCdem 3.

Because the output currents are equal in this arrangement, the power output from each stage is equal. But then additional control varies these output currents to adjust each capacitor voltage by adding three error signals VCe1, VCe2, VCe3 to the output currents Io1, Io2, Io 3. These capacitor voltage error signals VCe1, VCe2, VCe3 are generated by respective capacitor voltage loop amplifiers G1, G2, G3, wherein the respective capacitor voltage loop amplifiers G1, G2, G3 compare the average capacitor voltage VCave with the respective voltages VC1, VC2, VC3, and then the error signals are amplified by gains G1, G2, G3. Therefore, if any of the capacitor voltages VC1, VC2, VC3 is different from the average value, the output current is corrected to restore the voltage.

By limiting the DC gain of each capacitor voltage loop amplifier G1, G2, G3, the three control signals (i.e., capacitor voltage error signals VCe1, VCe2, VCe3) have an average value of zero, so the average output current is maintained even though each output current may be greater or less than their average value set by the common output current demand Ioutdem. Control of all three capacitor voltages is achieved by adjusting the output current individually.

Fig. 4 shows one possible topology of a single-phase two-stage converter. The AC input voltage AC in is rectified by a diode bridge and then processed by a boost circuit composed of a boost inductor LB, a boost switch SWB, and a boost diode DB, which delivers power into a storage capacitor C. By controlling the boost switch SWB using a Pulse Width Modulator (PWM) so that the magnitude of the input current is equal to the magnitude of the input voltage multiplied by the demand signal PFCdem, the stage behaves like a resistor of an AC input and a power factor close to 1 is achieved.

The isolated LLC DCDC stage is made up of switches SW1 and SW2, resonant elements LR, CR1, CR2, and the magnetizing inductance of transformer Tx, and a diode bridge connected to the secondary of transformer Tx. By controlling the switch inversion at almost 50% duty cycle and using a Frequency Modulator (FM) to vary the frequency, control of the output voltage and current can be achieved from the demand signal dcdem using the characteristics of the resonant network.

Fig. 5 shows three single-phase PFC stages combined according to fig. 2, such that their inputs are star (or Y) connected and the DCDC stage is omitted for clarity purposes, and a control circuit to stabilize the star point is shown in fig. 3. The control circuit of each PFC (e.g., as shown in fig. 4) ensures that the extracted input current is proportional to the input voltage multiplied by the desired value, forming an apparent input resistance. With varying demands, varying input power will be extracted.

In a single phase converter, the demand is varied to regulate the individual storage capacitor voltages, but not so here. Each PFC stage input demand signal PFCdem1, PFCdem2, PFCdem3 is identical and controlled by a single loop amplifier a7, the loop amplifier a7 controlling an average capacitor voltage VCave, which is an average of three capacitor voltages Vc1, Vc2, Vc3 through R1, R2, R3, to be equal to a reference VCaveref.

The reason for using a single control signal is to ensure that the requirements of all three circuits are the same, so the apparent input resistance of all three circuits is the same. This ensures stability of the star point even in the case of AC imbalance. The closed loop bandwidth of the average capacitor voltage loop amplifier a7 is low (say 5Hz) so that the demand signal at its output is substantially constant during the mains frequency cycle, allowing low distortion and high immunity to AC high line impedance with similar performance to typical single phase control circuits.

The gains of the individual PFC control circuits should be well matched over the control range (say +/-5%) to achieve similar apparent input resistance values and equal AC input voltages for each stage. Any gain mismatch results in unequal AC voltages due to unequal apparent resistance, and although not desired, the situation is stable because the apparent resistance is constant.

When controlling the average capacitor voltage VCave of all three capacitors, the individual capacitor voltages Vc1, Vc2, Vc3 may differ from each other by a small or large amount and still meet the average value requirement. This difference is undesirable and can lead to failure. So star point stability is solved but new problems arise.

Referring to fig. 6, three single-phase converters are combined according to fig. 1, 2 and 5 such that their inputs are star-connected and their outputs are connected in parallel. The sensing points of the output current and voltage are shown along with the isolated DCDC control signal, and the circuit that controls the DCDC stage is shown in fig. 7.

Referring to fig. 7, an output voltage loop amplifier A8 compares the output voltage Vout via R13 to a reference Voutref and has a high closed loop bandwidth (say 2kHz) to reject noise and accurately regulate the voltage output. The output of which is a common output demand current Ioutdem which is equally fed to the respective output current loop amplifiers a4, a5, a 6. As will be described below, the individual DCDC stages are controlled by loop amplifiers a4, a5, a6, and this individual control enables the capacitor imbalance problem outlined above to be solved.

Each output current loop amplifier a4, a5, a6 compares the output current Iout1, Iout2, Iout3 via R4, R5, R6 with the demanded current Ioutdem from the output voltage loop amplifier A8 and regulates each DCDC stage with a high closed loop bandwidth (say 5kHz) to achieve the demanded current and suppress any 100Hz ripple (assuming a 50Hz line frequency) present on the storage capacitor. The modulators Mod 1, Mod 2, Mod 3 are shown at the output of the loop amplifier before the isolation stages dcdem1, DCDCdem2, DCDCdem3, but they can equally well be placed after the isolation stages with the same function.

The result of achieving equal output currents and equal output voltages due to the parallel connection of the outputs is equal output power and thus equal input power from the three single-phase converters, thus achieving equal sharing of power between the converters. But sometimes equal power is not desired as described below.

Consider the case where the matching of the apparent input resistors of the three converters is defective or the sensing of the three output currents is defective. Either situation will result in the storage capacitor continuously losing or continuously gaining energy, running away to zero or a very high voltage, and the protection circuit opening or the converter is likely to fail. It is desirable to adjust the individual capacitor voltages to mitigate this situation.

Consider the case of an AC phase imbalance, in which case one phase voltage is lower than the other two phase voltages. The PFC stage will continue to present three equal capacitors to the AC inputs connected together at the star point. Because the input voltage is small, the current drawn in the lower phase will be small, so the average power drawn by the PFC stage connected to that phase will be small.

To achieve balance, the DCDC stage must consume the same average power as the PFC stage, otherwise the capacitor voltage will steadily drop or rise. Each capacitor voltage is adjusted by varying the DCDC power consumption so that the power in each DCDC matches the power provided by the PFC stage.

Each capacitor voltage loop amplifier a1, a2, A3 achieves capacitor voltage regulation by varying the output current Iout1, Iout2, Iout 3. They compare the individual capacitor voltages via R10, R11, R12 with the average capacitor voltage VCave and supply correction signals VCe1, VCe2, VCe3 to each of the output currents via R7, R8, R9 at the input nodes of the loop amplifiers a4, a5, a 6.

The closed loop bandwidth of each capacitor voltage loop amplifier a1, a2, A3 is low (say 4Hz) so that the ripple appearing at 100Hz on the capacitor voltage Vc1, Vc2, Vc3 does not substantially appear at the output of the capacitor voltage loop amplifier a1, a2, A3 and the DCDC stage controlled by each output current loop amplifier a4, a5, A6 does not substantially carry 100Hz ripple. The DC gain of the respective capacitor voltage loop amplifiers a1, a2, A3 may be advantageously limited to a value (say within 2%) sufficient to achieve an acceptable match of the capacitor voltages, with the following benefits: clipping (clipping) of these amplifiers a1, a2, A3 is avoided, and the average of the capacitor error voltages VCe1, VCe2, VCe3 is zero, so the behavior of the output voltage loop amplifier A8 is not substantially affected by the capacitor voltage regulation.

When all the above controls are used in the preferred embodiment of the invention, the star point is stable and the input current enjoys low distortion similar to a single phase converter, the capacitor voltage is controlled, the 100Hz ripple in the DCDC stage is low, the three converters share power equally except in the case of phase imbalance, and the output enjoys low noise similar to a single phase converter.

Finally, while preferred embodiments of the present invention have been described in detail herein, those skilled in the art will understand that other embodiments are possible and that such embodiments are included within the scope of the appended claims. For example, as shown in fig. 7, the control circuit shown in the drawing may be implemented in hardware, or may be implemented entirely or partially in software. It is to be appreciated that a software implementation of the control circuit will be well within the capabilities of those skilled in the art and therefore need not be described in detail herein. Such implementations are considered to fall within the scope of the appended claims.

Claims

1. A three-phase ac-to-dc power converter operating without a neutral connection, comprising:

a Power Factor Correction (PFC) stage configured to extract an input current determined by its input voltage multiplied by a controllable input demand signal;

a direct current to direct current converter (DCDC) stage connected to the energy storage capacitor and having an output controllable by an output demand signal,

wherein the three single phase power converter modules are star connected at their inputs and connected in parallel at their outputs; and

b) a control circuit for determining the input demand signal and the output demand signal such that, in use:

controlling all three power factor correction stages together by equal input demand signals determined by adjusting the average voltage across the three energy storage capacitors; and is

Each DC-to-DC converter stage is individually controlled by an output demand signal comprising:

a common output demand current based on a total output current required by a load connected to the three-phase AC-to-DC power converter, an

The required correction amount for the adjustment of the capacitor voltage over the associated storage capacitor of the respective module.

2. The converter of claim 1, wherein the correction amount is determined by a difference between (i) a capacitor voltage across each associated energy storage capacitor and (ii) the average voltage across the three energy storage capacitors.

3. A converter according to claim 2 wherein the average voltage across the three storage capacitors is controlled by an average voltage loop amplifier at which the individual capacitor voltages are averaged and then compared to a reference voltage.

4. A converter according to claim 3, wherein the amount of correction required to effect adjustment of the storage capacitors is determined by respective capacitor voltage loop amplifiers that compare the respective capacitor voltages with the average voltage across the three storage capacitors.

5. The converter of claim 4, wherein a closed loop bandwidth of the respective capacitor voltage loop amplifier is sufficiently low such that a ripple voltage present on the capacitor voltage is substantially absent at the output of the respective capacitor voltage loop amplifier.

6. A converter according to claim 5 wherein the DC gain of the respective capacitor voltage loop amplifiers is limited such that clipping of these amplifiers is avoided.

7. A converter according to any one of claims 1 to 6 wherein the common output demand current is determined by an output voltage loop amplifier which compares the output voltage of the three phase AC to DC converter with an output reference voltage.

8. The converter of claim 7, wherein the output voltage loop amplifier has a high closed loop bandwidth.

9. The converter of claim 7, wherein the common output demand current is equally fed to respective output current loop amplifiers, each of which compares an actual output current delivered by the respective DC-to-DC converter stage with the common output demand current.

10. The converter of claim 9, wherein the respective output current loop amplifier regulates each dc-to-dc converter stage with a high closed loop bandwidth.

11. A converter according to claim 7 wherein each DC to DC converter stage is isolated such that the output of each module is isolated from its input.

12. A converter according to claim 1, 2, 3, 4, 5, 6, 8, 9 or 10 wherein each dc-to-dc converter stage is isolated such that the output of each module is isolated from its input.

13. A method of controlling a three-phase ac to dc power converter operating without a neutral connection, the converter comprising:

wherein the three single-phase power converter modules are star-connected at their inputs and parallel-connected at their outputs, and

the method comprises the following steps:

measuring a capacitor voltage across each storage capacitor;

determining an average capacitor voltage across the three storage capacitors;

generating an equal input demand signal to regulate the average capacitor voltage;

controlling all three power factor correction stages together by applying the equal input demand signals;

measuring a current output of the DC-to-DC converter stage from each module; and

generating an output demand signal for each DC-to-DC converter stage, the output demand signal comprising:

a common output demand current based on a total output current required at a set output voltage by a load connected to the three-phase AC-to-DC power converter, an

The correction required to adjust the capacitor voltage across the associated storage capacitor of the respective module; and

each dc-to-dc converter stage is controlled based on a respective output demand signal.

14. The method of claim 13, wherein the correction amount is determined by a difference between (i) an average voltage across the three storage capacitors and (ii) a capacitor voltage across each associated storage capacitor.