CN106257648A - The forming method of semiconductor device - Google Patents
The forming method of semiconductor device Download PDFInfo
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- CN106257648A CN106257648A CN201510348723.5A CN201510348723A CN106257648A CN 106257648 A CN106257648 A CN 106257648A CN 201510348723 A CN201510348723 A CN 201510348723A CN 106257648 A CN106257648 A CN 106257648A
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- 238000000034 method Methods 0.000 title claims abstract description 77
- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 239000010410 layer Substances 0.000 claims abstract description 476
- 239000000758 substrate Substances 0.000 claims abstract description 254
- 229910052751 metal Inorganic materials 0.000 claims abstract description 216
- 239000002184 metal Substances 0.000 claims abstract description 216
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 208
- 239000011229 interlayer Substances 0.000 claims abstract description 78
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- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 17
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 17
- 230000004888 barrier function Effects 0.000 claims description 15
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 15
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- 239000011787 zinc oxide Substances 0.000 claims description 9
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- 229910052737 gold Inorganic materials 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
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- 238000012545 processing Methods 0.000 description 12
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- 229910052732 germanium Inorganic materials 0.000 description 3
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- 229910052738 indium Inorganic materials 0.000 description 3
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- 239000012212 insulator Substances 0.000 description 3
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- LCKIEQZJEYYRIY-UHFFFAOYSA-N Titanium ion Chemical compound [Ti+4] LCKIEQZJEYYRIY-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
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- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 2
- 229910017121 AlSiO Inorganic materials 0.000 description 1
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- -1 HfSiON Inorganic materials 0.000 description 1
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A kind of forming method of semiconductor device, including: form top dielectric layer on interlayer dielectric layer surface and grid structure top surface；Metal Substrate photoresist layer is formed on top dielectric layer surface；Metal Substrate photoresist layer is carried out photoetching treatment, is formed and be positioned at the first opening above doped region；Along the first opening etching top dielectric layer and interlayer dielectric layer, described interlayer dielectric layer forms the second opening exposing doped region surface；Remove described Metal Substrate photoresist layer；Form the conductive layer filling full described second opening.The present invention improves position precision and the pattern of the second opening of formation, thus improves electric property and the yield of the semiconductor device of formation.
Description
Technical field
The present invention relates to semiconductor fabrication techniques field, particularly to the forming method of a kind of semiconductor device.
Background technology
Along with integrated circuit develops to super large-scale integration, the current densities of IC interior is more come
The biggest, the number of elements comprised also gets more and more.In semiconductor integrated circuit, metal-oxide half
Conductor (MOS, Metal Oxide Semiconductor) transistor is one of the most of paramount importance element.
Existing MOS transistor processing step includes: provide substrate；Formed some at described substrate surface
Grid structure；Forming doped region in the substrate of described grid structure both sides, described doped region is as MOS
The source electrode of transistor or drain electrode；Interlayer dielectric layer is formed on described doped region surface and grid structure surface,
Described interlayer dielectric layer top flushes with grid structure top；At described interlayer dielectric layer surface and grid
Structural top surface forms top dielectric layer；Formed in described top dielectric layer and expose grid structure top
First contact hole on surface, portion；Form the second contact running through described top dielectric layer and interlayer dielectric layer
Hole, described second contact holes exposing goes out doped region surface；At described first contact hole and the second contact hole
The full conductive layer of interior filling, described conductive layer is as the metal plug of MOS transistor.
But, along with the size of semiconductor device is more and more less, the semiconductor device that prior art is formed
Electric property needs to be improved further.
Summary of the invention
The problem that the present invention solves is to provide the forming method of a kind of semiconductor device, to improve half formed
The electric property of conductor device and yield.
For solving the problems referred to above, the present invention provides the forming method of a kind of semiconductor device, including: provide
Substrate, described substrate surface is formed with grid structure, is formed and mixes in the substrate of described grid structure both sides
Miscellaneous district, described substrate surface is also formed with interlayer dielectric layer, and described interlayer dielectric layer is positioned at grid structure side
Wall surface, and described interlayer dielectric layer top flushes with grid structure top；At described interlayer dielectric layer table
Face and grid structure top surface form top dielectric layer；Metal is formed on described top dielectric layer surface
Base photoresist layer；Described Metal Substrate photoresist layer is carried out photoetching treatment, is formed in described Metal Substrate photoresist layer
First opening, and described first opening is positioned at above doped region；Described upper strata is etched along described first opening
Dielectric layer and interlayer dielectric layer, formed in described interlayer dielectric layer and expose the second of doped region surface
Opening；Remove described Metal Substrate photoresist layer；Form the conductive layer filling full described second opening.
Optionally, before forming described Metal Substrate photoresist layer, described top dielectric layer forms the 3rd
Opening, described 3rd opening exposes grid structure top；Described Metal Substrate photoresist layer also fills up completely described
3rd opening；While forming the conductive layer filling full described second opening, described conductive layer also fills up
Full described 3rd opening.
Optionally, described substrate includes: substrate, is positioned at the some discrete fin of substrate surface, is positioned at
The sealing coat of the substrate surface of fin both sides, described sealing coat is covered in fin sidewall surfaces, and described every
Absciss layer top is less than fin top, and wherein, described grid structure is positioned at insulation surface and across at least one
Individual fin, described grid structure covers top and the sidewall of fin.
Optionally, described 3rd opening is positioned at above the sealing coat adjacent with described fin；Described 3rd opens
Mouth exposes the grid structure top above sealing coat.
Optionally, the material of described Metal Substrate photoresist layer is titanium oxide, zirconium oxide, tungsten oxide, zinc oxide
Or aluminium oxide.
Optionally, described photoetching treatment includes exposure-processed and development treatment.
Optionally, before forming described top dielectric layer, further comprise the steps of: at described interlayer dielectric layer
And grid structure top surface forms etching barrier layer.
Optionally, described Metal Substrate photoresist layer is single layer structure；Described Metal Substrate photoresist layer is the first metal
Base photoresist layer；Described first opening runs through described first Metal Substrate photoresist layer.
Optionally, described Metal Substrate photoresist layer is laminated construction；Described Metal Substrate photoresist layer includes the first gold medal
Belong to base photoresist layer and be positioned at the second Metal Substrate photoresist layer on the first Metal Substrate photoresist layer surface.
Optionally, the method that described Metal Substrate photoresist layer carries out photoetching treatment is: to described second metal
Base photoresist layer carries out photoetching treatment, and described first opening runs through described second Metal Substrate photoresist layer.
Optionally, before etching described top dielectric layer and interlayer dielectric layer, edge is further comprised the steps of:
Described first opening etches described first Metal Substrate photoresist layer, until exposing top dielectric layer surface.
Optionally, the material of described first Metal Substrate photoresist layer is zirconium oxide；Described second Metal Substrate photoresistance
The material of layer is titanium oxide.
Optionally, the technological parameter etching described first Metal Substrate photoresist layer is: BCl3Flow is 50sccm
To 300sccm, Cl2Flow is 10sccm to 200sccm, CH4Flow is 0sccm to 100sccm,
Chamber pressure is that 10 millitorrs are to 200 millitorrs, it is provided that source power 100 watts to 1000 watts, it is provided that biasing merit
Rate 0 watt to 300 watts.
Optionally, the technological parameter etching described top dielectric layer and interlayer dielectric layer is: CHF3Flow
For 10sccm to 100sccm, CF4Flow is 10sccm to 200sccm, CH2F2Flow is 0sccm
To 100sccm, chamber pressure is that 10 millitorrs are to 200 millitorrs, it is provided that source power 100 watts to 1000 watts,
Bias power 0 watt to 300 watts is provided.
Optionally, wet-etching technology is used to remove described Metal Substrate photoresist layer；Use spin coating process
Form described Metal Substrate photoresist layer.
Optionally, along described fin bearing of trend, the size of described first opening be 100 angstroms to 1000
Angstrom, the distance between adjacent first opening is 500 angstroms to 5000 angstroms.
The present invention also provides for the forming method of a kind of semiconductor device, including: substrate, described substrate are provided
Surface is formed with grid structure, is formed with doped region, described substrate in the substrate of described grid structure both sides
Surface is also formed with interlayer dielectric layer, and described interlayer dielectric layer is positioned at gate structure sidewall surface, and described
Interlayer dielectric layer top flushes with grid structure top；At described interlayer dielectric layer and grid structure top
Surface forms top dielectric layer, is formed with the 3rd opening exposing grid structure in described top dielectric layer；
Formed and fill full described 3rd opening and be positioned at the first Metal Substrate photoresist layer on top dielectric layer surface；To institute
The rheme the first Metal Substrate photoresist layer in top dielectric layer surface carries out the first photoetching treatment, described first
Forming groove in Metal Substrate photoresist layer, described groove is above doped region and between adjacent doped region
Interlayer dielectric layer above；After forming described groove, at described first Metal Substrate photoresist layer top table
Face and sidewall surfaces form cured layer；After forming described cured layer, formed and fill full described groove
Second Metal Substrate photoresist layer；Described second Metal Substrate photoresist layer is carried out the second photoetching treatment, described
Two Metal Substrate photoresist layers are formed the first opening, and described first opening is positioned at above doped region；Along described
First opening etches described top dielectric layer and interlayer dielectric layer, is formed sudden and violent in described interlayer dielectric layer
Expose second opening on doped region surface；Remove described first Metal Substrate photoresist layer and the second Metal Substrate light
Resistance layer；Form the conductive layer filling full described second opening.
Optionally, the material of described first Metal Substrate photoresist layer is titanium oxide, zirconium oxide, tungsten oxide, oxygen
Change zinc or aluminium oxide；The material of described second Metal Substrate photoresist layer be titanium oxide, zirconium oxide, tungsten oxide,
Zinc oxide or aluminium oxide；The material of described cured layer is silicon.
Optionally, described substrate includes: substrate, is positioned at the some discrete fin of substrate surface, is positioned at
The sealing coat of the substrate surface of fin both sides, described sealing coat is covered in fin sidewall surfaces, and described every
Absciss layer top is less than fin top, and wherein, described grid structure is positioned at insulation surface and across at least one
Individual fin, described grid structure covers top and the sidewall of fin.
Optionally, described 3rd opening is positioned at above the sealing coat adjacent with described fin；Described 3rd opens
Mouth exposes the grid structure top above sealing coat.
Compared with prior art, technical scheme has the advantage that
The present invention provides the forming method of a kind of semiconductor device, forms Metal Substrate on top dielectric layer surface
Photoresist layer；Metal Substrate photoresist layer is carried out photoetching treatment, is formed and be positioned at the first opening above doped region；
Then along the first opening etching top dielectric layer and interlayer dielectric layer, formed in interlayer dielectric layer and expose
Going out second opening on doped region surface, described second opening is doped region contact hole.The present invention uses metal
Base photoresist layer forms the mask of doped region contact hole as etching, it is possible to form size relatively by photoetching process
It is the least that distance between the first opening that little and position precision is high, and adjacent first opening can be done,
And the first opening has good pattern so that formed the second opening have less size and
There is preferably pattern, thus improve electric property and the yield of semiconductor device.
Further, Metal Substrate photoresist layer includes the first Metal Substrate photoresist layer and is positioned at the first Metal Substrate photoresistance
The second Metal Substrate photoresist layer on layer surface.Wherein, the formation of the first Metal Substrate photoresist layer can be for formation the
Two Metal Substrate photoresist layers provide good interface basis so that the bottom of the second Metal Substrate photoresist layer of formation
Surface and top surface are respectively provided with higher flatness, it is to avoid the second Metal Substrate photoresist layer is carried out photoetching
There is unnecessary scattering or reflection during process, thus further increase in the second Metal Substrate photoresist layer
The position precision of the first opening formed and pattern, and then make the position of the second opening formed accurate
Degree and pattern are further improved, and improve electric property and the yield of the semiconductor device of formation accordingly.
The present invention also provides for the forming method of a kind of semiconductor device, forms first on top dielectric layer surface
Metal Substrate photoresist layer, described first Metal Substrate photoresist layer fills full 3rd opening；It is being positioned at top dielectric layer
The first Metal Substrate photoresist layer on surface carries out the first photoetching treatment, is formed recessed in the first Metal Substrate photoresist layer
Groove, described groove has smooth lower surface；At the first Metal Substrate photoresist layer top surface and sidewall table
Face forms cured layer, and described cured layer is it can be avoided that the first Metal Substrate photoresist layer is exposed to the second follow-up light
Carve in processing environment.After forming cured layer, form the second Metal Substrate photoresist layer filling full groove,
Owing to bottom portion of groove surface is smooth so that the second Metal Substrate photoresist layer without carrying out process for filling hole, i.e. second
Metal Substrate photoresist layer is without filling the 3rd opening, bottom the second Metal Substrate photoresist layer that therefore present invention is formed
Surface and top surface flatness are high so that the second Metal Substrate photoresist layer is being carried out the second photoetching treatment mistake
Journey is avoided unnecessary reflection or scattering, thus improves position precision and the shape of the first opening of formation
Looks, and then make the position precision height of the second opening of formation in interlayer dielectric layer and pattern good,
Improve electric property and the yield of the semiconductor device formed further.
Accompanying drawing explanation
The structural representation of the semiconductor device forming process that Fig. 1 to Figure 15 provides for one embodiment of the invention
Figure；
Figure 16 to Figure 20 shows for the structure of the semiconductor device forming process that another embodiment of the present invention provides
It is intended to；
Figure 21 to Figure 28 shows for the structure of the semiconductor device forming process that further embodiment of this invention provides
It is intended to.
Detailed description of the invention
From background technology, the electric property of the semiconductor device that prior art is formed has much room for improvement.With
The continuous reduction of dimensions of semiconductor devices, the metal plug that prior art is formed and grid structure, metal
Alignment precision between connector and doped region is more and more less, causes the resistance of semiconductor device to become big；Further,
During forming the first contact hole and the second contact hole, easily etching is caused in undesirably region, enter
And cause the electric property of semiconductor device and yield low.Owing to the distance between adjacent doped region is less,
Therefore the problem of the alignment precision difference between the second contact hole and doped region is particularly acute,
For solving the problems referred to above, the method proposing to use Dual graphing method, to improving the second contact hole
And the alignment precision between doped region.Concrete, formed on top dielectric layer surface low temperature oxide (LTO,
Low Temperature Oxide) layer；First light with the first opening is formed on low temperature oxide layer surface
Photoresist layer, described first opening is positioned at above the doped region of grid structure side；With described first photoresist
Layer is mask, forms the second opening in described low temperature oxide layer；There is described in removal the first opening
First photoresist layer；Then, formed on the described low temperature oxide layer surface with the second opening and have the
Second photoresist layer of three openings；With described second photoresist layer as mask, in described low temperature oxide layer
Interior formation the 4th opening；Remove the second photoresist layer of described 3rd opening；With described, there is the second opening
It is mask with the low temperature oxide layer of the 4th opening, etches described top dielectric layer and interlayer dielectric layer,
Form the second contact hole exposing doped region surface.
But, use said method to form the production cost height of semiconductor device, and the second photoresist layer figure
Shape and the first photoresist layer figure still suffer from the problem that graph position alignment precision is poor.
To this end, the present invention proposes the forming method of a kind of new semiconductor device, formation can not only be improved
The electric property of semiconductor device and yield, additionally it is possible to reduce the production cost of semiconductor device.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The specific embodiment of the present invention is described in detail.
The structural representation of the semiconductor device forming process that Fig. 1 to Figure 15 provides for one embodiment of the invention
Figure.
The semiconductor device that the present invention is formed can be nmos device, PMOS device or cmos device,
Semiconductor device can also be planar transistor or fin field effect pipe transistor.The present embodiment will be to be formed
Semiconductor device be that CMOS fin field effect pipe is described in detail as example.
Referring to figs. 1 to Fig. 3, wherein, Fig. 1 is perspective view, and Fig. 2 is that Fig. 1 is along line of cut
The cross-sectional view of XX1 cutting, Fig. 3 is the cross-section structure signal that Fig. 1 cuts along line of cut YY1
Figure, it is provided that substrate.
In the present embodiment, described substrate includes: substrate 100, be positioned at the some discrete of substrate 100 surface
Fin 101, it is positioned at the sealing coat 102 on substrate 100 surface of fin 101 both sides, described sealing coat 102
It is covered in fin 101 sidewall surfaces, and described sealing coat 102 top is less than fin 101 top.
The material of described substrate 100 is silicon, germanium, SiGe, GaAs or gallium indium, described substrate 100
Can also be the silicon substrate on insulator, the germanium substrate on insulator or the silicon-Germanium substrate on insulator；
The material of described fin 101 is silicon, germanium, SiGe, GaAs or gallium indium.In the present embodiment, institute
Stating substrate 100 is silicon substrate, and the material of described fin 101 is silicon.
Described sealing coat 102, for forming the isolation structure of semiconductor device, makes between adjacent fin 101
Electric isolution.The material of described sealing coat 102 is silicon oxide, silicon nitride or silicon oxynitride.The present embodiment
In, the material of described sealing coat 102 is silicon oxide.
Described substrate 100 includes that NMOS area I and PMOS area II, described NMOS area I are
Forming nmos device and provide technique platform, described PMOS area II provides for forming PMOS device
Technique platform.
With reference to Fig. 4 to Fig. 5, form grid structure at described substrate surface；Formation is positioned at described grid structure
The side wall 107 of sidewall surfaces；Doped region 105 is formed in the substrate of described grid structure both sides；Described
Substrate surface forms interlayer dielectric layer 106, and described interlayer dielectric layer 106 is positioned at gate structure sidewall surface,
And described interlayer dielectric layer 106 top flushes with grid structure top.Wherein, Fig. 4 is on Fig. 2 basis
On schematic diagram, Fig. 5 is the schematic diagram on the basis of Fig. 3.In the present embodiment, described grid structure position
In sealing coat 102 surface and across fin 101 at least one described, described grid structure also covers fin
The top of 101 and sidewall；Described interlayer dielectric layer 106 is positioned at sealing coat 102 surface.
Described grid structure includes gate dielectric layer 103 and is positioned at the grid conductive layer on gate dielectric layer 103 surface
104.The material of described gate dielectric layer 103 is silicon oxide or high K medium material, wherein, high K medium material
Material refers to the relative dielectric constant material more than the relative dielectric constant of silicon oxide, high K medium material bag
Include LaO, AlO, BaZrO, HfZrO, HfZrO, HfZrON, HfSiO, HfSiON, AlSiO,
HfTiO or Al2O3；The material of described grid conductive layer 104 be polysilicon, copper, aluminum, tungsten, titanium, tantalum or
Gold.
In the present embodiment, the material of described gate dielectric layer 103 is HfSiO, the material of described grid conductive layer 104
Material is tungsten.
The present embodiment with two fins 101 that NMOS area I is arranged in parallel share a grid structure,
PMOS area II two fins 101 arranged in parallel share a grid structure as example.At other
In embodiment, it is also possible to the corresponding independent grid structure of each fin, plural fin shares
One grid structure.
Before forming described doped region 105, form side wall 107, described side on gate structure sidewall surface
Wall 107 can play the effect of protection gate structure sidewall.In the present embodiment, described side wall 107 is single
Rotating fields, the material of side wall 107 is silicon nitride.In other embodiments, described side wall is laminated construction,
Including covering the silicon oxide layer on gate structure sidewall surface and being positioned at the silicon nitride layer on silicon oxide layer surface.
In the present embodiment, in the fin 101 of described grid structure both sides formed doped region 105, described in mix
Miscellaneous district 105 is for forming source electrode or the drain electrode of semiconductor device.For NMOS area I, doping
The dopant ion in district 105 is N-type ion, and described N-type ion is phosphorus, arsenic or antimony；For PMOS district
For the II of territory, the dopant ion of doped region 105 is p-type ion, and described p-type ion is boron, gallium or indium.
In order to improve the carrier mobility of semiconductor device, it is positioned at the doped region 105 of NMOS area I
In can also form stressor layers, the material of described stressor layers is the carborundum of carborundum or p-doped；It is positioned at
Can also form stressor layers in the doped region 105 of PMOS area II, the material of described stressor layers is germanium
Silicon or the SiGe of boron-doping.
The material of described interlayer dielectric layer 106 is silicon oxide, silicon nitride or silicon oxynitride.Described interlayer is situated between
The material of matter layer 106 is different from the material of side wall 107 so that follow-up when etching interlayer dielectric layer 106
Side wall 107 will not be caused etching, and then above doped region 105, form self-aligned contact hole
(Self-aligned Contact).In the present embodiment, the material of described interlayer dielectric layer 106 is silicon oxide.
With reference to Fig. 6 to Fig. 7, etching removes the grid conductive layer being positioned at the segment thickness directly over fin 101
104；Etching barrier layer 108 is formed on described remaining grid conductive layer 104 surface；At described inter-level dielectric
Layer 106 surface and grid structure surface form top dielectric layer 109.Wherein, Fig. 6 is on Fig. 4 basis
On schematic diagram, Fig. 7 is the schematic diagram on the basis of Fig. 5.
Described etching barrier layer 108 can play the effect of protection grid conductive layer 104, prevents grid conductive layer
104 are exposed in follow-up etching process environment so that grid conductive layer 104 remains good performance.
In the present embodiment, the material of described etching barrier layer 108 is silicon nitride.In order to make the etch stopper of formation
Layer 108 has enough protective effects, and removes the grid conductive layer 104 of segment thickness to grid structure
The harmful effect that causes of performance little, in the present embodiment, the thickness of described etching barrier layer 108 is 5 angstroms
To 50 angstroms.
In the present embodiment, described etching barrier layer 108 is also located at interlayer dielectric layer 106 top surface.Shape
The processing step becoming described etching barrier layer 108 includes: in described remaining grid conductive layer 104 surface shape
Becoming protecting film, described protecting film is also located at interlayer dielectric layer 106 surface；Use chemical mechanical milling tech,
Planarize described protecting film, formed and be positioned at interlayer dielectric layer 106 surface and residue grid conductive layer 104 table
The etching barrier layer 108 in face.
Owing to, in the present embodiment, interlayer dielectric layer 106 surface and grid conductive layer 104 surface are formed with quarter
Erosion barrier layer 108, because, in the present embodiment, described top dielectric layer 109 is positioned at etching barrier layer 108 surface.
The material of described top dielectric layer 109 is silicon oxide, silicon nitride or silicon oxynitride.In the present embodiment, institute
The material stating top dielectric layer 109 is identical with the material of interlayer dielectric layer 106, described top dielectric layer 109
Material be silicon oxide.
It is the schematic diagram on the basis of Fig. 6 with reference to Fig. 8, Fig. 8, is formed in described top dielectric layer 109
3rd opening 110, described 3rd opening 110 exposes grid structure top surface.
Described 3rd opening 110 exposes grid conductive layer 104 surface；Described 3rd opening 110 as with
The gate contact hole of grid structure electrical connection, follow-up completely conductive layer of filling in gate contact hole forms grid
Metal plug, described metal plug electrically connects with grid structure.
In the present embodiment, the 3rd opening 110 of NMOS area I is not to be just formed at fin 101
Top, and it is formed in above the sealing coat 102 adjacent with described fin 101, the most described NMOS
3rd opening 110 of region I exposes grid conductive layer 104 top surface above sealing coat 102.Equally
, the 3rd opening 110 of PMOS area II is also formed on the sealing coat 102 adjacent with grid structure
Side, the grid conductive layer 104 that the 3rd opening 110 of PMOS area II exposes above sealing coat 102 pushes up
Surface, portion.
Being the schematic diagram on the basis of Fig. 8 with reference to Fig. 9 and Figure 10, Fig. 9, Figure 10 is on the basis of Fig. 7
Schematic diagram, described top dielectric layer 109 surface formed Metal Substrate photoresist layer.
In the present embodiment, described Metal Substrate photoresist layer also fills up the most described 3rd opening 110 (with reference to Fig. 8)；
Described Metal Substrate photoresist layer is single layer structure, and described Metal Substrate photoresist layer is the first Metal Substrate photoresist layer 111.
Owing to the material of the first Metal Substrate photoresist layer 111 is Metal Substrate photoresist, therefore the first Metal Substrate
Photoresist 111 is after photoetching treatment, it is possible to is directly formed and has the of doped region contact hole graph
One opening, described first opening is positioned at above doped region 105, it is to avoid cause in figure transfer process
Position deviation；Further, the Other substrate materials traditional with employing, as mask, then carries out photoetching to mask
Process forms the first opening comparatively speaking, and the first opening formed in the present embodiment is sized to accomplish
Less, the distance between adjacent first opening can be accomplished less, and the figure pattern of the first opening is accurate
Du Genggao.
The material of described first Metal Substrate photoresist layer 111 is titanium oxide, zirconium oxide, tungsten oxide, zinc oxide
Or aluminium oxide.Spin coating process (spin on coating) is used to form described first Metal Substrate photoresist layer
111.In the present embodiment, the material of described first Metal Substrate photoresist layer 111 is titanium oxide；Described first gold medal
The thickness belonging to base photoresist layer 111 is 50 angstroms to 500 angstroms.
It is the schematic diagram on the basis of Figure 10 with reference to Figure 11, Figure 11, to described first Metal Substrate photoresist layer
111 carry out photoetching treatment, form the first opening 112, and institute in described first Metal Substrate photoresist layer 111
State the first opening 112 to be positioned at above doped region 105.
Described first opening 112 defines the positions and dimensions of the doped region contact hole being subsequently formed.Follow-up
Top dielectric layer 109 and interlayer dielectric layer 106 is etched, at interlayer dielectric layer 106 along the first opening 112
Middle formation the second opening, described second opening is positioned at above doped region 105, the second opening as with doping
The doped region contact hole of district 105 electrical connection.
Described photoetching treatment includes exposure-processed and development treatment.Described first Metal Substrate photoresist layer 111
Material be metal-oxide, and described metal-oxide includes that metal ion coordinates base even with photaesthesia
The chemical bond connect, also includes the chemical bond that metal ion is connected with hydroxyl group.In the present embodiment, institute
The material stating the first Metal Substrate photoresist layer 111 is titanium oxide, and the material of the first Metal Substrate photoresist layer 111 is negative
Property photoresistance (negative resist) material.The material of the first Metal Substrate photoresist layer 111 include titanium ion with
Photaesthesia coordinates the chemical bond that base (ligand) connects, and also includes the chemistry that titanium ion is connected with hydroxyl group
Key.
Concrete, it is exposed the first Metal Substrate photoresist layer 111 processing, in exposure process first
Metal Substrate photoresist layer 111 is divided into exposure area and non-exposed areas, the first Metal Substrate photoresistance of exposure area
The material of layer 111 changes, and the material of the first Metal Substrate photoresist layer 111 of exposure area is by hydrophilic material
Material becomes hydrophobic material；The first Metal Substrate photoresist layer 111 after exposure-processed is carried out development treatment,
First Metal Substrate photoresist layer 111 of exposure area keeps constant in development process, and non-exposed area
The first Metal Substrate photoresist layer 111 in territory dissolves in development process, thus at the first Metal Substrate photoresistance
Layer 111 forms the first opening 112.
Compared with carrying out photoetching treatment with to traditional Other substrate materials, to the first Metal Substrate light in the present embodiment
After resistance layer 111 is exposed processing, it is possible to form the first smaller opening 112, and adjacent first opens
Distance between mouth 112 is the least, makes the first opening 112 maintain higher position precision and tool simultaneously
There is good profile pattern.Concrete, in the present embodiment, on described fin 101 bearing of trend, i.e. fin
Portion 101 side doped region 105 points on the direction of the relative opposite side doped region 105 of fin 101, described
The size of the first opening 112 is 100 angstroms to 1000 angstroms, and the distance between adjacent first opening 112 is 500
Angstrom to 5000 angstroms.
Therefore, the size of follow-up the second opening formed above doped region 105 can be accomplished less, the
The size of two openings is 100 angstroms to 1000 angstroms, and therefore the size of doped region 105 can also be less, doping
The size on surface, district 105 is 100 angstroms to 1000 angstroms.Distance between adjacent second opening being subsequently formed
Can also accomplish the least, the distance between adjacent second opening is 500 angstroms to 5000 angstroms, therefore fin 101
Distance between the doped region 105 of both sides can also be 500 angstroms to 5000 angstroms, is meeting device miniaturization
While miniaturization trend, the second opening being subsequently formed also will have higher alignment precision and good
Good profile pattern.
After forming the first opening 112 in the first Metal Substrate photoresist layer 111, if the chi of the first opening 112
Very little too small, the first opening 112 is projected on the figure on doped region 105 surface and is not completely covered by doped region 105
Surface, then, after forming described first opening 112, further comprise the steps of: and have the first opening to described
The first Metal Substrate photoresist layer 111 of 112 carries out repairing (trim) and processes, thus adjusts the first opening 112
Size and position so that the first opening 112 is projected on the figure on doped region 105 surface and is completely covered
In doped region 105 surface.
In a specific embodiment, to the described first Metal Substrate photoresist layer 111 with the first opening 112
The technological parameter carrying out finishing process is: O2Flow is 10sccm to 100sccm, CO2Flow is 10sccm
To 100sccm, NH3Flow is 0sccm to 100sccm, chamber pressure be 10 millitorrs to 100 millitorrs,
There is provided source power 50 watts to 500 watts, it is provided that bias power 0 watt to 200 watts.
Use above-mentioned technological parameter that the first Metal Substrate photoresist layer 111 is carried out finishing process, enough avoid
Top dielectric layer 109 bottom one opening 112 causes etching, and trim process is to the first Metal Substrate light
The etch rate of resistance layer 111 is moderate, prevents due to too fast to the etch rate of the first Metal Substrate photoresist layer 111
And over etching occurs.
Being the schematic diagram on the basis of Fig. 9 referring to figs 12 to Figure 13, Figure 12, Figure 13 is at Figure 11 base
Schematic diagram on plinth, etches described top dielectric layer 109 along described first opening 112 (with reference to Figure 11)
And interlayer dielectric layer 106, formed in described interlayer dielectric layer 106 and expose doped region 105 surface
Second opening 113.
In the present embodiment, use dry etch process, along the first opening 112 etch top dielectric layer 109,
Etching barrier layer 108 and interlayer dielectric layer 106, form described second opening 113.Described 3rd opening
113 as doped region contact hole, the follow-up full conductive layer of filling in the 3rd opening 113, thus is formed and mix
The doped region metal plug of miscellaneous district 105 electrical connection.
Due to the size of the first opening 112 can do the least, the second opening 113 of being therefore correspondingly formed
Size can also do the least, meet semiconductor device miniaturization miniaturization development trend.Further,
Due to the distance of adjacent first opening 112 can do the least, to this end, NMOS area in the present embodiment
It is the least that the distance of adjacent first opening 112 that the same grid structure of I is corresponding can be done, same, PMOS
It is the least that distance between adjacent first opening 112 that II same grid structure in region is corresponding can be done.With
Time, owing to the sidewall roughness of the first opening 112 is less, the second opening therefore formed in the present embodiment
The sidewall profile of 113 is good, thus is conducive to improving the follow-up conductive layer formed in the second opening 113
Quality, and then improve the electric property of semiconductor device.
In the present embodiment, along fin 101 bearing of trend, the size of described second opening 113 is 100
Angstrom to 1000 angstroms；Along fin 101 bearing of trend, adjacent second opening that same grid structure is corresponding
The distance of 113 is 500 angstroms to 5000 angstroms.
During etching forms the 3rd opening 113, the side wall 107 being positioned at grid structure both sides plays
The effect of protection grid structure, and described side wall 107 and be positioned at the etching on grid conductive layer 104 surface
Barrier layer 108 can also form the part of mask for the 3rd opening 113 as etching, described side wall 107,
The etching barrier layer 108 and the first Metal Substrate photoresist layer 111 that are positioned at grid conductive layer 104 surface are made jointly
For forming autoregistration (self aligned) mask of the 3rd opening 113.
After forming described second opening 113, remove described first Metal Substrate photoresist layer 111 (with reference to figure
11 to Figure 12).In the present embodiment, use wet-etching technology, remove described first Metal Substrate photoresist layer
111, the etch liquids of described wet-etching technology is the aqueous solution of ammonia and hydrogen peroxide.
With reference to figs. 14 to Figure 15, form the conductive layer filling full described second opening 113 (with reference to Figure 13)
114, Figure 14 is the schematic diagram on the basis of Figure 12, and Figure 15 is the schematic diagram on the basis of Figure 13.
In the present embodiment, while forming the conductive layer 114 filling full described second opening 113, institute
State conductive layer 114 and also fill up the most described 3rd opening 110 (with reference to Figure 12).
It is positioned at the conductive layer 114 of the second opening 113 as doped region metal plug, described doped region gold
Belong to connector to electrically connect with doped region 105；The conductive layer 114 being positioned at the 3rd opening 110 is tied as grid
Structure metal plug, described grid structure metal plug electrically connects with grid structure.The present embodiment concurrently forms
Doped region metal plug and grid structure metal plug, conductive layer 114 fills full second opening 113 simultaneously
With the 3rd opening 110, therefore can save processing step, and then the production of reduction formation semiconductor device becomes
This.
The material of described conductive layer 114 is copper, aluminum, tungsten, titanium or tantalum.In the present embodiment, described conduction
The material of layer 114 is tungsten.
In the present embodiment, due to the size of the first opening 112 can do the least, be therefore correspondingly formed
It is the least that the size of the second opening 113 can also be done, and meets the development of semiconductor device miniaturization miniaturization
Trend.Further, due to the distance of adjacent first opening 112 can do the least, to this end, the present embodiment
Distance between the adjacent doped region 105 that the same grid structure of middle NMOS area I is corresponding can be done very
Little, same, distance between the adjacent doped region 105 that the same grid structure of PMOS area II is corresponding
That can do is the least.Simultaneously as the sidewall roughness of the first opening 112 is less, therefore the present embodiment
The sidewall profile of the second opening 113 of middle formation is good, thus advantageously forms high-quality conductive layer 114,
And then improve the electric property of semiconductor device；And the alignment precision of the second opening 113 formed is high, makes
Obtain, between adjacent conductive layer 114, there is good electrical insulation capability.
It addition, the present embodiment has only carried out a photoetching treatment, it becomes possible to square on doped region 105
Become high-quality second opening 113.The second opening is formed comparatively speaking with using Dual graphing method, this
The forming method of the semiconductor device that embodiment provides decreases production cost, shortens the production cycle, and
And avoid repeatedly photoetching treatment it is possible that position alignment offset issue so that the quasiconductor of formation
The yield of device is improved.
Figure 16 to Figure 20 shows for the structure of the semiconductor device forming process that another embodiment of the present invention provides
It is intended to.
In conjunction with referring to figs. 1 to Fig. 8, it is provided that substrate；Grid structure is formed at described substrate surface；Form position
Side wall 107 in described gate structure sidewall surface；Doping is formed in the substrate of described grid structure both sides
District 105；Forming interlayer dielectric layer 106 at described substrate surface, described interlayer dielectric layer 106 is positioned at grid
Structure side wall surface, and interlayer dielectric layer 106 top flushes with grid structure top；Etching removal is positioned at
The grid conductive layer 104 of the segment thickness directly over fin 101；Formed on remaining grid conductive layer 104 surface
Etching barrier layer 108；Top dielectric is formed on described interlayer dielectric layer 106 surface and grid structure surface
Layer 109；Forming the 3rd opening 110 in described top dielectric layer 109, described 3rd opening 110 is positioned at
Above grid structure.
Being the schematic diagram on the basis of Fig. 8 referring to figures 16 to Figure 17, Figure 16, Figure 17 is on Fig. 7 basis
On schematic diagram, described top dielectric layer 109 surface formed Metal Substrate photoresist layer.
In the present embodiment, described Metal Substrate photoresist layer is laminated construction, and described Metal Substrate photoresist layer includes
One Metal Substrate photoresist layer 201 and be positioned at the second Metal Substrate photoresistance on the first Metal Substrate photoresist layer 201 surface
Layer 202, wherein, described first Metal Substrate photoresist layer 201 also fills up the most described 3rd opening 110 (reference
Fig. 8).
Metal Substrate photoresist layer is laminated construction, and wherein, the first Metal Substrate photoresist layer primarily serves filling full the
The effect of three openings 110, for forming the interface basis that the second Metal Substrate photoresist layer 202 provides good, makes
The surface flatness of the second Metal Substrate photoresist layer 202 that must be formed is higher, the second Metal Substrate photoresist layer 202
Surface flatness higher than the surface flatness of the first Metal Substrate photoresist layer 201 so that follow-up to the
The lithographic accuracy that two Metal Substrate photoresist layers 202 carry out photoetching treatment gets a promotion.
The material of described first Metal Substrate photoresist layer 201 is titanium oxide, zirconium oxide, tungsten oxide or aluminium oxide；
The material of described second Metal Substrate photoresist layer 202 is titanium oxide, zirconium oxide, tungsten oxide or aluminium oxide.This
In embodiment, the material of described first Metal Substrate photoresist layer 201 and described second Metal Substrate photoresist layer 202
Material different, so that subsequent etching processes is to the first Metal Substrate photoresist layer 201 and the second Metal Substrate
The etch rate of photoresist layer 202 is different.
In a specific embodiment, the material of described first Metal Substrate photoresist layer 201 is zirconium oxide, thick
Degree is 50 angstroms to 500 angstroms；The material of described second Metal Substrate photoresist layer 202 is titanium oxide, and thickness is 50
Angstrom to 500 angstroms.
With reference to Figure 18, described second Metal Substrate photoresist layer 202 is carried out photoetching treatment, formed and run through described
First opening 203 of the second Metal Substrate photoresist layer 202, described first opening 203 is positioned on doped region 105
Side, Figure 18 is the schematic diagram on the basis of Figure 16.
Described photoetching treatment includes exposure-processed and development treatment.Description about photoetching treatment refers to
The explanation of previous embodiment, does not repeats them here.
It is smaller that described first opening 203 is sized to do, and, it is positioned at same grid structure pair
It is smaller that distance between adjacent first opening 203 answered can be done, so that same fin 101
It is smaller that the corresponding distance between adjacent doped region 105 can be done, and meets semiconductor device miniaturization
The development trend of miniaturization.
Along fin 101 bearing of trend, the size of described first opening 203 is 100 angstroms to 1000 angstroms,
Distance between adjacent first opening 203 is 500 angstroms to 5000 angstroms.
Further, in the present embodiment, the first Metal Substrate photoresist layer 201 fills full 3rd opening 110, then exists
First Metal Substrate photoresist layer 201 surface forms the second Metal Substrate photoresist layer 202, therefore in the present embodiment second
Metal Substrate photoresist layer 202 surface has relatively high flat degree, it is to avoid it is unnecessary to occur in lithographic processes
Reflection, thus improve lithographic accuracy so that position and the pattern of the first opening 203 of formation are more accurate.
Referring to figures 19 through Figure 20, etch described first metal along described first opening 203 (with reference to Figure 18)
Base photoresist layer 201 (referring to figures 16 to Figure 18), until exposing top dielectric layer 109 surface；Along institute
State the first opening 203 and etch described top dielectric layer 109 and interlayer dielectric layer 106, be situated between at described interlayer
Forming the second opening 204 in matter layer 106, Figure 19 is the schematic diagram on the basis of Figure 16, Figure 20 be
Schematic diagram on the basis of Figure 18.
Along fin 101 bearing of trend, the size of described second opening 204 is 100 angstroms to 1000 angstroms,
Distance between adjacent second opening 204 is 500 angstroms to 5000 angstroms.
In the present embodiment, the gas etching described first Metal Substrate photoresist layer 201 is BCl3, BCl3 is to
The etch rate of one Metal Substrate photoresist layer 201 is big, and the etch rate to the second Metal Substrate photoresist layer 202
Little, therefore, it is possible to the second Metal Substrate photoresist layer 202 as mask, the first Metal Substrate photoresist layer 201 is entered
Row etching.The etching gas etching described top dielectric layer 109 and interlayer dielectric layer 106 is CF4,
CF4 is big to the etch rate of top dielectric layer 109 and interlayer dielectric layer 106, and to the first Metal Substrate
The etch rate of photoresist layer 201 and the second Metal Substrate photoresist layer 202 is little.
In the present embodiment, the technological parameter etching described first Metal Substrate photoresist layer 201 is: BCl3Flow
For 50sccm to 300sccm, Cl2Flow is 10sccm to 200sccm, CH4Flow be 0sccm extremely
100sccm, chamber pressure is that 10 millitorrs are to 200 millitorrs, it is provided that source power 100 watts, to 1000 watts, carries
For bias power 0 watt to 300 watts.
Above-mentioned technological parameter is used to etch the first Metal Substrate photoresist layer 201, it is possible to make the first metal after etching
Base photoresist layer 201 sidewall profile is good, and then makes the sidewall of the second opening 204 that subsequent etching formed
Pattern is good.
In the present embodiment, etch described top dielectric layer 109 and the technological parameter of interlayer dielectric layer 106
For: CHF3Flow be 10sccm to 100sccm, CF4Flow be 10sccm to 200sccm,
CH2F2Flow be 0sccm to 100sccm, chamber pressure is that 10 millitorrs are to 200 millitorrs, it is provided that source
Power 100 watts to 1000 watts, it is provided that bias power 0 watt to 300 watts.
Use above-mentioned technological parameter etching top dielectric layer 109 and interlayer dielectric layer 106, it is possible to make shape
The second opening 204 sidewall profile become is good, and above-mentioned etching technics to top dielectric layer 109 and
The etch rate of interlayer dielectric layer 106 is big, and the least to the etch rate of doped region 105, therefore can
Doped region 105 is enough made to be exposed to etch the time in environment short, additionally it is possible to avoid etching technics to doping
District 105 causes over etching so that doped region 105 remains superperformance.
After forming described second opening 204, use wet-etching technology, remove described first metal
Base photoresist layer 201 and the second Metal Substrate photoresist layer 202.In a specific embodiment, described wet method is carved
The etch liquids of etching technique is the mixed solution of hydrogen peroxide and ammonia.
Follow-up processing step includes: is formed and fills leading of full described second opening 204 (with reference to Figure 20)
Electric layer；While forming the conductive layer filling full second opening 204, described conductive layer also fills up full the
Three openings 110 (with reference to Figure 19).
Description about conductive layer refers to conductive layer 114 (with reference to Figure 15 to Figure 16) in previous embodiment
Description, do not repeat them here.
It is excellent that in the present embodiment, the second opening 204 of formation not only has that size is little, line width roughness is little
Point, and due to when the second Metal Substrate photoresist layer 202 is carried out photoetching treatment, it is to avoid photoetching treatment
During occur unnecessary reflection and scattering so that be positioned in the second Metal Substrate photoresist layer 202
The position precision of the first opening 203 and pattern degree of accuracy higher, and then make formed second to open
Position precision and the pattern degree of accuracy of mouth 204 are higher so that the quality of the conductive layer of formation is entered
One step improves, thus improves electric property and the yield of the semiconductor device of formation further.
Figure 21 to Figure 28 shows for the structure of the semiconductor device forming process that further embodiment of this invention provides
It is intended to.
In conjunction with referring to figs. 1 to Fig. 8, it is provided that substrate；Grid structure is formed at described substrate surface；Form position
Side wall 107 in described gate structure sidewall surface；Doping is formed in the substrate of described grid structure both sides
District 105；Forming interlayer dielectric layer 106 at described substrate surface, described interlayer dielectric layer 106 is positioned at grid
Structure side wall surface, and interlayer dielectric layer 106 top flushes with grid structure top；Etching removal is positioned at
The grid conductive layer 104 of the segment thickness directly over fin 101；Formed on remaining grid conductive layer 104 surface
Etching barrier layer 108；Top dielectric is formed on described interlayer dielectric layer 106 surface and grid structure surface
Layer 109；Forming the 3rd opening 110 in described top dielectric layer 109, described 3rd opening 110 is positioned at
Above grid structure.
Being the schematic diagram on the basis of Fig. 8 with reference to figures 21 to Figure 22, Figure 21, Figure 22 is on Fig. 7 basis
On schematic diagram, form the first Metal Substrate photoresist layer 301 on described top dielectric layer 109 surface.
In the present embodiment, described first Metal Substrate photoresist layer 301 also fills up the most described 3rd opening 110.Institute
The material stating the first Metal Substrate photoresist layer 301 is titanium oxide, zirconium oxide, tungsten oxide, zinc oxide or oxidation
Aluminum.
In the present embodiment, the material of described first Metal Substrate photoresist layer 301 is titanium oxide, described first gold medal
The thickness belonging to base photoresist layer 301 is 50 angstroms to 500 angstroms.
It is the schematic diagram on the basis of Figure 22 with reference to Figure 21 and Figure 23, Figure 23, to described first Metal Substrate
Photoresist layer 301 carries out the first photoetching treatment, forms groove 302 in described first Metal Substrate photoresist layer 301.
The described groove 302 interlayer dielectric layer above doped region 105, between adjacent doped region 105
Above in the of 106, therefore, the size of described groove 302 is relatively big, so that the technique of the first photoetching treatment is difficult
Spend relatively low.Further, there is described in the first Metal Substrate photoresist layer 301 of groove 302 fill out and be filled with the 3rd and open
Mouth 110 (with reference to Fig. 8), provides good for the second Metal Substrate photoresist layer being subsequently formed surface topography good
Good interface basis so that the second Metal Substrate photoresist layer surface flatness of formation is high, so that follow-up
The lithographic accuracy that second Metal Substrate photoresist layer carries out the second photoetching treatment is improved.
Being the schematic diagram on the basis of Figure 21 with reference to Figure 24 to Figure 25, Figure 24, Figure 25 is at Figure 23 base
Schematic diagram on plinth, after forming described groove 302 (with reference to Figure 23), in described first Metal Substrate
Photoresist layer 301 top surface and sidewall surfaces form cured layer 303；After forming described cured layer 303,
Form the second Metal Substrate photoresist layer 304 filling full described groove 302.
Described cured layer 303 play prevent the first Metal Substrate photoresist layer 301 be exposed to follow-up carry out second
In photoetching treatment environment so that the second Metal Substrate photoresist layer 302 is only carried out by the second follow-up photoetching treatment.
Therefore, the material of described cured layer 303 is the material that light-proofness is strong, in the present embodiment, and described cured layer
The material of 303 is silicon.
In the present embodiment, described cured layer 303 is also located at bottom groove 302, thus reduces formation solidification
The technology difficulty of layer 303, rear extended meeting etching is removed and is positioned at bottom groove 302 and the cured layer of sidewall surfaces
303。
The method forming described cured layer 303 includes: described substrate is placed in process chamber, and processes
Chamber inner wall material includes silicon；Thering is provided plasma, described plasma is in the effect of DC offset voltage
Lower bombardment processing chamber inner wall, makes the silicon atom of process chamber inner wall come off, described in the silicon atom that comes off attached
In the lower surface of groove 302 and sidewall surfaces, form described cured layer 303.
Concrete, can be by plasmarized for Ar formation Ar plasma, at the work of DC offset voltage
Under with, Ar plasma bombardment processes chamber inner wall；Or, can be by N2Plasmarized formation N
Plasma, under the effect of DC offset voltage, N plasma bombardment processes chamber inner wall.
It should be noted that in the present embodiment, the mesh that plasma bombards under DC offset voltage effect
It is designated as processing chamber inner wall, it is therefore desirable to according to the positive negativity of plasma-charge, determines direct current biasing electricity
The positive negativity of pressure, so that plasma bombards, without to top dielectric processing chamber inner wall
Layer 109 and the first Metal Substrate photoresist layer 301 bombard.
In the present embodiment, the technological parameter forming described cured layer 303 is: N2Flow be 0sccm extremely
200sccm, Ar flow is 50sccm to 500sccm, process chamber pressure be 10 millitorrs to 200 millitorrs,
There is provided plasma rf power be 100 watts to 500 watts, it is provided that biasing radio-frequency power be 0 watt to 200
Watt, it is provided that DC offset voltage be-50V to-400V.
Wherein, to be-50V be, at described DC offset voltage to the meaning of-400V DC offset voltage
Under effect, N plasma, Ar plasma bombardment are positioned at the process chamber directly over dielectric layer 103
Wall, under the effect of DC offset voltage, plasma obtains to bombard and is positioned at groove 302 and first
The kinetic energy of chamber inner wall is processed directly over Metal Substrate photoresist layer 301.
In other embodiments, if the material processing chamber inner wall does not include silicon atom, then cured layer is formed
Method include: provide silicon target, using plasma bombards silicon target under the effect of direct current biasing power
Material, make silicon atom come off from silicon target be attached to the first Metal Substrate photoresist layer surface, the bottom of groove and
Sidewall, thus form cured layer.
The material of described second Metal Substrate photoresist layer 302 is titanium oxide, zirconium oxide, tungsten oxide, zinc oxide
Or aluminium oxide.In the present embodiment, the material of described second Metal Substrate photoresist layer 302 is zirconium oxide, second
The thickness of Metal Substrate photoresist layer 302 is 50 angstroms to 500 angstroms.
Owing to the second Metal Substrate photoresist layer 302 is without filling the 3rd opening 110 (with reference to Fig. 8), and formed
The interface flat degree of the second Metal Substrate photoresist layer 302 is high, so that the second Metal Substrate photoresist layer formed
302 lower surface and top surface are respectively provided with higher flatness.
With reference to Figure 24 and Figure 26, described second Metal Substrate photoresist layer 304 is carried out the second photoetching treatment,
Described second Metal Substrate photoresist layer 304 is formed the first opening 305, and described first opening 305 is positioned at and mixes
Above miscellaneous district 105.
Described second photoetching treatment includes exposure-processed and development treatment.Due to the present embodiment formed the
Two Metal Substrate photoresist layer 302 lower surface and top surface are respectively provided with higher flatness, therefore to second
The lithographic accuracy that Metal Substrate photoresist layer 302 carries out the second photoetching treatment is high so that the first opening 305 of formation
There is good position precision, and there is good pattern.
After forming the first opening 305, it is also possible to described second metal with the first opening 305
Base photoresist layer 302 carries out finishing process, adjusts size and the position of the first opening 305, relevant finishing
The description processed refers to previous embodiment, does not repeats them here.
Being the schematic diagram on the basis of Figure 24 with reference to Figure 27 to Figure 28, Figure 27, Figure 28 is at Figure 26 base
Schematic diagram on plinth, etches described top dielectric layer 109 and inter-level dielectric along described first opening 305
Layer 106, forms the second opening 306 exposing doped region 105 surface in described interlayer dielectric layer 106.
During etching described top dielectric layer 109 and interlayer dielectric layer 106, also etch removal
It is positioned at the cured layer 303 (with reference to Figure 26) of groove 302 (with reference to Figure 23) sidewall surfaces, and etching is removed
It is positioned at the cured layer 303 below the first opening 305.
Position precision due to aforementioned the first opening 305 formed in the second Metal Substrate photoresist layer 304
Height and pattern are good, and therefore corresponding the second opening 306 formed in interlayer dielectric layer 106 also will have
Good position precision and pattern, thus improve electric property and the yield of semiconductor device further.
Further, it is the least that the size of described second opening 306 can be done, and between adjacent second opening 306
It is the least that distance can be done, and the distance between the adjacent doped region 105 of the most same fin 101 correspondence is also
That can do is less, thus meets the development trend of device miniaturization miniaturization.
Remove described first Metal Substrate photoresist layer 301 (with reference to Figure 25 to Figure 26) and the second Metal Substrate light
Resistance layer 304 (with reference to Figure 25 to Figure 26), removes remaining cured layer 303.
Follow-up processing step includes: form the conductive layer filling full described second opening 306；Formed
While filling the conductive layer of full second opening 306, also form the conductive layer filling full 3rd opening 110.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (20)
1. the forming method of a semiconductor device, it is characterised in that including:
Thering is provided substrate, described substrate surface is formed with grid structure, in the substrate of described grid structure both sides
Being formed with doped region, described substrate surface is also formed with interlayer dielectric layer, and described interlayer dielectric layer is positioned at grid
Electrode structure sidewall surfaces, and described interlayer dielectric layer top flushes with grid structure top；
Top dielectric layer is formed on described interlayer dielectric layer surface and grid structure top surface；
Metal Substrate photoresist layer is formed on described top dielectric layer surface；
Described Metal Substrate photoresist layer is carried out photoetching treatment, described Metal Substrate photoresist layer is formed first and opens
Mouthful, and described first opening is positioned at above doped region；
Described top dielectric layer and interlayer dielectric layer is etched, at described inter-level dielectric along described first opening
The second opening exposing doped region surface is formed in Ceng；
Remove described Metal Substrate photoresist layer；
Form the conductive layer filling full described second opening.
2. the forming method of semiconductor device as claimed in claim 1, it is characterised in that forming described gold
Before belonging to base photoresist layer, forming the 3rd opening in described top dielectric layer, described 3rd opening exposes
Go out grid structure top；Described Metal Substrate photoresist layer also fills up the most described 3rd opening；Fill being formed
While the conductive layer of full described second opening, described conductive layer also fills up the most described 3rd opening.
3. the forming method of semiconductor device as claimed in claim 2, it is characterised in that described substrate includes:
Substrate, it is positioned at the some discrete fin of substrate surface, is positioned at the isolation of the substrate surface of fin both sides
Layer, described sealing coat is covered in fin sidewall surfaces, and described sealing coat top is less than fin top,
Wherein, described grid structure is positioned at insulation surface and across at least one fin, described grid structure
Cover top and the sidewall of fin.
4. the forming method of semiconductor device as claimed in claim 3, it is characterised in that described 3rd opening
It is positioned at above the sealing coat adjacent with described fin；Described 3rd opening exposes the grid above sealing coat
Electrode structure top.
5. the forming method of the semiconductor device as described in claim 1 or 3, it is characterised in that described metal
The material of base photoresist layer is titanium oxide, zirconium oxide, tungsten oxide, zinc oxide or aluminium oxide.
6. the forming method of the semiconductor device as described in claim 1 or 3, it is characterised in that described photoetching
Process includes exposure-processed and development treatment.
7. the forming method of the semiconductor device as described in claim 1 or 3, it is characterised in that forming institute
Before stating top dielectric layer, further comprise the steps of: at described interlayer dielectric layer and grid structure top table
Face forms etching barrier layer.
8. the forming method of the semiconductor device as described in claim 1 or 3, it is characterised in that described metal
Base photoresist layer is single layer structure；Described Metal Substrate photoresist layer is the first Metal Substrate photoresist layer；Described first
Opening runs through described first Metal Substrate photoresist layer.
9. the forming method of the semiconductor device as described in claim 1 or 3, it is characterised in that described metal
Base photoresist layer is laminated construction；Described Metal Substrate photoresist layer includes the first Metal Substrate photoresist layer and is positioned at
The second Metal Substrate photoresist layer on the first Metal Substrate photoresist layer surface.
10. the forming method of semiconductor device as claimed in claim 9, it is characterised in that to described Metal Substrate
Photoresist layer carries out the method for photoetching treatment: described second Metal Substrate photoresist layer is carried out photoetching treatment,
Described first opening runs through described second Metal Substrate photoresist layer.
The forming method of 11. semiconductor device as claimed in claim 9, it is characterised in that on etching is described
Before layer dielectric layer and interlayer dielectric layer, further comprise the steps of: along described first opening etching described the
One Metal Substrate photoresist layer, until exposing top dielectric layer surface.
The forming method of 12. semiconductor device as claimed in claim 9, it is characterised in that described first metal
The material of base photoresist layer is zirconium oxide；The material of described second Metal Substrate photoresist layer is titanium oxide.
The forming method of 13. semiconductor device as claimed in claim 12, it is characterised in that etch described first
The technological parameter of Metal Substrate photoresist layer is: BCl3Flow is 50sccm to 300sccm, Cl2Flow is
10sccm to 200sccm, CH4Flow is 0sccm to 100sccm, chamber pressure be 10 millitorrs extremely
200 millitorrs, it is provided that source power 100 watts to 1000 watts, it is provided that bias power 0 watt to 300 watts.
The forming method of 14. semiconductor device as claimed in claim 12, it is characterised in that etch described upper strata
The technological parameter of dielectric layer and interlayer dielectric layer is: CHF3Flow is 10sccm to 100sccm,
CF4Flow is 10sccm to 200sccm, CH2F2Flow is 0sccm to 100sccm, chamber pressure
It it is by force that 10 millitorrs are to 200 millitorrs, it is provided that source power 100 watts to 1000 watts, it is provided that bias power 0
Watt to 300 watts.
The forming method of 15. semiconductor device as described in claim 1 or 3, it is characterised in that use wet method
Etching technics removes described Metal Substrate photoresist layer；Spin coating process is used to form described Metal Substrate photoresistance
Layer.
The forming method of 16. semiconductor device as claimed in claim 3, it is characterised in that along described fin
On bearing of trend, the size of described first opening is 100 angstroms to 1000 angstroms, between adjacent first opening
Distance be 500 angstroms to 5000 angstroms.
The forming method of 17. 1 kinds of semiconductor device, it is characterised in that including:
Thering is provided substrate, described substrate surface is formed with grid structure, in the substrate of described grid structure both sides
Being formed with doped region, described substrate surface is also formed with interlayer dielectric layer, and described interlayer dielectric layer is positioned at grid
Electrode structure sidewall surfaces, and described interlayer dielectric layer top flushes with grid structure top；
Forming top dielectric layer at described interlayer dielectric layer and grid structure top surface, described upper strata is situated between
Matter layer is formed the 3rd opening exposing grid structure；
Formed and fill full described 3rd opening and be positioned at the first Metal Substrate photoresist layer on top dielectric layer surface；
Described the first Metal Substrate photoresist layer being positioned at top dielectric layer surface is carried out the first photoetching treatment,
Forming groove in described first Metal Substrate photoresist layer, described groove is positioned at above doped region and adjacent mixes
Above interlayer dielectric layer between miscellaneous district；
After forming described groove, in described first Metal Substrate photoresist layer top surface and sidewall surfaces shape
Become cured layer；
After forming described cured layer, form the second Metal Substrate photoresist layer filling full described groove；
Described second Metal Substrate photoresist layer is carried out the second photoetching treatment, at described second Metal Substrate photoresist layer
Middle formation the first opening, and described first opening is positioned at above doped region；
Described top dielectric layer and interlayer dielectric layer is etched, at described inter-level dielectric along described first opening
The second opening exposing doped region surface is formed in Ceng；
Remove described first Metal Substrate photoresist layer and the second Metal Substrate photoresist layer；
Form the conductive layer filling full described second opening.
The forming method of 18. semiconductor device as claimed in claim 17, it is characterised in that described first metal
The material of base photoresist layer is titanium oxide, zirconium oxide, tungsten oxide, zinc oxide or aluminium oxide；Described second
The material of Metal Substrate photoresist layer is titanium oxide, zirconium oxide, tungsten oxide, zinc oxide or aluminium oxide；Described
The material of cured layer is silicon.
The forming method of 19. semiconductor device as claimed in claim 17, it is characterised in that described substrate includes:
Substrate, it is positioned at the some discrete fin of substrate surface, is positioned at the isolation of the substrate surface of fin both sides
Layer, described sealing coat is covered in fin sidewall surfaces, and described sealing coat top is less than fin top,
Wherein, described grid structure is positioned at insulation surface and across at least one fin, described grid structure
Cover top and the sidewall of fin.
The forming method of 20. semiconductor device as claimed in claim 19, it is characterised in that described 3rd opening
It is positioned at above the sealing coat adjacent with described fin；Described 3rd opening exposes the grid above sealing coat
Electrode structure top.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101727000A (en) * | 2008-10-27 | 2010-06-09 | 株式会社东进世美肯 | Photoresist composition |
| US20140199837A1 (en) * | 2013-01-14 | 2014-07-17 | United Microelectronics Corp. | Method of forming semiconductor structure having contact plug |
| CN104217964A (en) * | 2013-06-05 | 2014-12-17 | 中芯国际集成电路制造(上海)有限公司 | Forming method of conductive plug |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101727000A (en) * | 2008-10-27 | 2010-06-09 | 株式会社东进世美肯 | Photoresist composition |
| US20140199837A1 (en) * | 2013-01-14 | 2014-07-17 | United Microelectronics Corp. | Method of forming semiconductor structure having contact plug |
| CN104217964A (en) * | 2013-06-05 | 2014-12-17 | 中芯国际集成电路制造(上海)有限公司 | Forming method of conductive plug |
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