CN106252286B - The selection method of the polysilicon dry etching process of embedded flash memory - Google Patents
The selection method of the polysilicon dry etching process of embedded flash memory Download PDFInfo
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- CN106252286B CN106252286B CN201610885898.4A CN201610885898A CN106252286B CN 106252286 B CN106252286 B CN 106252286B CN 201610885898 A CN201610885898 A CN 201610885898A CN 106252286 B CN106252286 B CN 106252286B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
Abstract
A kind of selection method of the polysilicon dry etching process of embedded flash memory, the described method comprises the following steps: providing the domain of the active area of the embedded flash memory and the domain of floating gate region；According to the domain of the domain of the active area and floating gate region, determine that the layout density of the practical etching area of the active area and the floating gate region, the practical etching area are the region that polysilicon is etched by dry etching process；According to the layout density in the practical reproduction region and the preset thickness of oxide layer after the etching under the polysilicon, corresponding dry etching process is selected.The present invention program can select suitable polysilicon dry etching process according to the layout density of the practical etching area of polysilicon, to accurately be controlled floating gate sharp distal tip, to improve flash memory performance.
Description
Technical field
The present invention relates to field of semiconductor fabrication processes, the polysilicon dry etching process of especially a kind of embedded flash memory
Selection method.
Background technique
In embedded flash memory, the height and sharpness of floating gate sharp distal tip will affect floating gate coupling when programming, erasable
The voltage of conjunction, and then influence performance of flash memory when programming, erasable.Therefore, accurately control floating gate sharp distal tip dodges control
The performance deposited is of great significance.In concrete technology implementation, polysilicon dry etching process (Poly Dry-Etch) can be passed through
Remain the precise degrees of the thickness of oxide layer (such as silica, silicon nitride etc.) on the active area afterwards to know floating gate tip
Whether tip is accurate.
It in the prior art, can be close according to the layout density of active area or the domain of floating gate region for determining product
Degree, and the preset thickness of oxide layer after the etching under the polysilicon select polysilicon dry etching process.This be because
For according to the load effect (loading effect) of etch process it is found that the etch-rate ratio in the biggish region of reaction density
The lesser region of density is slow, i.e. the polysilicon of actual needs progress dry ecthing is more, and occupied area is bigger, can choose etching speed
The etch process that rate is faster, etching period is longer or etch temperature is higher.Wherein it is possible to chip area and production by region
The area of whole domain of product is divided by, to obtain the layout density in the region.
It more specifically, can be according to the layout density of active area or the layout density of floating gate region, to needing to carry out dry corrosion
The area of the polysilicon at quarter is judged in advance.Specifically, the layout area of embedded flash memory includes memory area and logic
Region, in memory area, the territory pattern of active area and floating gate region is evenly distributed namely active area or floating gate region
The area of chip area and the polysilicon for needing to be etched has the chip area of linear relationship, the active area or floating gate region
Bigger, the area for needing to carry out the polysilicon of dry ecthing is also bigger.
It is possible to further according to the size of the layout density of the layout density or floating gate region of active area, in conjunction with oxide layer
Preset thickness after the etching selects polysilicon dry etching process.
But for new product, only by the domain of active area, or only pass through the domain of floating gate region, it is difficult to by pre-
Judgement selects correct dry etching process, and the oxidated layer thickness obtained is caused not meet expection, the control of floating gate sharp distal tip
It is inaccurate.This is because in logic region, the territory pattern and uneven arrangement, i.e. active area of active area and floating gate region
Or the area of polysilicon that the chip area of floating gate region and needs are etched is non-linear relation namely active area or floating gate region
The big product of chip area, the area for needing to carry out the polysilicon of dry ecthing but may not be big.The characteristics of this non-linear relation,
It is expressively more prominent for product biggish for logic region area ratio.
Summary of the invention
The technical problem to be solved by the present invention is to provide a kind of selection method of the polysilicon dry etching process of embedded flash memory,
Suitable polysilicon dry etching process can be selected, thus to floating gate according to the layout density of the practical etching area of polysilicon
The pattern of sharp distal tip is accurately controlled, to improve flash memory performance.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of polysilicon dry etching process of embedded flash memory
Selection method, comprising the following steps: the domain of the active area of the embedded flash memory and the domain of floating gate region are provided；According to described
The domain of active area and the domain of floating gate region determine that the domain of the active area and the practical etching area of the floating gate region is close
Degree, the practical etching area are the region that polysilicon is etched by dry etching process；According to the practical reproduction region
Layout density and the preset thickness of oxide layer after the etching under the polysilicon, select corresponding dry etching process.
Optionally, the layout density of the determination active area and the practical etching area of the floating gate region includes: root
According to the domain of the active area and the domain of floating gate region, the overlapping region of the floating gate region Yu the active area is determined；According to institute
The layout density of the layout density and the overlapping region of stating active area determines the layout density of the practical etching area.
Optionally, the practical erosion is determined according to the layout density of the layout density of the active area and the overlapping region
The layout density for carving region includes: the layout density that the overlapping region is subtracted using the layout density of the active area, with
To the layout density of the practical etching area.
Optionally, the layout density of the overlapping region is equal to the layout density of the floating gate region multiplied by preset first ratio
Value.
Optionally, the layout density of the determination active area and the practical etching area of the floating gate region includes: root
According to the domain of the active area and the domain of floating gate region, the overlapping region of the floating gate region Yu the active area is determined, it is described heavy
The layout density in region is closed as the first layout density；The layout density for determining the practical etching area of the floating gate region, as
Second layout density；According to the layout density of the active area, first layout density and the second layout density, determine described in
The layout density of active area and the practical etching area of the floating gate region.
Optionally, first layout density is subtracted along with second domain using the layout density of the active area
Density, to obtain the layout density of the practical etching area of the active area and the floating gate region.
Optionally, the etch depth of the polysilicon is calculated according to the volume of the polysilicon actually etched in the floating gate region
Value；The volume of the floating gate region under same depth is calculated according to the etch depth value；It calculates and is actually etched in the floating gate region
Polysilicon volume and the floating gate region volume ratio；Using the layout density of the floating gate region multiplied by the ratio,
With the layout density of the practical etching area of the determination floating gate region.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that
The embodiment of the present invention provides a kind of selection method of the polysilicon dry etching process of embedded flash memory, including following step
It is rapid: the domain of the domain and floating gate region of the active area of the embedded flash memory is provided；According to the domain and floating gate of the active area
The domain in area determines the layout density of the practical etching area of the active area and the floating gate region, the practical etching area
For the region for etching polysilicon by dry etching process；According to the layout density in the practical reproduction region and it is located at described more
The preset thickness of oxide layer after the etching under crystal silicon, selects corresponding dry etching process.Using the embodiment of the present invention, Ke Yigen
According to the layout density of the practical etching area of polysilicon, suitable polysilicon dry etching process is selected, thus to floating gate distal tip
The pattern at end is accurately controlled, to improve flash memory performance.
It further, in embodiments of the present invention, can for not needing the case where being etched in floating gate region to polysilicon
To subtract each other or calculate multiplied by a variety of calculations such as default ratio the layout density of practical etching area by layout density, it is
User provides convenient.
Further, in embodiments of the present invention, the case where needs being etched polysilicon in the floating gate region,
It can more precisely calculate according to the volume of the polysilicon actually etched in floating gate region and the volume of floating gate region and obtain floating gate region
The layout density of the polysilicon inside actually etched facilitates the layout density for calculating more accurate practical etching area, into
And more particularly suitable polysilicon dry etching process is selected, so that the pattern to floating gate sharp distal tip is accurately controlled.
Detailed description of the invention
Fig. 1 is the process of the selection method of the polysilicon dry etching process of one of embodiment of the present invention embedded flash memory
Figure；
Fig. 2 shows the arrangement modes of the domain of one of embodiment of the present invention active area and the domain of floating gate region；
Fig. 3 to Fig. 4 is the schematic diagram of the section structure of the polysilicon dry etching process process in first embodiment of the invention.
Fig. 5 to Fig. 6 is the schematic diagram of the section structure of the polysilicon dry etching process process in second embodiment of the invention.
Specific embodiment
As previously mentioned, the height and sharpness of floating gate sharp distal tip will affect floating gate in programming, wiping in embedded flash memory
The voltage coupled when writing, and then influence performance of flash memory when programming, erasable.Specifically, too low, excessively blunt floating gate tip
Tip will lead to too small tunnelling current, and then since electric field strength is too low, and programming, erasable electric current is too small and leads to programming, wipes
The case where writing overlong time.
It, can be by remaining the thickness of oxide layer on the active area after polysilicon dry etching process in concrete technology implementation
The precise degrees of degree know whether floating gate sharp distal tip is accurate.Specifically, remaining oxide layer is thinner, indicate that polysilicon is dry
Etching is heavier to the etching degree of the floating gate sharp distal tip, and it is too low, excessively blunt more to easily lead to floating gate sharp distal tip.But it chases after simply
Seek blocked up oxide layer, it is possible to cause polysilicon etch insufficient, component failure is caused when serious.So keeping oxide layer
The precision of thickness is of great significance.
It in the prior art, can be close according to the layout density of active area or the domain of floating gate region for determining product
Degree obtains corresponding oxidated layer thickness by selecting polysilicon dry etching process.But for new product, only pass through active area
Domain, or only pass through the domain of floating gate region, it is difficult to select correct dry etching process, lead to the oxidated layer thickness obtained not
Meet expection, the control of floating gate sharp distal tip is inaccurate.
The present inventor has found that the key of the above problem is that the prior art relies only on active area or floating after study
Single layer domain in grid region, it is difficult to accurately calculate the correlation of the layout density and etch-rate actually etched.This is because
In logic region, the territory pattern and uneven arrangement, the i.e. chip area of active area or floating gate region of active area and floating gate region
It is non-linear relation namely active area or the big production of the chip area of floating gate region with the area of polysilicon for needing to be etched
Product, the area for needing to carry out the polysilicon of dry ecthing but may not be big.
It, can be in conjunction with two by analyzing simultaneously active area and two layers of floating gate region domain using the embodiment of the present invention
The layout density of the practical etching area of polysilicon is calculated in layer domain, so that correct polysilicon dry etching process is selected,
Accurately to be controlled floating gate sharp distal tip.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent, with reference to the accompanying drawing to this
The specific embodiment of invention is described in detail.
Referring to Fig.1, Fig. 1 is the selecting party of the polysilicon dry etching process of one of embodiment of the present invention embedded flash memory
The flow chart of method.The selection method of the polysilicon dry etching process of the embedded flash memory includes step S101 to step S103.
Step S101: the domain of the active area of the embedded flash memory and the domain of floating gate region are provided.
Step S102: according to the domain of the domain of the active area and floating gate region, the active area and the floating gate are determined
The layout density of the practical etching area in area, the practical etching area are the region that polysilicon is etched by dry etching process.
Step S103: existed according to the layout density in the practical reproduction region and the oxide layer under the polysilicon
Preset thickness after etching selects corresponding dry etching process.
In the specific implementation of step S101, the domain of the active area of embedded flash memory and the domain of floating gate region can led
The product stage for entering the embedded flash memory obtains in the product layout information of importing.
Fig. 2 shows the arrangement modes of the domain of one of embodiment of the present invention active area and the domain of floating gate region.Such as
Shown in Fig. 2, the domain of active area 110 and the domain of floating gate region 120 are in cross arrangement, and formation floating gate region is overlapped area with active area
Domain 121.
Wherein, the dotted line for connecting A to B, which can serve to indicate that, carries out the polysilicon dry etching process process of embedded flash memory
When section detects, selectable profile position.Specific the schematic diagram of the section structure will be described hereinafter.
As previously mentioned, the layout area of embedded flash memory includes memory area and logic region, in memory area,
Active area 110 and the domain of floating gate region 120 arrange in an uniform way, for example, Fig. 2 shows cross arrangement mode, active area at this time
110 or floating gate region 120 chip area and overlapping region 121 area have linear relationship.It is active but in logic region
The territory pattern arrangement mode of area 110 or floating gate region 120 shows diversity, complexity, i.e. active area 110 or floating gate region 120
Chip area and overlapping region 121 area do not have linear relationship.
With continued reference to Fig. 1, in the specific implementation of step S102, according to the version of the domain of the active area and floating gate region
Figure determines that the layout density of the practical etching area of the active area and the floating gate region, the practical etching area are to pass through
The region of dry etching process etching polysilicon.
In the first embodiment of the present invention, it does not need to be etched polysilicon in the layout area of floating gate region, only
It needs to be etched process to the polysilicon being located in remaining region above active area.
It is the cross-section structure signal of the polysilicon dry etching process process in first embodiment of the invention referring to Fig. 3, Fig. 3
Figure.Its profile position connects the dotted line of A to B as shown in Figure 2.
As shown in figure 3, being sequentially formed with oxide 101, floating gate (Floating Gate) on 100 surface of semiconductor substrate
111 and floating gate side wall (Floating Gate Spacer) 112.In the oxide not covered by floating gate 111 and floating gate side wall 112
On 101 regions, it is formed with polysilicon 130 to be etched.
Wherein, the region between the edge of adjacent floating gate side wall 112 is floating gate region 120 (referring to Fig. 2), floating gate region 120
The polysilicon 131 between floating gate side wall 112 and floating gate side wall 112 is included at least, wherein the edge of floating gate side wall 112 is
The edge adjacent with polysilicon 130 to be etched of floating gate side wall 112.Floating gate side wall 112 will be as polysilicon dry etching process
Hard mask layer (Hard Mask), controls the etching step and occurs over just the region that do not protected by floating gate side wall 112.
It should be pointed out that between adjacent floating gate side wall 112, i.e., also shape in the region of floating gate region 120 (referring to Fig. 2)
At there is polysilicon 131.In the manufacturing process of the embedded flash memory product of the embodiment of the present invention, matcoveredn 121 is covered to protect
It is protected not to be etched.Therefore, in the first embodiment, the practical etching area of polysilicon dry etching process processing only includes to more
Crystal silicon 130 is etched.
Fig. 4 shows that after the polysilicon dry etching process, the cross-section structure of the embedded flash memory of acquisition shows
It is intended to.
As shown in figure 4, exposing floating gate sharp distal tip 113 and position after being etched to polysilicon 130 (referring to Fig. 3)
Oxide layer 101 under polysilicon.
Wherein, accurately the pattern of control floating gate sharp distal tip 113 is of great significance for controlling the performance of flash memory.Specifically
For, if etching excessively, leads to the excessively passivation of the floating gate sharp distal tip 113, it will affect embedded flash memory in programming, erasable
When performance., whereas if undercut, remaining polysilicon 130, which may cause, bridges short-circuit (bridge) phenomenon, reduces and produces
The yield of product.
According to the prior art it is found that the layout density of the practical etching area obtained is more accurate, more adduction can be more selected
Suitable polysilicon dry etching process.
It continues to refer to figure 1, in a kind of specific implementation of the first embodiment, according to the domain of the active area and floats
The domain in grid region can determine overlapping region, and then according to the domain of the layout density of the active area and the overlapping region
Density can determine the layout density of the practical etching area.
In specific implementation, it can be handled by the domain of domain and floating gate region to the active area, with determination
Overlapping region.Such as pass through conventional Overlapping radar image, repeated data processing technique etc..The embodiment of the present invention does not limit this
System.
It is possible to further subtract the layout density of the overlapping region using the layout density of the active area, with
To the layout density of the practical etching area.
Specifically, be the region of the active area blocked by floating gate region according to overlapping region, it can be by the domain of active area
Density subtracts the layout density of overlapping region, to obtain the layout density of practical etching area, to obtain not hidden by floating gate region
The layout density of polysilicon above the active area of gear.
In another specific implementation of the first embodiment, the layout density of the overlapping region is equal to the floating gate
The layout density in area is multiplied by preset first ratio.
Specifically, the first ratio is that layout density ratio namely active area that active area occupies account in the region of floating gate region
According to area ratio.
Preset first ratio can be configured according to the empirical value of the manufacturing process of similar-type products, can also led
The product stage for entering the embedded flash memory is obtained by the product layout information of importing.The present invention is to the first ratio of acquisition
Mode is with no restrictions.As a unrestricted example, it is 50% that preset first ratio, which can be set, at this time in floating gate region
Region in, the area equation of active area and non-active area (such as shallow trench isolation region).
In the first embodiment of the present invention, for not needing to be etched polysilicon in the layout area of floating gate region
The case where, it can choose the layout density that a variety of calculations calculate practical etching area, provided conveniently for user.
In the second embodiment of the present invention, in addition to being located at the polysilicon above active area, it is also necessary in the floating gate region
Layout area in process is etched to polysilicon.
It is the cross-section structure signal of the polysilicon dry etching process process in second embodiment of the invention referring to Fig. 5, Fig. 5
Figure.Its profile position connects the dotted line of A to B as shown in Figure 2.
As shown in figure 5, being sequentially formed with oxide 201, floating gate 211 and floating gate side wall on 200 surface of semiconductor substrate
212.On 201 region of oxide not covered by floating gate 211 and floating gate side wall 212, it is formed with polysilicon 230 to be etched,
And between adjacent floating gate side wall 212, it is formed with polysilicon 231 to be etched.Wherein, the side of adjacent floating gate side wall 212
Region between edge is floating gate region 120 (referring to Fig. 2), and floating gate region 120 has included at least floating gate side wall 212 and floating gate side wall
Polysilicon 231 between 212, wherein the edge of floating gate side wall 212 is that floating gate side wall 212 is adjacent with polysilicon 230 to be etched
Edge.
In a second embodiment, the practical etching area of polysilicon dry etching process processing includes to polysilicon 230 and more
Crystal silicon 231 is etched.
Fig. 6 shows that after the polysilicon dry etching process, the cross-section structure of the embedded flash memory of acquisition shows
It is intended to.
As shown in fig. 6, exposing floating gate sharp distal tip 213 and position after being etched to polysilicon 230 (referring to Fig. 5)
Oxide layer 201 under polysilicon.The polysilicon 231 of partial volume is etched simultaneously.
It continues to refer to figure 1, in the second embodiment of the invention, according to the version of the domain of the active area and floating gate region
Figure, determines the overlapping region of the floating gate region Yu the active area, the layout density of the overlapping region is close as the first domain
Degree.
According to Such analysis it is found that subtracting first layout density using the layout density of the active area, as exist
In the oxide areas not covered by floating gate and floating gate side wall, the layout density of polysilicon to be etched is determined.
Further, it is determined that the layout density of the practical etching area of the floating gate region, as the second layout density, as
Between adjacent floating gate side wall, the layout density of polysilicon to be etched is determined.
Further, first layout density is subtracted along with described second using the layout density of the active area
Layout density, to obtain the layout density of the practical etching area of the active area and the floating gate region.
It is not completely etched away in view of the polysilicon between adjacent floating gate side wall, it can be by calculating the floating gate
The ratio of the volume of the floating gate region obtains the second layout density under the volume and same depth of the polysilicon actually etched in area.
Specifically, the etch depth of the polysilicon is calculated according to the volume of the polysilicon actually etched in the floating gate region
Value calculates the volume of the floating gate region under same depth according to the etch depth value, calculates and actually etch in the floating gate region
Polysilicon volume and the floating gate region volume ratio, and then using the floating gate region layout density multiplied by the ratio
Value, with the layout density namely the second layout density of the practical etching area of the determination floating gate region.
Wherein, the volume of the polysilicon actually etched in the floating gate region can be according to the manufacturing process of similar-type products
Empirical value obtains, such as after polysilicon dry etching process, passes through SEM (Scanning Electronic
Microscope, scanning electron microscope) sectional view that obtains embedded flash memory product or semi-finished product, is obtained by survey calculation
?.
In embodiments of the present invention, feelings needs being etched polysilicon in the layout area of the floating gate region
Condition can calculate the layout density of the polysilicon actually etched within the scope of the domain for obtaining more accurate floating gate region, facilitate
The layout density of more accurate practical etching area is calculated, to select more particularly suitable polysilicon dry etching process.
In the specific implementation of step S103, according to the layout density in the practical reproduction region and it is located at the polycrystalline
The preset thickness of oxide layer after the etching under silicon, selects corresponding polysilicon dry etching process.
In the prior art, can be according to the experience of the manufacturing process of similar-type products, the domain for obtaining etching area is close
Pair between degree, the thickness after the etching of the oxide layer under the polysilicon and different polysilicon dry etching process threes
It should be related to, preparation in advance covers etch process parameters, thus in new product introduction, according to the layout density and oxygen of etching area
The preset thickness for changing layer can select more accurate etch process, quickly to facilitate new product volume production.As a non-limit
The example of property processed, the preset thickness that the oxide layer can be set is 0.1 nanometer to 40 nanometers.
But only by the domain of active area, or only by the domain of floating gate region, simultaneously to the judgement of practical etching area
Inaccuracy causes during further improvement, and etch process conditions can only be determined by round-about way, such as produces few
After measuring product or semi-finished product, the sectional view of product is obtained by SEM, and then polysilicon is modified according to the measurement data of sectional view and is done
Etch process parameters, and then produced again with new technological parameter, detect SEM result again later.
Above-mentioned process not only spends higher production cost, and because of finiteness existing for SEM number of samples, it is difficult to one
The adjustment of technology of product in place, is caused the promotion period of yield after new product introduction to be longer than expection by secondary property.
Using the embodiment of the present invention, the layout density of practical etching area can be obtained, then in conjunction with the default of oxide layer
Thickness can choose out more accurate etch process, so that the tip pattern of different product flash memory floating gate is accurately controlled, it is high
Realize the smooth importing of new product in effect ground.
In specific implementation, the etch-rate of the polysilicon dry etching process be 0.1 nm/minute to 1000 nanometers/
Minute, the etch-rate of the oxide layer is 0.1 nm/minute to 500 nm/minutes.The polysilicon dry etching process
It is etched 2 seconds to 100 seconds based on etching period, overetch (over etch) 0 to 500 second.The erosion of the polysilicon dry etching process
Carving temperature is -80 degrees Celsius to 300 degrees Celsius.The etching gas of the polysilicon dry etching process can be chlorine (Cl2), bromine
Change hydrogen (HBr) etc..The etching pressure of the polysilicon dry etching process is 1mTorr to 5000mTorr.The polysilicon dry corrosion
The etch voltage of carving technology is 1V to 2000V.The original thickness of the oxide layer is 2 nanometers to 50 nanometers.It should be pointed out that
The embodiment of the present invention to the technological parameter of the polysilicon dry etching process with no restriction.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (7)
1. a kind of selection method of the polysilicon dry etching process of embedded flash memory, which comprises the following steps:
The domain of the active area of the embedded flash memory and the domain of floating gate region are provided；
According to the domain of the domain of the active area and floating gate region, the practical etching region of the active area Yu the floating gate region is determined
The layout density in domain, the practical etching area are the region that polysilicon is etched by dry etching process；
According to the default thickness of the layout density of the practical etching area and the oxide layer under the polysilicon after the etching
Degree, selects corresponding dry etching process.
2. the selection method of the polysilicon dry etching process of embedded flash memory according to claim 1, which is characterized in that institute
It states and determines that the layout density of the active area and the practical etching area of the floating gate region includes:
According to the domain of the domain of the active area and floating gate region, the overlapping region of the floating gate region Yu the active area is determined；
The version of the practical etching area is determined according to the layout density of the layout density of the active area and the overlapping region
Figure density.
3. the selection method of the polysilicon dry etching process of embedded flash memory according to claim 2, which is characterized in that root
The layout density of the practical etching area is determined according to the layout density of the active area and the layout density of the overlapping region
It include: the layout density that the overlapping region is subtracted using the layout density of the active area, to obtain the practical etching region
The layout density in domain.
4. the selection method of the polysilicon dry etching process of embedded flash memory according to claim 2, which is characterized in that institute
The layout density for stating overlapping region is equal to the layout density of the floating gate region multiplied by preset first ratio.
5. the selection method of the polysilicon dry etching process of embedded flash memory according to claim 1, which is characterized in that institute
It states and determines that the layout density of the active area and the practical etching area of the floating gate region includes:
According to the domain of the domain of the active area and floating gate region, the overlapping region of the floating gate region Yu the active area is determined,
The layout density of the overlapping region is as the first layout density；
The layout density for determining the practical etching area of the floating gate region, as the second layout density；
According to the layout density of the active area, first layout density and the second layout density, determine the active area with
The layout density of the practical etching area of the floating gate region.
6. the selection method of the polysilicon dry etching process of embedded flash memory according to claim 5, which is characterized in that root
According to the layout density of the active area, first layout density and the second layout density, determine that the active area is floated with described
The layout density of the practical etching area in grid region includes: to subtract first layout density using the layout density of the active area
Along with second layout density, to obtain the layout density of the practical etching area of the active area and the floating gate region.
7. the selection method of the polysilicon dry etching process of embedded flash memory according to claim 5, which is characterized in that institute
It states and determines that the layout density of the practical etching area of the floating gate region includes:
The etch depth value of the polysilicon is calculated according to the volume of the polysilicon actually etched in the floating gate region；
The volume of the floating gate region under same depth is calculated according to the etch depth value；
Calculate the ratio of the volume of the polysilicon actually etched in the floating gate region and the volume of the floating gate region；
Using the layout density of the floating gate region multiplied by the ratio, with the domain of the practical etching area of the determination floating gate region
Density.
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