CN106230541A - A kind of Site synch system and method for EPA - Google Patents
A kind of Site synch system and method for EPA Download PDFInfo
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- CN106230541A CN106230541A CN201610642303.2A CN201610642303A CN106230541A CN 106230541 A CN106230541 A CN 106230541A CN 201610642303 A CN201610642303 A CN 201610642303A CN 106230541 A CN106230541 A CN 106230541A
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- main website
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/4026—Bus for use in automation systems
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- Computer Networks & Wireless Communication (AREA)
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- Synchronisation In Digital Transmission Systems (AREA)
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Abstract
The invention discloses a kind of Site synch system and method for EPA, can solve the problem that owing to the shake of operating system and protocol stack causes time inaccurate problem, by the EPA bag regularly given out a contract for a project and real time parsing receives, eliminate processor and process the process given out a contract for a project and unpack, improve the disposal ability of whole system, solve to cause, due to the shake of operating system and Software Protocol Stack, the problem that processing capability in real time is low, main website time service function can also be provided, the simultaneously operating between collaborative slave station.The present invention includes: clock counter is arranged in FPGA, and main website connects main control processor, and reference clock parameter is provided to main website by clock counter, and main website carries out clock synchronization for the reference clock parameter sent by clock counter；It is additionally operable to synchronize bag to corresponding slave station tranmitting data register；The slave station that main website is corresponding synchronizes bag for the clock sent according to main website and carries out clock synchronization.The present invention is applicable to website control.
Description
Technical field
The present invention relates to electronic information technical field, particularly relate to a kind of Site synch system for EPA and
Method.
Background technology
In the most conventional Ethernet auto-control technology (EtherCAT) scheme, ASIC is used to reach by slave station
Time strong, main website is then soft solution based on high-performance CPU so that system minimal circulation week in running
Phase is limited by CPU in master station, if the cpu performance that main website is used is not high enough, or operating system real-time is not enough, may result in it
Cycle period increases.
Affect a lot of because have of operating system real-time, such as in the application based on current EtherCAT agreement,
Master station protocol needs constantly to obtain timer clock from operating system, main website can be caused to open owing to operating system exists clock jitter
Time jitter, process cycle data and the shake of data time aperiodic that dynamic message sends.Main website is directly sent by NIC
EtherCAT message, will cause Frame to send the shake of time every time, thus affect the real-time performance of master device.And
Owing to controlling the multiformity of equipment in system, in actual applications, whole system needs to integrate based on the industry under different agreement
Ethernet device, now uses same main website based on cpu software processes to synchronize, inevitably there is the biggest trembling
Dynamic so that the net synchronization capability between different agreement is very poor, it is difficult to meet the real-time performance of master device.
Summary of the invention
Embodiments of the invention provide a kind of Site synch system and method for EPA, it is possible to solve due to
The shake of operating system and protocol stack causes time inaccurate problem.
For reaching above-mentioned purpose, embodiments of the invention use a kind of Site synch system for EPA, bag
Include: main control processor, the FPGA, NIOS, clock counter, main website and the main website pair that are connected by bus with described main control processor
The slave station answered, described NIOS at least accelerates for the speed ring of described website control system and the calculating of position ring, or described
Main control processor carries out the calculating of speed ring and position ring for device；
Described clock counter is arranged in described FPGA, and described main website passes through Avalon-MM (Avalon Memory
Map EBI, a set of system bus standard completed provided for Altera, and in the FPGA product) interface connects institute
Stating main control processor, reference clock parameter is provided to described main website by described clock counter, and described main website is for by described
The reference clock parameter that clock counter sends carries out clock synchronization；
Described main website is connected with corresponding slave station by network interface, and described main website sends for the slave station corresponding to described main website
Too net frame, and for resolving the ethernet frame that slave station corresponding to described main website returns, described main website is additionally operable to corresponding slave station
Tranmitting data register synchronizes bag；
The slave station that described main website is corresponding synchronizes bag for the clock sent according to described main website and carries out clock synchronization.
Wherein, described main control processor includes ARM, and described main control processor is used for the initial configuration of each main website, and
For sending mailbox data, it is additionally operable to each slave station is carried out initialization operation, and calculates the required director data of slave station,
The data controlling depositor of each slave station are by described main control processor read and write access.
And each main website is connected by the slave station that network interface is corresponding with at least one, each network interface correspondence connects different watching
Take equipment and/or I/O device, concrete, the network interface of part main website can be had to be not connected to slave station, main website can be configured to close mold closing
Formula；The small data packets that each network interface is answered for transmission.
And described website control system uses at least one industrial ethernet protocol, different industrial ethernet protocols is corresponding
It is carried to different network interfaces；The reference clock of each industrial ethernet protocol is the described clock count being arranged in described FPGA
Device.
In the website control system of existing agreement based on EtherCAT, due to trembling of operating system and protocol stack
Dynamic, there is the biggest error in traditional main website timestamp on Frame, causes timestamp inaccurate.And first slave station makes
With ASIC, it is substantially not present dozen timestamp and there will be the problem of shake, so beating timestamp from first slave station toward Frame
Relatively accurate；And all of data that traditional main website sends all can be forwarded to follow-up slave station through first slave station the most again,
Thus the temporal information of first slave station is sent to follow-up all of slave station, therefore generally use first slave station as reference
Clock synchronizes follow-up all of EtherCAT slave station clock.The Site synch system and method that the embodiment of the present invention provides, makes
The intervalometer sent as the time source of time service and periodic data bag with the clock counter in FPGA, it is ensured that give out a contract for a project
Timestamp in time and packet is accurate, solves in prior art owing to the shake of operating system and protocol stack causes
The inaccurate problem of timestamp.And shorten the cycle period of periodic data, the work that timing is given out a contract for a project and real time parsing receives
Industrial Ethernet bag, the process that processor is given out a contract for a project without care and unpacked, the disposal ability of whole main station system is greatly improved, solves
Owing to the shake of operating system and Software Protocol Stack causes the problem that processing capability in real time is low, additionally it is possible to provide main website time service merit
Can, the simultaneously operating between collaborative slave station.
Accompanying drawing explanation
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, below by use required in embodiment
Accompanying drawing is briefly described, it should be apparent that, the accompanying drawing in describing below is only some embodiments of the present invention, for ability
From the point of view of the those of ordinary skill of territory, on the premise of not paying creative work, it is also possible to obtain the attached of other according to these accompanying drawings
Figure.
The system architecture schematic diagram that Fig. 1-3 provides for the embodiment of the present invention；
The schematic diagram of the instantiation of distribution task time of the periodic data that Fig. 4 provides for the embodiment of the present invention；
The main website that Fig. 5 a provides for the embodiment of the present invention sends the schematic flow sheet controlled；
The main website that Fig. 5 b provides for the embodiment of the present invention receives the schematic flow sheet controlled；
The schematic diagram of the instantiation of a kind of transmission timing that Fig. 6 provides for the embodiment of the present invention；
A kind of periodic data that Fig. 7 provides for the embodiment of the present invention and the instantiation of aperiodicity data transmission collision
Schematic diagram；
Fig. 8 carries out for a kind of aperiodicity message that the embodiment of the present invention provides splitting the schematic diagram sent；
The schematic flow sheet that a kind of periodic data that Fig. 9 provides for the embodiment of the present invention sends；
The schematic flow sheet that a kind of aperiodicity data that Figure 10 provides for the embodiment of the present invention send.
Detailed description of the invention
For making those skilled in the art be more fully understood that technical scheme, below in conjunction with the accompanying drawings and specific embodiment party
The present invention is described in further detail by formula.Embodiments of the present invention, the showing of described embodiment are described in more detail below
Example is shown in the drawings, and the most same or similar label represents same or similar element or has identical or class
Element like function.The embodiment described below with reference to accompanying drawing is exemplary, is only used for explaining the present invention, and can not
It is construed to limitation of the present invention.Those skilled in the art of the present technique are appreciated that unless expressly stated, odd number shape used herein
Formula " one ", " one ", " described " and " being somebody's turn to do " may also comprise plural form.It is to be further understood that the description of the present invention
The wording of middle use " includes " referring to there is described feature, integer, step, operation, element and/or assembly, but it is not excluded that
Exist or add other features one or more, integer, step, operation, element, assembly and/or their group.It should be understood that
When we claim element to be " connected " or during " coupled " to another element, and it can be directly connected or coupled to other elements, or
Intermediary element can also be there is.Additionally, " connection " used herein or " coupling " can include wireless connections or couple.Here make
Wording "and/or" include one or more any cell listing item being associated and all combinations.The art
Those of skill will appreciate that, unless otherwise defined, all terms used herein (including technical term and scientific terminology) have
With the those of ordinary skill in art of the present invention be commonly understood by identical meaning.Should also be understood that the most general
Those terms defined in dictionary should be understood that have the meaning consistent with the meaning in the context of prior art, and
Unless defined as here, will not explain by idealization or the most formal implication.
The embodiment of the present invention provides a kind of Site synch system for EPA, as it is shown in figure 1, include: master control
Processor, the FPGA being connected by bus with described main control processor (Field-Programmable Gate Array, scene
Programmable gate array), NIOS (a kind of uses Harvard structure, has on the second filial generation sheet of 32 bit instruction collection at programmable soft core
Reason device), clock counter, slave station that main website is corresponding with main website, described NIOS is at least for the speed of described website control system
The calculating of ring and position ring is accelerated, or described main control processor carries out the calculating of speed ring and position ring for device, it is possible to
The treatment effeciency of system is improved by the acceleration function of NIOS.
In the present embodiment, the FPGA being provided with multiple main website is alternatively referred to as FPGA main website, and slave station is referred to as
EtherCAT (Ethernet auto-control technology) slave station.Concrete, the clock counter of main website is as reference clock and is used for
Synchronize the equipment on all-network, such as EtherCAT/PowerLink etc.；Main website is mainly used in giving out a contract for a project of packet and unpacks；Main website
The data controlling depositor by ARM (Advanced RISC Machine, advanced compacting instruction set processor) write；Adopt
Carry out multiaxis speed ring/position ring with the NIOS of FPGA to calculate and accelerate, it is also possible to direct ARM carries out speed ring and position ring
Calculate.To improve real-time and to alleviate the burden of ARM side；FPGA timing produces to be interrupted to NIOS and ARM, obtains afterwards and sends out next time
The data of bag；Main website configurable period property sends distribution clock and synchronizes bag, and especially the present embodiment is applied at servo period longer
Scene in；
Described clock counter is arranged in described FPGA, and as shown in Figure 2, described main website passes through Avalon-MM interface
Connecting described main control processor, reference clock parameter is provided to described main website by described clock counter, and described main website is used for leading to
The reference clock parameter crossing the transmission of described clock counter carries out clock synchronization.
During it should be noted that only use single network interface for FPGA main website, in the concrete application of the present embodiment, can
Using by main station time as the reference time, it is possible to use main website corresponding first supports the slave station of DC function in a dc mode
Time as the reference time, recommend main station time here as the reference time；And Multi-netmouth is existed for FPGA main website
Situation, then the time of main website must be used as the reference time.
In the present embodiment, described main website is connected with corresponding slave station by network interface, and described main website is for described main website
Corresponding slave station sends too net frame, and for resolving the ethernet frame that slave station corresponding to described main website returns, described main website also uses
In synchronizing bag to corresponding slave station tranmitting data register.The slave station that described main website is corresponding synchronizes for the clock sent according to described main website
Bag carries out clock synchronization.
In the present embodiment, described main control processor can use ARM, and described main control processor is at the beginning of each main website
Beginningization configures, and is used for sending mailbox data, is additionally operable to carry out each slave station initialization operation, and calculates the required of slave station
Director data, each slave station control depositor data by described main control processor read and write access.Wherein, FPGA main website joins
Being set to periodically send the pattern of fixing packet, ARM then configures corresponding periodically descriptor.
Concrete, frame head depositor can be used as the depositor in the present embodiment.Such as: according to Ethernet protocol,
Ethernet frame includes destination address, source address, frame type, data and FCS (Frame Check Sequence, frame check sequence
Row).The present embodiment uses frame head depositor as shown in table 1, mainly comprises destination address, source address, frame type (such as:
EtherCAT is 0x88A4), the information device of Ethercat head.Destination address, source address, frame type have only to initialization definitions one
Secondary.
Table 1
Wherein it is possible to store the operation content of every sub-message by descriptor buffer and address that data are deposited
(the Descriptor buffer of similar DMA (Directional Memory Access, direct memory access)), descriptor is posted
Storage is as shown in table 2.In the present embodiment, the periodically structure of depositor and acyclic descriptor is substantially the same, and distinguishes
In the most corresponding Frame of periodicity descriptor, but the corresponding multiple Frames of aperiodic descriptor.
Table 2
As shown in table 2, each descriptor is from the corresponding sub-message of the description content of 0xN0-0xN0+10, multiple descriptors
Leave a RAM (Random-Access Memory, random access memory) the inside in and constitute a descriptor buffer, often
Secondary ARM/NIOS writes every descriptor corresponding to sub-message inside descriptor Buffer, and FPGA resolves these descriptions simultaneously
Symbol, and send out needing the data write in slave to read and be organized into EtherCAT Frame from WriteMemory Address
Toward slave station.The Frame real time parsing that parsing module then will return, i.e. starts data parsing Frame receives when
Journey, and the data parsed are written to the address that Read Memory Address specifies, thus realized by FPGA main website
Unpacking in real time, the scheme just resolved after all harvesting relative to traditional Frame, the real-time of the present embodiment and motility are more
By force.
Wherein, for periodically sending data, FPGA main website is according to whether having subsequent packet mark (M) in descriptor
Determine insert FCS or continue to add subsequent packet.And for acyclic transmission data, FPGA main website is according to descriptor
The order of the inside sends out Frame.
In the present embodiment, described NIOS at least adds for the described speed ring of website control system and the calculating of position ring
Speed, or described main control processor carries out the calculating of speed ring and position ring for device.Concrete, FPGA main website is at running
NIOS and ARM is given in the different interruption of middle generation respectively, for periodic data, after FPGA main website completes the reception of data, passes through
The data that the process of interrupt notification NIOS receives, after interrupting being sent to NIOS, NIOS carries out the calculating of speed ring and position ring；Right
In aperiodicity data, the data that FPGA main website is received by the process of interrupt notification ARM after completing the reception of data.Meanwhile,
FPGA main website the most also sends interrupt notification to ARM process.Interrupt register in the present embodiment, in ARM
Concrete as shown in table 3
Table 3
In the present embodiment, too much for the interstitial content of slave station in whole system, cause that packet is long, cycle period
Become big problem, use multiple network interface to connect different servos or I/O device, thus packet big for data volume is resolved into not
Send with the small data packets on network interface, reduce the data volume of each network interface load, thus shorten cycle period thus improve system
Performance.The most as shown in Figure 3, each main website is connected by the slave station that network interface is corresponding with at least one, each network interface pair
Different servosystems and/or I/O device should be connected；Concrete, the network interface of part main website can be had to be not connected to slave station, main website can
To be configured to " shut " mode".Wherein, the small data packets that each network interface is answered for transmission, the small data packets of each network interface corresponding is by counting
Obtain more than the packet decomposition of threshold value according to amount.
Further, as it is shown on figure 3, the multiple main websites connected by FPGA, each master device can arrange one
Individual network interface, thus FPGA main website possesses the framework of concurrent multiple network interface, thus support the hot plug merit of Multi-netmouth redundancy and slave station
Energy.And multiple master device therein based on same clock counter as reference clock, row clock of going forward side by side synchronizes.And at this
In embodiment, different communication protocol can be respectively configured on multiple network interfaces, owing to the clock of the master device of each network interface is
Synchronize, it is achieved that the communication standard of multiple agreement is simultaneously, synchronously run.
In the present embodiment, described website control system uses at least one industrial ethernet protocol, different industry with
Too fidonetFido correspondence is carried to different network interfaces.Wherein, the reference clock of each industrial ethernet protocol is described for being arranged on
Described clock counter in FPGA.In the present embodiment, for the synchronization between different agreement, specifically by different industrial ether
FidonetFido corresponds on different network interfaces, and the reference clock of all of agreement all uses the clock counter of FPGA main website, makes
The slave station of all of agreement is all synchronized with the clock of main website, the clock between different agreement all pass through one accurately main website time
Clock realizes indirect synchronization, it is achieved thereby that mixing between different agreement is dynamic.
In the website control system of agreement based on EtherCAT, due to operating system and the shake of protocol stack, tradition
Main website on Frame, beat timestamp there is the biggest error, cause timestamp inaccurate.And first slave station uses ASIC,
It is substantially not present and beats timestamp and there will be the problem of shake, so aligning toward beating timestamp Frame from first slave station
Really；And all of data that traditional main website sends all can be forwarded to follow-up slave station through first slave station the most again, thus will
The temporal information of first slave station is sent to follow-up all of slave station, therefore generally uses first slave station and comes as reference clock
Synchronize follow-up all of EtherCAT slave station clock.
And in the present embodiment, using FPGA as the main website under EtherCAT agreement, given out a contract for a project by main website and unpacking etc. patrols
Collect and harden in FPGA, i.e. timing transmission packet work etc. process in FPGA, thus message are greatly decreased and send out
Go out the shake of time.The clock of the most all of EtherCAT slave station equipment is all synchronized with master clock, so it is also possible that
Almost Complete Synchronization between main website and slave station, the lock-out pulse shake between main website and slave station can be much smaller than 1us.And for FPGA
Main website, ARM is responsible for the flow processs such as initialization and the configuration of FPGA main website, is responsible for sending mailbox data and the initialization to all slave stations
Operation.Wherein NIOS is responsible for the calculating acceleration of speed ring and position ring, thus improves real-time.The following of main website is greatly improved simultaneously
The performances such as ring cycle.Thus avoid the shake of traditional operating system and protocol stack, and the time of giving out a contract for a project is controlled and complete
Entirely can measure, thus improve the accuracy of timestamp, it is to avoid due to operating system and the shake of protocol stack in prior art
Cause time inaccurate problem.
The present embodiment also provides for a kind of Site synch method for EPA, and specifically for system, this system has
Body is referred in this enforcement, website control system as Figure 1-3, including: at main control processor and described master control
FPGA that reason device is connected by bus, NIOS, clock counter, slave station that main website is corresponding with main website, described NIOS is for described
The speed ring of website control method and the calculating of position ring are accelerated.Described clock counter is arranged in described FPGA, described master
Stand and connect described main control processor by Avalon-MM interface.Described main website is connected with corresponding slave station by network interface.
Described method includes:
Obtain reference clock parameter from described clock counter, and described reference clock parameter issued to described main website,
And control the reference clock parameter that described main website sent by described clock counter and carry out clock synchronization.
Control described main website again and synchronize bag to corresponding slave station tranmitting data register, and it is corresponding to described main website to control described main website
Slave station send too net frame, and/or control described main website and resolve the ethernet frame that slave station corresponding to described main website returns.
Control the clock that slave station corresponding to described main website send according to described main website afterwards to synchronize bag and carry out clock synchronization.
In the present embodiment, also include: control described main control processor and each main website is carried out initial configuration, and send
Mailbox data.With, each slave station is carried out initialization operation, and calculates the required director data of slave station, wherein, described master
Control processor includes ARM, and the data controlling depositor of each slave station are by described main control processor read and write access.
In the present embodiment, also include: data volume is decomposed into more than the packet of threshold value the decimal of each network interface corresponding
According to bag.And transmit, by each network interface, the small data packets answered, wherein, each main website by network interface corresponding with at least one from
Standing and be connected, each network interface correspondence connects different servosystems and/or I/O device.
In the present embodiment, the described small data packets that data volume is decomposed into more than the packet of threshold value each network interface corresponding
Including:
According to the length of aperiodicity data, whether detection aperiodicity data existed with the transmission time of periodic data
Conflict.If there is conflict, then first in the aperiodicity data detected and periodic data, screening and sending and there is not conflict
Packet；And the sub-message of aperiodicity data being split according to the message length of maximum transmission, and latent period
Packet retransmits after distributing.Such as: distribution task time of periodic data can as shown in Figure 4, wherein, arrow upwards
Representing Interruption, Tcycle represents cycle period.Owing to FPGA main website transmits data to network according to EtherCAT agreement
On, need the packet sent to be divided into periodic data and aperiodicity data, wherein, the priority of periodic data is higher than
Aperiodicity data, need to complete to send in the time window specified, and periodic data content can not be disassembled, and aperiodic
Property data there is no strict timing requirements, only need to complete transmission receives.
The periodicity of the FPGA main website in the present embodiment and acyclic transmission control, and can use as shown in Figure 5 a
Controlling logic, wherein, data-moving logic class is similar to dma controller, it is only necessary to the data of position will be specified according to EtherCAT
Protocol packing is put in Frame, and FCS calculates the calculating that logic is responsible for the CRC32 of Frame, and is joined by the CRC32 of calculating
Frame end.Sof generation module then generates the pulse signal in the moment of Sof, and external logic can use this moment of sof signal latch
Timestamp, for ARMW or FRMW order, for the calibration of synchronised clock.In a dc mode, FPGA main website needs to ensure
Frame arrived slave station before SYNC, can use transmission timing as shown in Figure 6, and wherein, dotted arrow represents that main website is sent out
Sending data-frame times, the dotted arrow of band point represents the SYNC time of slave station (or referred to as lock in time).
Further, FPGA main website according to PHY (physical layer) time ordered pair PHY side data be received, and by the number of PHY side
Carry out unpacking process according to according to EtherCAT agreement.As shown in Figure 5 b, wherein, FPGA main website need to check Frame to the block diagram received
The most correct with FCS, and according to the content in descriptor, the data returned are write corresponding position.FPGA main website need to be by inspection
Look into WKC (Working Count, job count) judge slave station either with or without completing the action specified, if the WKC received and expection
WKC inconsistent, then need notify ARM side carry out respective handling.FPGA main website can judge according to the Index receiving data
Periodic data frame or aperiodicity Frame, the Index frame less than 0x80 is periodic data frame, and Index is more than 0x80
Frame be aperiodicity Frame.
When the request of aperiodicity Frame sends, FPGA main website is according to the transmission required for aperiodicity Frame
Time judge its whether transmission with periodic data frame have conflict.If the time that the request of aperiodicity Frame sends and week
The interval of the timed sending time of phase property Frame cannot send first sub-message of aperiodicity Frame, then by aperiodic
Property Frame transmission request be deferred to after periodic data is sent completely.If the time that the request of aperiodicity Frame sends
The time interval sent with the timing of periodic data frame can complete the sub-message of one or more aperiodicity Frame still
Cannot complete to send whole sub-messages, then send after needing to split aperiodicity Frame.Segmentation is according to being maximum
Can send sub-message time less than aperiodicity Frame request send time and periodic data frame timing send time
Between be spaced.When not enabling the transmission of periodic data frame, such as at initial phase, it is not required to split aperiodicity
Frame, only just needs to split aperiodicity Frame during periodic data sends.If still there being conflict after Fen Ge,
Then FPGA main website needs to report an error.Such as: the sequential of periodic data and aperiodicity data transmission collision is as it is shown in fig. 7, non-week
Phase property message carries out splitting the sequential sent as shown in Figure 8, and in figures 7 and 8, solid box represents periodic data frame, dotted line
Frame represents aperiodicity Frame, and shown in figure, the duration needed for eldest son's message of aperiodicity message sends is less than week
When phase property data are sent to the interval time in cycle next time, i.e. can avoid conflict, the present embodiment specifically can be taked reduce
The scheme of the length of single sub-message, the length reducing periodic data frame or increasing cycle period is to avoid conflict.Or,
The length of message or cycle can not also be modified by the present embodiment, but directly obtain the conflict time, and when conflict
Moment beyond between sends message, thus avoids the conflict time.
After avoiding conflict by fractionation aperiodicity data, periodic data and aperiodicity data transmission flow are the most such as
Shown in Fig. 9 and Figure 10.Further, descriptor will be deleted after Frame correctly returns aperiodic, and periodically descriptor will not
Being automatically deleted, only ARM side is modified.
Further, in the present embodiment, main website can detect abnormal in real time and process abnormal, including: if
Data transmission collision, then the reason sending conflict is searched by main website, and contrasting data transmitting portion chapters and sections solve；If Frame is lost
Lose, then the ARM process of main website notice, generally need to retransmit.If Frame exception or mistake, then main website notice ARM
Process, generally need to retransmit；If WKC mistake, then the ARM process of main website notice.
In the website control system of existing agreement based on EtherCAT, due to trembling of operating system and protocol stack
Dynamic, traditional main website beats timestamp on Frame and there is the biggest error, causes timestamp inaccurate.And first slave station makes
With ASIC, it is substantially not present dozen timestamp and there will be the problem of shake, so beating timestamp from first slave station toward Frame
Relatively accurate；And all of data that traditional main website sends all can be forwarded to follow-up slave station through first slave station the most again,
Thus the temporal information of first slave station is sent to follow-up all of slave station, therefore generally use first slave station as reference
Clock synchronizes follow-up all of EtherCAT slave station clock.The Site synch system and method that the embodiment of the present invention provides, makes
The intervalometer sent as the time source of time service and periodic data bag with the clock counter in FPGA, it is ensured that give out a contract for a project
Timestamp in time and packet is accurate, solves in prior art owing to the shake of operating system and protocol stack causes
The inaccurate problem of timestamp.And shorten the cycle period of periodic data, the work that timing is given out a contract for a project and real time parsing receives
Industrial Ethernet bag, the process that processor is given out a contract for a project without care and unpacked, the disposal ability of whole main station system is greatly improved, solves
Owing to the shake of operating system and Software Protocol Stack causes the problem that processing capability in real time is low, additionally it is possible to provide main website time service merit
Can, the simultaneously operating between collaborative slave station.
Each embodiment in this specification all uses the mode gone forward one by one to describe, identical similar portion between each embodiment
Dividing and see mutually, what each embodiment stressed is the difference with other embodiments.Real especially for equipment
For executing example, owing to it is substantially similar to embodiment of the method, so describing fairly simple, relevant part sees embodiment of the method
Part illustrate.The above, the only detailed description of the invention of the present invention, but protection scope of the present invention is not limited to
This, any those familiar with the art in the technical scope that the invention discloses, the change that can readily occur in or replace
Change, all should contain within protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of claim
Enclose and be as the criterion.
Claims (8)
1. the Site synch system for EPA, it is characterised in that including: main control processor and described master control
FPGA that processor is connected by bus, NIOS, clock counter, slave station that main website is corresponding with main website, described NIOS at least uses
Accelerate in the speed ring of described website control system and the calculating of position ring, or described main control processor carries out speed for device
Ring and the calculating of position ring；
Described clock counter is arranged in described FPGA, and described main website connects described master control by Avalon-MM interface and processes
Device, reference clock parameter is provided to described main website by described clock counter, and described main website is for by described clock counter
The reference clock parameter sent carries out clock synchronization；
Described main website is connected with corresponding slave station by network interface, and described main website is for sending too net to the slave station that described main website is corresponding
Frame, and for resolving the ethernet frame that slave station corresponding to described main website returns, described main website is additionally operable to send to corresponding slave station
Clock synchronizes bag；
The slave station that described main website is corresponding synchronizes bag for the clock sent according to described main website and carries out clock synchronization.
System the most according to claim 1, it is characterised in that described main control processor includes ARM, described main control processor
For the initial configuration of each main website, and it is used for sending mailbox data, is additionally operable to each slave station is carried out initialization operation,
And calculating the required director data of slave station, the data controlling depositor of each slave station are visited by the read-write of described main control processor
Ask.
System the most according to claim 1, it is characterised in that each main website by network interface corresponding with at least one from
Standing and be connected, each network interface correspondence connects different servosystems and/or I/O device；
The small data packets that each network interface is answered for transmission.
System the most according to claim 1, it is characterised in that described website control system uses at least one industry ether
FidonetFido, different industrial ethernet protocol correspondences is carried to different network interfaces；
The reference clock of each industrial ethernet protocol is the described clock counter being arranged in described FPGA.
5. a kind of Site synch method for EPA, it is characterised in that described method controls system for website
System, described website control system includes: main control processor, the FPGA being connected by bus with described main control processor, NIOS, time
The slave station that clock enumerator, main website are corresponding with main website, described NIOS is for the speed ring of described website control method and position ring
Calculate；Described clock counter is arranged in described FPGA, and described main website connects described master control by Avalon-MM interface and processes
Device；Described main website is connected with corresponding slave station by network interface；
Described method includes:
Obtain reference clock parameter from described clock counter, and described reference clock parameter is issued to described main website, and control
Make the reference clock parameter that described main website sent by described clock counter and carry out clock synchronization；
Control described main website and synchronize bag to corresponding slave station tranmitting data register, and control described main website to slave station corresponding to described main website
Send too net frame, and/or control the ethernet frame that slave station corresponding to the described main website of parsing of described main website returns；
Control the clock that slave station corresponding to described main website send according to described main website to synchronize bag and carry out clock synchronization.
Method the most according to claim 5, it is characterised in that also include:
Control described main control processor and each main website is carried out initial configuration, and send mailbox data；
With, each slave station is carried out initialization operation, and calculates the required director data of slave station, wherein, at described master control
Reason device includes ARM, and the data controlling depositor of each slave station are by described main control processor read and write access.
Method the most according to claim 5, it is characterised in that also include:
Data volume is decomposed into more than the packet of threshold value the small data packets of each network interface corresponding；
Transmitted the small data packets answered by each network interface, wherein, each main website passes through the slave station that network interface is corresponding with at least one
Being connected, each network interface correspondence connects different servosystems and/or I/O device.
Method the most according to claim 7, it is characterised in that it is right that the described packet that data volume is more than threshold value is decomposed into
The small data packets answering each network interface includes:
According to the length of aperiodicity data, whether detection aperiodicity data exist punching with the transmission time of periodic data
Prominent；
If there is conflict, then first in the aperiodicity data detected and periodic data, screening and sending and there is not conflict
Packet；And the sub-message of aperiodicity data being split according to the message length of maximum transmission, and latent period
Packet retransmits after distributing.
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