CN106229953A - A kind of ESD protection circuit - Google Patents
A kind of ESD protection circuit Download PDFInfo
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- CN106229953A CN106229953A CN201610794520.3A CN201610794520A CN106229953A CN 106229953 A CN106229953 A CN 106229953A CN 201610794520 A CN201610794520 A CN 201610794520A CN 106229953 A CN106229953 A CN 106229953A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
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Abstract
This application discloses a kind of ESD protection circuit, the power channel of sensitive circuit unit arranges switching device；And/or, driving element is set to the original switching device in the power channel controlling sensitive circuit unit；And/or, in the power channel that sensitive circuit unit is connected with non-sensitive circuit unit, the switching device being in parallel with sensitive circuit unit is set.The application can realize protection when esd event occurs to sensitive circuit unit, it is to avoid sensitive circuit unit damages owing to crossing stream, thus improves the reliability of whole IC chip, and the anti-ESD ability of circuit is greatly improved.The ESD protection circuit of the application only need to increase a small amount of device on the basis of available circuit structure, it is achieved mode is easy and cost is relatively low.
Description
Technical field
The application relates to a kind of ESD protection circuit, is particularly well-suited to the ESD protection of integrated circuit fields.
Background technology
The harm that the reliability of integrated circuit is brought by static discharge (ESD, electrostatic discharge) is day by day
Increasing, ESD protection circuit design has become as a pith in IC design.The basic ideas of ESD protection are
There is provided extra discharge path to discharge electrostatic charge, thus protect operating circuit.
Referring to Fig. 1, this is existing a kind of RC clamp circuit for ESD protection (RC clamp circuit).Institute
State RC clamp circuit and include a RC series arm, a phase inverter branch road and a clamping transistor Tclamp.Described RC goes here and there
Connection branch road is the resistance R and electric capacity C, the time constant (time of this RC series arm connected between supply voltage VCC and ground
Constant) microsecond (μ s) rank it is normally provided as.As a comparison, voltage rising time (rise when esd event occurs
Time) being usually nanosecond (ns) rank, voltage rising time when (power up) event that powers on occurs is typically millisecond (ms)
Rank.Described RC series arm junction point between resistance R and electric capacity C is referred to as node P0.Described phase inverter props up route one
Or the phase inverter composition of multiple cascade, the input of described phase inverter branch road connects node P0, and outfan connects clamping transistor
The grid of Tclamp i.e. node P1.The drain electrode of described clamping transistor Tclamp and source electrode connect supply voltage VCC respectively and connect
Ground.Clamping transistor Tclamp shown in Fig. 1 is nmos pass transistor, phase inverter branch road include three phase inverter Inv1 cascaded,
Inv2, Inv3, it is possible to change the cascade of any odd number phase inverter into.If clamping transistor Tclamp is PMOS transistor, then
Phase inverter branch road changes the cascade of any even number of inverters into.Under equal conditions, nmos pass transistor has more than PMOS transistor
Low conducting resistance, therefore clamping transistor Tclamp is preferably nmos pass transistor.
Fig. 2 gives a kind of specific implementation to the phase inverter in Fig. 1, each phase inverter by a PMOS transistor with
One nmos pass transistor is formed.Such as, phase inverter one Inv1 includes PMOS transistor one TP1 and nmos pass transistor one TN1.
The grid of PMOS transistor one TP1 and the grid of nmos pass transistor one TN1 are all connected with node P0 and as phase inverter one Inv1's
Input.The drain electrode of PMOS transistor one TP1 meets supply voltage VCC, and source electrode connects the drain electrode of nmos pass transistor one TN1 and as anti-
The outfan of phase device one Inv1.The source ground of nmos pass transistor one TN1.
RC clamp circuit shown in Fig. 1 is coupled between supply voltage VCC and ground.Replacing as one, it also can couple
Between the supply voltage of two different potentials, for realizing the ESD protection of power-supply system.
The operation principle that RC clamp circuit shown in Fig. 1 realizes ESD protection is as follows:
One, when esd event does not occurs, when the event that the most normally powers on occurs, electric capacity C has time enough to charge,
Therefore the voltage of node P0 is substantially identical with supply voltage VCC.In phase inverter one Inv1, PMOS transistor one TP1 turns off,
Nmos pass transistor one TN1 opens, and the output end voltage of phase inverter one Inv1 is zero.In phase inverter two Inv2, PMOS transistor
Two TP2 open, and nmos pass transistor two TN2 turns off, and the output end voltage of phase inverter two Inv2 is supply voltage VCC.At phase inverter
In three Inv3, PMOS transistor three TP3 turns off, and nmos pass transistor three TN3 opens, outfan (the i.e. node of phase inverter three Inv3
P1) voltage is zero.Owing to the grid voltage of clamping transistor Tclamp is low level, it is held off.
Its two, when an esd event occurs, supply voltage VCC raises suddenly, the drain voltage phase of clamping transistor Tclamp
Rising quick for source voltage.Electric capacity C response is too late, and the voltage of node P0 is closely in a short period of time.At phase inverter
In one Inv1, PMOS transistor one TP1 opens, and nmos pass transistor one TN1 turns off, and the output end voltage of phase inverter one Inv1 is electricity
Source voltage VCC.In phase inverter two Inv2, PMOS transistor two TP2 turns off, and nmos pass transistor two TN2 opens, phase inverter two
The output end voltage of Inv2 is zero.In phase inverter three Inv3, PMOS transistor three TP3 opens, and nmos pass transistor three TN3 closes
Disconnected, outfan (the i.e. node P1) voltage of phase inverter three Inv3 is supply voltage VCC.Grid due to clamping transistor Tclamp
Voltage is high level, and it is opened and drain electrode is conducted to source electrode.Described RC clamp circuit begins through clamping transistor Tclamp
Electric discharge, until supply voltage VCC recovers normal, clamping transistor Tclamp turns off again.
Publication No. CN1601746A, publication date are the description the 2nd of the Chinese invention patent application on March 30th, 2005
Page the 2nd section and Fig. 2 B discloses a kind of grid coupling electrostatic discharge protective equipment.Application publication number is CN103760444A, Shen
Please date of publication be that the description 0004 section and Fig. 1 to Fig. 2 of Chinese invention patent application on April 30th, 2014 discloses one
ESD transient state detection circuit.Application publication number is CN103915828A, Shen Qing Publication day is that the Chinese invention on July 9th, 2014 is special
Description 0004 section to 0005 section and Fig. 1 of profit application discloses a kind of RC trigger-type esd protection circuit.Application publication number is
CN104348148A, Shen Qing Publication day are that the description 0004 section of the Chinese invention patent application on February 11st, 2015 is to 0005
Section and Fig. 2 disclose a kind of ESD (Electrostatic Discharge) clamp circuit.Circuit structure disclosed in document above is similar with operation principle
In Fig. 1 of the application, and it is typically designed to the most externally export control signal.
Some IC chip includes sensitive circuit unit, realizes ESD protection at the RC clamp circuit shown in Fig. 1
In action time (usually nanosecond rank), the transient current that static discharge produces still can flow through these sensitive circuit unit,
And be likely to result in sensitive circuit unit due to cross stream and damage, may finally affect whole chip cannot normally work.
Summary of the invention
Technical problems to be solved in this application are to provide a kind of ESD protection circuit, it is possible in the extremely short effect of ESD protection
Protection is provided to the sensitive circuit unit in IC chip, it is ensured that these sensitive circuit unit are safe and reliable in time.
For solving above-mentioned technical problem, the application one ESD protection circuit includes: at the electricity of sensitive circuit unit
First switching device is set on source channels, closes the first switching device when electrostatic discharge event does not occurs so that sensitive circuit list
Unit's normal power supply, disconnects the first switching device so that the power channel of sensitive circuit unit is broken when electrostatic discharge event occurs
Road；
And/or, driving element is set to the original switching device in the power channel controlling sensitive circuit unit, works as electrostatic
When electric discharge event does not occurs, driving element does not affect original switching device so that sensitive circuit unit normally works, and works as static discharge
When event occurs, driving element disconnects original switching device so that the power channel of sensitive circuit unit is switched off；
And/or, in the power channel that sensitive circuit unit is connected with non-sensitive circuit unit, arrange and sensitive circuit list
The second switch device that unit is in parallel, disconnects second switch device so that sensitive circuit unit when electrostatic discharge event does not occurs
Normal power supply, closes second switch device so that sensitive circuit unit is short in power channel when electrostatic discharge event occurs
Road.
Existing ESD protection circuit have ignored the protection when esd event occurs to sensitive circuit unit, and the application is to this
Give solution, sensitive circuit unit can be avoided to damage owing to crossing stream, thus improve whole IC chip
Reliability, the anti-ESD ability of circuit is greatly improved.The ESD protection circuit of the application is on the basis of available circuit structure
Only need to increase a small amount of device, from existing RC clamp circuit, the signal of acquisition node P1 is used to refer to whether esd event occurs,
And with this signal, the power channel of sensitive circuit unit being carried out open circuit or short circuit, it is achieved mode is easy and cost is relatively low.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of a kind of existing ESD protection circuit.
Fig. 2 is the specific implementation schematic diagram of the phase inverter in Fig. 1.
Fig. 3 to Fig. 8 is the circuit diagram of embodiment one to the embodiment six of the ESD protection circuit of the application respectively.
Fig. 9 a to Fig. 9 c is the different structure schematic diagram of the first implementation of the ESD protection circuit of the application.
Figure 10 a to Figure 10 c is the different structure schematic diagram of the second implementation of the ESD protection circuit of the application.
Figure 11 a to Figure 11 d is the different structure schematic diagram of the third implementation of the ESD protection circuit of the application.
Description of reference numerals in figure: VCC is supply voltage；R is resistance；C is electric capacity；Tclamp is clamping transistor；
Invx is phase inverter (x is natural number)；TNx is nmos pass transistor (x is natural number)；TPx is that (x is nature to PMOS transistor
Number)；Blockx is circuit unit (x is natural number).
Detailed description of the invention
Referring to Fig. 3, this is the embodiment one of ESD protection circuit of the application.Fig. 3 is divided into two, left and right by chain-dotted line
Point, left side circuit is to add nmos pass transistor five TN5 on the basis of existing RC clamp circuit, is newly-increased circuit.Right side
Circuit is to be provided with switching device in the power channel of sensitive circuit unit, is original circuit.Such as, sensitive circuit unit is
Circuit unit one Block1, needs to be protected within the action time of ESD protection；Switching device is nmos pass transistor six TN6.
The power end of circuit unit one Block1 connects the earth terminal of supply voltage VCC, circuit unit one Block1 and connects NMOS crystal
The drain electrode of pipe six TN6, the source ground of nmos pass transistor six TN6.
Described RC clamp circuit includes a RC series arm, a phase inverter branch road and a clamping transistor
Tclamp.Described RC series arm be between supply voltage VCC and ground or two different potentials supply voltage it
Between resistance R and the electric capacity C of series connection, the time constant of this RC series arm is normally provided as microsecond rank.Described RC series connection
Road junction point between resistance R and electric capacity C is referred to as node P0.Described phase inverter props up route odd number and (works as clamping transistor
When Tclamp is nmos pass transistor) or the inverter group that cascades of even number (when clamping transistor Tclamp is PMOS transistor)
Becoming, input connects node P0, and outfan connects the grid of clamping transistor Tclamp.Described clamping transistor Tclamp is
Nmos pass transistor or PMOS transistor, grid is referred to as node P1, drain electrode be connected respectively with source electrode supply voltage VCC and or
Connect two supply voltages of high and low current potential respectively.
In the embodiment one of the ESD protection circuit shown in Fig. 3, described node P1 is also connected with the grid of nmos pass transistor five TN5
Pole, the drain electrode of nmos pass transistor five TN5 is referred to as node P2 and connects the grid of nmos pass transistor six TN6, nmos pass transistor five TN5
Source ground.The grid of nmos pass transistor six TN6 may also have other and control connecting line, and Fig. 3 does not draws.
The operation principle that the embodiment one of the ESD protection circuit of the application realizes ESD protection is as follows:
One, when esd event does not occurs, when the event that the most normally powers on occurs, node P1 is low level, NMOS crystal
Pipe five TN5 turns off, and the grid voltage of pair nmos transistor six TN6 has no effect.The now unlatching shape of nmos pass transistor six TN6
State is controlled connecting line by other and determines.
Its two, when an esd event occurs, supply voltage VCC extremely short action time (usually nanosecond rank, for example,
Hundreds of nanosecond) in voltage be gradually lowered by height, now node P1 is high level, nmos pass transistor five TN5 open and by node
The voltage of P2 is forced down for low level.Nmos pass transistor six TN6 turns off, thus by the supply voltage of circuit unit one Block1
VCC cuts off to the path on ground, and the electric current that now esd event produces is without going past sensitive circuit unit one Block1, thus real
Show the protection to sensitive circuit unit.
Referring to Fig. 4, this is the embodiment two of ESD protection circuit of the application.Fig. 4 is also divided into two, left and right by chain-dotted line
Point, left side circuit is to add phase inverter four Inv4 and PMOS transistor five TP5 on the basis of existing RC clamp circuit, is
Newly-increased circuit.Right side circuit is to be provided with switching device in the power channel of sensitive circuit unit, is original circuit.Such as,
Sensitive circuit unit is circuit unit one Block1, needs to be protected within the action time of ESD protection；Switching device is
PMOS transistor six TP6.The source electrode of PMOS transistor six TP6 connects supply voltage VCC, and drain electrode connects circuit unit one Block1
Power end, the earth terminal ground connection of circuit unit one Block1.
Described RC clamp circuit includes a RC series arm, a phase inverter branch road and a clamping transistor
Tclamp.Described RC series arm be between supply voltage VCC and ground or two different potentials supply voltage it
Between resistance R and the electric capacity C of series connection, the time constant of this RC series arm is normally provided as microsecond rank.Described RC series connection
Road junction point between resistance R and electric capacity C is referred to as node P0.Described phase inverter props up route odd number and (works as clamping transistor
When Tclamp is nmos pass transistor) or the inverter group that cascades of even number (when clamping transistor Tclamp is PMOS transistor)
Becoming, input connects node P0, and outfan connects the grid of clamping transistor Tclamp.Described clamping transistor Tclamp is
Nmos pass transistor or PMOS transistor, grid is referred to as node P1, drain electrode be connected respectively with source electrode supply voltage VCC and or
Connect two supply voltages of high and low current potential respectively.
In the embodiment two of the ESD protection circuit shown in Fig. 4, described node P1 is also connected with the input of phase inverter four Inv4
End, the i.e. node P2 of the outfan of phase inverter four Inv4 connects the grid of PMOS transistor five TP5, the source of PMOS transistor five TP5
Pole connects the drain electrode of supply voltage VCC, PMOS transistor five TP5 and is referred to as node P3 and connects the grid of PMOS transistor six TP6.
The grid of PMOS transistor six TP6 may also have other and control connecting line, and Fig. 4 does not draws.
The operation principle that the embodiment two of the ESD protection circuit of the application realizes ESD protection is as follows:
One, when esd event does not occurs, when the event that the most normally powers on occurs, node P1 is low level, and node P2 is
High level, PMOS transistor five TP5 turns off, and the grid voltage of pair pmos transistor six TP6 has no effect.Now PMOS crystal
The opening of pipe six TP6 is controlled connecting line by other and determines.
Its two, when an esd event occurs, supply voltage VCC extremely short action time (usually nanosecond rank, for example,
Hundreds of nanosecond) in voltage be gradually lowered by height, now node P1 is high level, and node P2 is low level, PMOS transistor five
TP5 opens and forces to draw high as high level by the voltage of node P3.PMOS transistor six TP6 turns off, thus by circuit unit one
The supply voltage VCC of Block1 cuts off to the path on ground, and the electric current that now esd event produces is without going past sensitive circuit unit
One Block1, it is achieved thereby that the protection to sensitive circuit unit.
Referring to Fig. 5, this is the embodiment three of ESD protection circuit of the application.Fig. 5 is also divided into two, left and right by chain-dotted line
Point, left side circuit is to add phase inverter five Inv5 and nmos pass transistor seven TN7 on the basis of existing RC clamp circuit, is
Newly-increased circuit.Right side circuit is a sensitive circuit unit, is original circuit.Such as, sensitive circuit unit is circuit unit one
Block1, needs to be protected within the action time of ESD protection.The power end of circuit unit one Block1 connects supply voltage
VCC。
Described RC clamp circuit includes a RC series arm, a phase inverter branch road and a clamping transistor
Tclamp.Described RC series arm be between supply voltage VCC and ground or two different potentials supply voltage it
Between resistance R and the electric capacity C of series connection, the time constant of this RC series arm is normally provided as microsecond rank.Described RC series connection
Road junction point between resistance R and electric capacity C is referred to as node P0.Described phase inverter props up route odd number and (works as clamping transistor
When Tclamp is nmos pass transistor) or the inverter group that cascades of even number (when clamping transistor Tclamp is PMOS transistor)
Becoming, input connects node P0, and outfan connects the grid of clamping transistor Tclamp.Described clamping transistor Tclamp is
Nmos pass transistor or PMOS transistor, grid is referred to as node P1, drain electrode be connected respectively with source electrode supply voltage VCC and or
Connect two supply voltages of high and low current potential respectively.
In the embodiment three of the ESD protection circuit shown in Fig. 5, described node P1 is also connected with the input of phase inverter five Inv5
End, the i.e. node P2 of the outfan of phase inverter five Inv5 connects the grid of nmos pass transistor seven TN7, the leakage of nmos pass transistor seven TN7
Pole connects the earth terminal of circuit unit one Block1, the source ground of nmos pass transistor seven TN7.
The operation principle that the embodiment three of the ESD protection circuit of the application realizes ESD protection is as follows:
One, when esd event does not occurs, when the event that the most normally powers on occurs, node P1 is low level, and node P2 is
High level, nmos pass transistor seven TN7 opens, and circuit unit one Block1 obtains normal power supply thus can normally work.
Its two, when an esd event occurs, supply voltage VCC extremely short action time (usually nanosecond rank, for example,
Hundreds of nanosecond) in voltage be gradually lowered by height, now node P1 is high level, and node P2 is low level, nmos pass transistor seven
TN7 turns off, thus is cut off by the path of the supply voltage VCC of circuit unit one Block1 to ground, the electricity that now esd event produces
Flow without going past sensitive circuit unit one Block1, it is achieved thereby that the protection to sensitive circuit unit.
Referring to Fig. 6, this is the embodiment four of ESD protection circuit of the application.Fig. 6 is also divided into two, left and right by chain-dotted line
Point, left side circuit is to add PMOS transistor seven TP7 on the basis of existing RC clamp circuit, is newly-increased circuit.Right side
Circuit is a sensitive circuit unit, is original circuit.Such as, sensitive circuit unit is circuit unit one Block1, needs
Protected in the action time of ESD protection.The earth terminal ground connection of circuit unit one Block1.
Described RC clamp circuit includes a RC series arm, a phase inverter branch road and a clamping transistor
Tclamp.Described RC series arm be between supply voltage VCC and ground or two different potentials supply voltage it
Between resistance R and the electric capacity C of series connection, the time constant of this RC series arm is normally provided as microsecond rank.Described RC series connection
Road junction point between resistance R and electric capacity C is referred to as node P0.Described phase inverter props up route odd number and (works as clamping transistor
When Tclamp is nmos pass transistor) or the inverter group that cascades of even number (when clamping transistor Tclamp is PMOS transistor)
Becoming, input connects node P0, and outfan connects the grid of clamping transistor Tclamp.Described clamping transistor Tclamp is
Nmos pass transistor or PMOS transistor, grid is referred to as node P1, drain electrode be connected respectively with source electrode supply voltage VCC and or
Connect two supply voltages of high and low current potential respectively.
In the embodiment four of the ESD protection circuit shown in Fig. 6, described node P1 is also connected with the grid of PMOS transistor seven TP7
Pole, the source electrode of PMOS transistor seven TP7 connects the drain electrode of supply voltage VCC, PMOS transistor seven TP7 and connects circuit unit one
The power end of Block1.
The operation principle that the embodiment four of the ESD protection circuit of the application realizes ESD protection is as follows:
One, when esd event does not occurs, when the event that the most normally powers on occurs, node P1 is low level, PMOS crystal
Pipe seven TP7 opens, and circuit unit one Block1 obtains normal power supply thus can normally work.
Its two, when an esd event occurs, supply voltage VCC extremely short action time (usually nanosecond rank, for example,
Hundreds of nanosecond) in voltage be gradually lowered by height, now node P1 is high level, and PMOS transistor seven TP7 turns off, thus by electricity
The supply voltage VCC of road unit one Block1 cuts off to the path on ground, and the electric current that now esd event produces is without going past sensitivity
Circuit unit one Block1, it is achieved thereby that the protection to sensitive circuit unit.
Referring to Fig. 7, this is the embodiment five of ESD protection circuit of the application.Fig. 7 is also divided into two, left and right by chain-dotted line
Point, left side circuit is to add nmos pass transistor eight TN8 on the basis of existing RC clamp circuit, is newly-increased circuit.Right side
Circuit is at least one sensitive circuit unit and the connecting of at least one non-sensitive circuit unit, a termination electricity of this series arm
Source voltage VCC, other end ground connection, is original circuit.Such as, sensitive circuit unit is circuit unit one Block1, needs at ESD
Protected in the action time of protection.Non-sensitive circuit unit is circuit unit two Block2, can bear esd event and produce
Electric current.
Described RC clamp circuit includes a RC series arm, a phase inverter branch road and a clamping transistor
Tclamp.Described RC series arm be between supply voltage VCC and ground or two different potentials supply voltage it
Between resistance R and the electric capacity C of series connection, the time constant of this RC series arm is normally provided as microsecond rank.Described RC series connection
Road junction point between resistance R and electric capacity C is referred to as node P0.Described phase inverter props up route odd number and (works as clamping transistor
When Tclamp is nmos pass transistor) or the inverter group that cascades of even number (when clamping transistor Tclamp is PMOS transistor)
Becoming, input connects node P0, and outfan connects the grid of clamping transistor Tclamp.Described clamping transistor Tclamp is
Nmos pass transistor or PMOS transistor, grid is referred to as node P1, drain electrode be connected respectively with source electrode supply voltage VCC and or
Connect two supply voltages of high and low current potential respectively.
In the embodiment five of the ESD protection circuit shown in Fig. 7, described node P1 is also connected with the grid of nmos pass transistor eight TN8
Pole, the drain electrode of nmos pass transistor eight TN8 connects the power end of circuit unit one Block1, and the source electrode of nmos pass transistor eight TN8 connects
Ground.
The operation principle that the embodiment eight of the ESD protection circuit of the application realizes ESD protection is as follows:
One, when esd event does not occurs, when the event that the most normally powers on occurs, node P1 is low level, NMOS crystal
Pipe eight TN8 turns off.Circuit unit one Block1 of series connection all can be powered with circuit unit two Block2 and normally be worked.
Its two, when an esd event occurs, supply voltage VCC extremely short action time (usually nanosecond rank, for example,
Hundreds of nanosecond) in voltage be gradually lowered by height, now node P1 is high level, and nmos pass transistor eight TN8 opens and by drain electrode
With source shorted.Supply voltage VCC passes through nmos pass transistor eight TN8 opened after insensitive circuit unit two Block2
Ground connection, and got around circuit unit one Block1 of sensitivity.Therefore the electric current that esd event produces is without going past sensitive circuit list
Unit one Block1, thus prevent this partial circuit to damage because electric current is excessive.
Referring to Fig. 8, this is the embodiment six of ESD protection circuit of the application.Fig. 8 is also divided into two, left and right by chain-dotted line
Point, left side circuit is to add phase inverter six Inv6 and PMOS transistor eight TP8 on the basis of existing RC clamp circuit, is
Newly-increased circuit.Right side circuit is at least one sensitive circuit unit and the connecting of at least one non-sensitive circuit unit, this series connection
One termination supply voltage VCC of branch road, other end ground connection, is original circuit.Such as, sensitive circuit unit is circuit unit one
Block1, needs to be protected within the action time of ESD protection.Non-sensitive circuit unit is circuit unit two Block2, can
To bear the electric current that esd event produces.
Described RC clamp circuit includes a RC series arm, a phase inverter branch road and a clamping transistor
Tclamp.Described RC series arm be between supply voltage VCC and ground or two different potentials supply voltage it
Between resistance R and the electric capacity C of series connection, the time constant of this RC series arm is normally provided as microsecond rank.Described RC series connection
Road junction point between resistance R and electric capacity C is referred to as node P0.Described phase inverter props up route odd number and (works as clamping transistor
When Tclamp is nmos pass transistor) or the inverter group that cascades of even number (when clamping transistor Tclamp is PMOS transistor)
Becoming, input connects node P0, and outfan connects the grid of clamping transistor Tclamp.Described clamping transistor Tclamp is
Nmos pass transistor or PMOS transistor, grid is referred to as node P1, drain electrode be connected respectively with source electrode supply voltage VCC and or
Connect two supply voltages of high and low current potential respectively.
In the embodiment six of the ESD protection circuit shown in Fig. 8, described node P1 is also connected with the input of phase inverter six Inv6
End, the outfan of phase inverter six Inv6 connects the grid of PMOS transistor eight TP8, and the source electrode of PMOS transistor eight TP8 connects electricity
The drain electrode of source voltage VCC, PMOS transistor eight TP8 connects the earth terminal of circuit unit one Block1.
The operation principle that the embodiment eight of the ESD protection circuit of the application realizes ESD protection is as follows:
One, when esd event does not occurs, when the event that the most normally powers on occurs, node P1 is low level, phase inverter six
Inv6 exports high level, and PMOS transistor eight TP8 turns off.Circuit unit one Block1 of series connection is equal with circuit unit two Block2
Can be powered and normally be worked.
Its two, when an esd event occurs, supply voltage VCC extremely short action time (usually nanosecond rank, for example,
Hundreds of nanosecond) in voltage be gradually lowered by height, now node P1 is high level, phase inverter six Inv6 output low level, PMOS
Transistor eight TP8 opens and by drain electrode and source shorted.Supply voltage VCC is after PMOS transistor eight TP8 opened, then leads to
Cross insensitive circuit unit two Block2 ground connection, and get around circuit unit one Block1 of sensitivity.Therefore esd event produces
Electric current without going past sensitive circuit unit one Block1, thus prevent this partial circuit to damage because electric current is excessive.
Various embodiments above can be optionally combined, such as can be by the embodiment shown in the embodiment one shown in Fig. 3, Fig. 4
Two, the embodiment three shown in Fig. 5 merges.
Comprehensive above six embodiments, the ESD protection main circuit of the application to use following three kinds of modes to sensitive circuit
Unit is protected when esd event occurs.
First kind of way is that original circuit comprises sensitive circuit unit.The ESD protection circuit of the application is just at sensitive circuit
In the power channel of unit, newly-increased switching device, closes this switching device when an esd event occurs, so that sensitive circuit unit
Power channel be switched off, thus ESD electric current cannot be introduced into sensitive circuit unit, such as shown in Fig. 9 a, Fig. 9 b.Become as one
Multiple sensitive circuit unit can be in series in power channel, only need to arrange one in the power channel of this series connection by shape
Switching device, such as shown in Fig. 9 c.This implementation corresponds to the embodiment four shown in the embodiment three shown in Fig. 5, Fig. 6.
First kind of way is that original circuit comprises and comprises on sensitive circuit unit, and the power channel of sensitive circuit unit
Original switching device.The most newly-increased driving element of the ESD protection circuit of the application controls original switching device, when esd event is sent out
Closing original switching device time raw, so that the power channel of sensitive circuit unit is switched off, thus ESD electric current cannot be introduced into quick
Inductive circuit unit, such as shown in Figure 10 a, Figure 10 b.Deform as one, can be by multiple sensitive circuit unit in power channel
On be in series, the power channel of this series connection only needs arrange a switching device, such as shown in Figure 10 c.This implementation
Corresponding to the embodiment two shown in the embodiment one shown in Fig. 3, Fig. 4.
The third mode is that original circuit comprises sensitive circuit unit and non-sensitive circuit unit, and they are mutually gone here and there
Connection.The ESD protection circuit of the application just in the power channel that sensitive circuit unit is connected with non-sensitive circuit unit newly-increased with
The switching device that sensitive circuit unit is in parallel.Open this switching device when an esd event occurs, so that sensitive circuit unit
Power channel is shorted, thus ESD electric current cannot be introduced into sensitive circuit unit, such as shown in Figure 11 a, Figure 11 b.As one
Plant deformation, one or more non-sensitive circuit units can be gone here and there with one or more sensitive circuit unit in power channel mutually
Connection, at least needs to arrange a switching device and carries out in parallel in power channel, extremely with all sensitive circuit unit being in series
Need to arrange with the switching device of sensitive circuit unit equal number more respectively with each sensitive circuit unit in power channel
On carry out parallel connection, such as shown in Figure 11 c, Figure 11 d.This implementation is corresponding to shown in the embodiment five shown in Fig. 7, Fig. 8
Embodiment six.
Existing ESD protection circuit have ignored the protection when esd event occurs to sensitive circuit unit, and the application is to this
Give solution, sensitive circuit unit can be avoided to damage owing to crossing stream, thus improve whole IC chip
Reliability, the anti-ESD ability of circuit is greatly improved.The ESD protection circuit of the application is on the basis of available circuit structure
Only need to increase a small amount of device, it is achieved mode is easy and cost is relatively low.
These are only the preferred embodiment of the application, be not used to limit the application.Those skilled in the art is come
Saying, the application can have various modifications and variations.All within spirit herein and principle, any amendment of being made, equivalent
Replacement, improvement etc., within should be included in the protection domain of the application.
Claims (10)
1. an ESD protection circuit, is characterized in that, arranges switching device in the power channel of sensitive circuit unit, when
This switching device is closed so that sensitive circuit unit normal power supply, when electrostatic discharge event occurs when electrostatic discharge event does not occurs
Time disconnect this switching device so that the power channel of sensitive circuit unit is switched off；
And/or, driving element is set to the original switching device in the power channel controlling sensitive circuit unit, works as static discharge
When event does not occurs, driving element does not affect original switching device so that sensitive circuit unit normally works, and works as electrostatic discharge event
During generation, driving element disconnects original switching device so that the power channel of sensitive circuit unit is switched off；
And/or, in the power channel that sensitive circuit unit is connected with non-sensitive circuit unit, arrange and sensitive circuit unit phase
Switching device in parallel, disconnects this switching device so that sensitive circuit unit normal power supply when electrostatic discharge event does not occurs,
This switching device is closed so that sensitive circuit unit is shorted in power channel when electrostatic discharge event occurs.
ESD protection circuit the most according to claim 1, is characterized in that, described ESD protection circuit includes RC
Clamp circuit and nmos pass transistor five；
Described RC clamp circuit includes clamping transistor；The grid of described clamping transistor is referred to as node P1, connects NMOS crystal
The grid of pipe five, the original switching device in the power channel of the drain drives sensitive circuit unit of nmos pass transistor five；
When there is not electrostatic discharge event, node P1 is low level, and nmos pass transistor five turns off, the power supply to sensitive circuit unit
Original switching device on passage is without impact；
When there is electrostatic discharge event, node P1 is high level, and nmos pass transistor five is opened and by the power supply of sensitive circuit unit
Original switching device on passage is forced shutdown, thus the power channel of sensitive circuit unit cut off, it is to avoid static discharge
The electric current that event produces is through sensitive circuit unit.
ESD protection circuit the most according to claim 1, is characterized in that, described ESD protection circuit includes RC
Clamp circuit, phase inverter four and PMOS transistor five；
Described RC clamp circuit includes clamping transistor；The grid of described clamping transistor is referred to as node P1, connects phase inverter four
Input, the i.e. node P2 of the outfan of phase inverter four connect PMOS transistor five TP5 grid, the drain electrode of PMOS transistor five
Drive the original switching device in the power channel of sensitive circuit unit；
When there is not electrostatic discharge event, node P1 is low level, and node P2 is high level, and PMOS transistor five turns off, to quick
Original switching device in the power channel of inductive circuit unit is without impact；
When there is electrostatic discharge event, node P1 is high level, and node P2 is low level, and PMOS transistor five is opened and by sensitivity
Original switching device in the power channel of circuit unit is forced shutdown, thus the power channel of sensitive circuit unit is cut off,
Avoid the electric current of electrostatic discharge event generation through sensitive circuit unit.
ESD protection circuit the most according to claim 1, is characterized in that, described ESD protection circuit includes RC
Clamp circuit, phase inverter five and nmos pass transistor seven；
Described RC clamp circuit includes clamping transistor；The grid of described clamping transistor is referred to as node P1, connects phase inverter five
Input, the i.e. node P2 of the outfan of phase inverter five connect nmos pass transistor seven grid, nmos pass transistor seven is arranged on quick
In the power channel of inductive circuit unit；
When there is not electrostatic discharge event, node P1 is low level, and node P2 is high level, and nmos pass transistor seven is opened, sensitive
Circuit unit obtains normal power supply；
When there is electrostatic discharge event, node P1 is high level, and node P2 is low level, and nmos pass transistor seven turns off, thus will
The power channel of sensitive circuit unit is cut off, it is to avoid the electric current that electrostatic discharge event produces is through sensitive circuit unit.
ESD protection circuit the most according to claim 1, is characterized in that, described ESD protection circuit includes RC
Clamp circuit and PMOS transistor seven；
Described RC clamp circuit includes clamping transistor；The grid of described clamping transistor is referred to as node P1, connects PMOS crystal
The grid of pipe seven, PMOS transistor seven is arranged in the power channel of sensitive circuit unit；
When there is not electrostatic discharge event, node P1 is low level, and PMOS transistor seven is opened, and sensitive circuit unit obtains normally
Power supply；
When there is electrostatic discharge event, node P1 is high level, and PMOS transistor seven turns off, thus by the electricity of sensitive circuit unit
Source channels cuts off, it is to avoid the electric current that electrostatic discharge event produces is through sensitive circuit unit.
ESD protection circuit the most according to claim 1, is characterized in that, described ESD protection circuit includes RC
Clamp circuit and nmos pass transistor eight；
Described RC clamp circuit includes clamping transistor；The grid of described clamping transistor is referred to as node P1, connects NMOS crystal
The grid of pipe eight, nmos pass transistor eight is in parallel in power channel with sensitive circuit unit；
When there is not electrostatic discharge event, node P1 is low level, and nmos pass transistor eight turns off, and sensitive circuit unit obtains normally
Power supply；
When there is electrostatic discharge event, node P1 is high level, and nmos pass transistor eight is opened and by sensitive circuit unit at power supply
Short circuit on passage, it is to avoid the electric current that electrostatic discharge event produces is through sensitive circuit unit.
ESD protection circuit the most according to claim 1, is characterized in that, described ESD protection circuit includes RC
Clamp circuit, phase inverter six and PMOS transistor eight；
Described RC clamp circuit includes clamping transistor；The grid of described clamping transistor is referred to as node P1, connects phase inverter six
Input, the outfan of phase inverter six connects the grid of PMOS transistor eight, and PMOS transistor eight and sensitive circuit unit exist
It is in parallel in power channel；
When there is not electrostatic discharge event, node P1 is low level, and phase inverter six exports high level, and PMOS transistor eight turns off,
Sensitive circuit unit obtains normal power supply；
Occur electrostatic discharge event time, node P1 is high level, phase inverter six output low level, PMOS transistor eight open and incite somebody to action
Sensitive circuit unit is short circuit in power channel, it is to avoid the electric current that electrostatic discharge event produces is through sensitive circuit unit.
8. according to the ESD protection circuit according to any one of claim 2 to 7, it is characterized in that, described RC clamp circuit
Also include RC series arm and phase inverter branch road；
Described RC series arm is to connect between supply voltage with ground or between the supply voltage of two different potentials
Resistance and electric capacity, the time constant of this RC series arm is set to microsecond rank；Described RC series arm is at resistance and electric capacity
Between junction point be referred to as node P0；
Described phase inverter props up the phase inverter composition routeing one or more cascades, and input connects node P0, outfan connecting joint
Point P1；
Described clamping transistor is nmos pass transistor or PMOS transistor；When clamping transistor is nmos pass transistor, described instead
Phase device props up route odd number inverter stage joint group and becomes；When clamping transistor is PMOS transistor, it is even that described phase inverter props up route
Several inverter stage joint groups become；The drain electrode of described clamping transistor is connected supply voltage and ground respectively or connects respectively with source electrode
Connect two supply voltages of high and low current potential.
ESD protection circuit the most according to claim 1, is characterized in that, multiple sensitive circuit unit are in power channel
Upper series connection, arranges switching device in the power channel of this series connection；
And/or, driving element is set to the original switching device in the power channel controlling the series connection of multiple sensitive circuit unit.
ESD protection circuit the most according to claim 1, is characterized in that, one or more non-sensitive circuit units
Be in series in power channel with one or more sensitive circuit unit, arrange one or more switching device and with all sensitivities
Circuit unit carries out parallel connection in power channel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201610794520.3A CN106229953A (en) | 2016-08-31 | 2016-08-31 | A kind of ESD protection circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610794520.3A CN106229953A (en) | 2016-08-31 | 2016-08-31 | A kind of ESD protection circuit |
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| CN106229953A true CN106229953A (en) | 2016-12-14 |
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| CN201610794520.3A Pending CN106229953A (en) | 2016-08-31 | 2016-08-31 | A kind of ESD protection circuit |
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| CN111211673A (en) * | 2020-01-10 | 2020-05-29 | 伟芯科技(绍兴)有限公司 | ESD power protection clamping circuit |
| WO2021196990A1 (en) * | 2020-04-03 | 2021-10-07 | 长鑫存储技术有限公司 | Test circuit and semiconductor test method |
| CN113552457A (en) * | 2020-04-03 | 2021-10-26 | 长鑫存储技术有限公司 | Test circuit and semiconductor test method |
| CN114498596A (en) * | 2022-03-29 | 2022-05-13 | 武汉市聚芯微电子有限责任公司 | Electrostatic protection circuit, electrostatic protection method and integrated circuit |
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