CN106227695A - The programming I/O of FPGA and the optimization method of user I/O and device - Google Patents

The programming I/O of FPGA and the optimization method of user I/O and device Download PDF

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Publication number
CN106227695A
CN106227695A CN201610569902.6A CN201610569902A CN106227695A CN 106227695 A CN106227695 A CN 106227695A CN 201610569902 A CN201610569902 A CN 201610569902A CN 106227695 A CN106227695 A CN 106227695A
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China
Prior art keywords
programming
user
fpga device
fpga
programmable controller
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CN201610569902.6A
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Chinese (zh)
Inventor
朱璟辉
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Guangdong High Cloud Semiconductor Technologies Ltd Co
Gowin Semiconductor Corp
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Guangdong High Cloud Semiconductor Technologies Ltd Co
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Priority to CN201610569902.6A priority Critical patent/CN106227695A/en
Publication of CN106227695A publication Critical patent/CN106227695A/en
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G06F15/7871Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

The present invention provides the programming I/O of a kind of FPGA and the optimization method of user I/O and device, and the MODE pin value in programming I/O is set and then determines the programming mode of FPGA device by arranging programmable controller by method;Colleague, by one or more MODE pins connect ground or the power supply of encapsulation in advance, is not connected to off-chip circuit, and then reduces taking of user's I/O resource, it is achieved that same wafer is for different packaged types and then saves production cost, reduces customer using cost.

Description

The programming I/O of FPGA and the optimization method of user I/O and device
Technical field
The present invention relates to integrated circuit fields, more particularly, to programming I/O and the optimization of user I/O of a kind of FPGA Method and device.
Background technology
FPAG wafer is a kind of wafer that can the most again the control formula needed be inputted, and it is not fixing Circuit, but a kind of optionally can change the wafer of function, its function can change along with the data of input.Different User can design the intellectual property of oneself on FPGA, applies in different fields.The intellectual property of user is with data streaming file Form be stored in FPGA device, make FPGA produce the function required for user.
Due to the general-purpose device characteristic of FPGA, in different application field, the programming mode of FPGA also there is different requirements. Existing FPGA is almost without being programmed with processor, but has carried out the programming of various ways by the value of pin Through becoming the standing procedure of industry, and different programmed configurations, the number of required programmable I/O pin is very different.Also it is Due to the versatility of FPGA, for meeting the demand of user, FPGA device needs to provide multiple packing forms to meet user not The demand of same domain.As in consumer electronics field, user needs little and thin encapsulation.At field of telecommunications, user needs pin many And the encapsulation that reliability is high.Owing to wafer cost is far above packaging cost, same wafer is often made different by current manufacturer Encapsulation.Make the two requirement of different encapsulation from previously described programming mode from same wafer, in actual applications will Produce contradiction.
Such as, if a device is for the encapsulation of mobile phone, removing power supply and programming pin, the pin that user can use only remains Lower 7.If at this moment also needing to the MODE pin of 3 programming modes alternatively, user can the most remaining 4.This Sample cannot be applied after several.But the fields such as same wafer package becomes the wafer for communication, Industry Control, because user needs A lot of I/O pin and multiple programming mode.Thus need to select the MODE pin of programming mode.
Such contradiction, current solution is that the two kinds of situations said above are made two different wafers.Due to Wafer cost is the highest.It will be apparent that ultimately increase the use cost of user.
Summary of the invention
The present invention provides programming I/O and the optimization method of user I/O of a kind of FPGA, the method can make same wafer for Different packaged types and then saving production cost, reduce customer using cost.
A further object of the present invention is to provide a kind of FPGA device being optimized programming I/O and user I/O.
In order to reach above-mentioned technique effect, technical scheme is as follows:
The programming I/O of a kind of FPGA and the optimization method of user I/O, comprise the following steps:
S1: programmable controller is set the MODE pin value in programming I/O is set and then determines the volume of FPGA device Journey pattern;
S2: by one or more MODE pins being connect in advance ground or the power supply of encapsulation, be not connected to off-chip circuit, and then Reduce taking of user's I/O resource.
Further, described programmable controller is connected with the on-chip memory of FPGA device by unique interface, programming Controller is by this whole FPGA device of unique interface management.
Further, all can carry out by programmable controller volume when FPGA device powers on or during not power down reprogramming MODE pin value in journey I/O is set and then determines the programming mode of FPGA device.
Further, when FPGA device powers on and during not power down reprogramming, programmable controller is by different loadings MODE pin information is read out by program.
A kind of FPGA device that programming I/O and user I/O is optimized, including:
Programmable controller, for being set the MODE pin value in programming I/O and then determine the programming of FPGA device Pattern, programmable controller is connected with programming I/O;
The definable programmable logic cells of user, for being written and read the data of user;
On-chip memory unit, is used for storing programming data and controlling programmable logic array in real time, sheet Upper memory portion unit is connected with user I/O.
Further, described programmable controller is connected with the on-chip memory of FPGA device by unique interface, programming Controller is by this whole FPGA device of unique interface management.
Further, all can carry out by programmable controller volume when FPGA device powers on or during not power down reprogramming MODE pin value in journey I/O is set and then determines the programming mode of FPGA device.
Further, when FPGA device powers on and during not power down reprogramming, programmable controller is by different loadings MODE pin information is read out by program.
Compared with prior art, technical solution of the present invention provides the benefit that:
MODE pin value in programming I/O is set and then determines FPGA device by arranging programmable controller by the present invention The programming mode of part;Colleague, by one or more MODE pins connect ground or the power supply of encapsulation in advance, is not connected to sheet outside line Road, and then reduce taking of user's I/O resource, it is achieved that same wafer produces into for different packaged types and then saving This, reduce customer using cost.
Accompanying drawing explanation
Fig. 1 is the inventive method flow chart;
Fig. 2 is device junction composition of the present invention.
Detailed description of the invention
Accompanying drawing being merely cited for property explanation, it is impossible to be interpreted as the restriction to this patent;
In order to the present embodiment is more preferably described, some parts of accompanying drawing have omission, zoom in or out, and do not represent actual product Size;
To those skilled in the art, in accompanying drawing, some known features and explanation thereof may be omitted is to be appreciated that 's.
With embodiment, technical scheme is described further below in conjunction with the accompanying drawings.
Embodiment 1
As it is shown in figure 1, the programming I/O of a kind of FPGA and the optimization method of user I/O, comprise the following steps:
S1: programmable controller is set the MODE pin value in programming I/O is set and then determines the volume of FPGA device Journey pattern;
S2: by one or more MODE pins being connect in advance ground or the power supply of encapsulation, be not connected to off-chip circuit, and then Reduce taking of user's I/O resource.
Programmable controller is connected with the on-chip memory of FPGA device by unique interface, and programmable controller is by this only The whole FPGA device of interface management of one.
All can carry out when FPGA device powers on or during not power down reprogramming by programmable controller in programming I/O MODE pin value is set and then determines the programming mode of FPGA device.
When FPGA device powers on and during not power down reprogramming, programmable controller by different loading procedures to MODE Pin information is read out.
MODE pin value in programming I/O is set and then determines FPGA device by arranging programmable controller by the method The programming mode of part;Colleague, by one or more MODE pins connect ground or the power supply of encapsulation in advance, is not connected to sheet outside line Road, and then reduce taking of user's I/O resource, it is achieved that same wafer produces into for different packaged types and then saving This, reduce customer using cost.
Embodiment 2
As in figure 2 it is shown, a kind of FPGA device that programming I/O and user I/O is optimized, including:
Programmable controller, for being set the MODE pin value in programming I/O and then determine the programming of FPGA device Pattern, programmable controller is connected with programming I/O;
The definable programmable logic cells of user, for being written and read the data of user;
On-chip memory unit, is used for storing programming data and controlling programmable logic array in real time, sheet Upper memory portion unit is connected with user I/O.
Programmable controller is connected with the on-chip memory of FPGA device by unique interface, and programmable controller is by this only The whole FPGA device of interface management of one.
All can carry out when FPGA device powers on or during not power down reprogramming by programmable controller in programming I/O MODE pin value is set and then determines the programming mode of FPGA device.
When FPGA device powers on and during not power down reprogramming, programmable controller by different loading procedures to MODE Pin information is read out.
The corresponding same or analogous parts of same or analogous label;
Described in accompanying drawing, position relationship is used for the explanation of being merely cited for property, it is impossible to be interpreted as the restriction to this patent;
Obviously, the above embodiment of the present invention is only for clearly demonstrating example of the present invention, and is not right The restriction of embodiments of the present invention.For those of ordinary skill in the field, the most also may be used To make other changes in different forms.Here without also cannot all of embodiment be given exhaustive.All at this Any amendment, equivalent and the improvement etc. made within the spirit of invention and principle, should be included in the claims in the present invention Protection domain within.

Claims (8)

1. the programming I/O of a FPGA and the optimization method of user I/O, it is characterised in that comprise the following steps:
S1: programmable controller is set the MODE pin value in programming I/O is set and then determines the programming mould of FPGA device Formula;
S2: by one or more MODE pins connect ground or the power supply of encapsulation in advance, is not connected to off-chip circuit, and then reduces Taking of user's I/O resource.
The programming I/O of FPGA the most according to claim 1 and the optimization method of user I/O, it is characterised in that described programming Controller is connected with the on-chip memory of FPGA device by unique interface, and programmable controller is by this unique interface management Whole FPGA device.
The programming I/O of FPGA the most according to claim 2 and the optimization method of user I/O, it is characterised in that at FPGA device All can carry out when part powers on or during not power down reprogramming by programmable controller, the MODE pin value in programming I/O being set Determine and then determine the programming mode of FPGA device.
The programming I/O of FPGA the most according to claim 3 and the optimization method of user I/O, it is characterised in that at FPGA device When part powers on and during not power down reprogramming, MODE pin information is read by programmable controller by different loading procedures Take.
5. the FPGA device applying optimization method as claimed in claim 4, it is characterised in that including:
Programmable controller, for the MODE pin value in programming I/O is set and then determines the programming mode of FPGA device, Programmable controller is connected with programming I/O;
The definable programmable logic cells of user, for being written and read the data of user;
On-chip memory unit, is used for storing programming data and controlling programmable logic array in real time, sheet is deposited Reservoir portion unit is connected with user I/O.
The FPGA device being optimized programming I/O and user I/O the most according to claim 5, gas is characterised by, described Programmable controller is connected with the on-chip memory of FPGA device by unique interface, and programmable controller is by this unique interface Manage whole FPGA device.
The FPGA device that programming I/O and user I/O is optimized the most according to claim 6, gas is characterised by, All can carry out when FPGA device powers on or during not power down reprogramming by programmable controller the MODE pin value in programming I/O It is set and then determines the programming mode of FPGA device.
The FPGA device that programming I/O and user I/O is optimized the most according to claim 6, gas is characterised by, When FPGA device powers on and during not power down reprogramming, MODE pin information is entered by programmable controller by different loading procedures Row reads.
CN201610569902.6A 2016-07-18 2016-07-18 The programming I/O of FPGA and the optimization method of user I/O and device Pending CN106227695A (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101582688A (en) * 2008-05-15 2009-11-18 中兴通讯股份有限公司 Dynamic configuration circuit with FPGA loading mode
CN101859289A (en) * 2010-06-11 2010-10-13 华中科技大学 Off-chip memory access controller
CN202018808U (en) * 2010-07-30 2011-10-26 康佳集团股份有限公司 Circuit arranged at LED signal interface
CN104716954A (en) * 2015-03-17 2015-06-17 广东高云半导体科技股份有限公司 Programmable logic device provided with on-chip user nonvolatile memory
CN105573960A (en) * 2015-12-10 2016-05-11 中国航空工业集团公司西安航空计算技术研究所 Low-power consumption and high-performance processing module and construction method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101582688A (en) * 2008-05-15 2009-11-18 中兴通讯股份有限公司 Dynamic configuration circuit with FPGA loading mode
CN101859289A (en) * 2010-06-11 2010-10-13 华中科技大学 Off-chip memory access controller
CN202018808U (en) * 2010-07-30 2011-10-26 康佳集团股份有限公司 Circuit arranged at LED signal interface
CN104716954A (en) * 2015-03-17 2015-06-17 广东高云半导体科技股份有限公司 Programmable logic device provided with on-chip user nonvolatile memory
CN105573960A (en) * 2015-12-10 2016-05-11 中国航空工业集团公司西安航空计算技术研究所 Low-power consumption and high-performance processing module and construction method thereof

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Application publication date: 20161214