CN106209024A - Alpha ray basic pulse generator and launching technique - Google Patents
Alpha ray basic pulse generator and launching technique Download PDFInfo
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- CN106209024A CN106209024A CN201610525392.2A CN201610525392A CN106209024A CN 106209024 A CN106209024 A CN 106209024A CN 201610525392 A CN201610525392 A CN 201610525392A CN 106209024 A CN106209024 A CN 106209024A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
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Abstract
The invention discloses one and can produce three kinds of different types of signals, to meet alpha ray basic pulse generator and the launching technique of different alpha ray pulse signal input demands.This alpha ray calibration pulse generating means includes power supply, FPGA expansion module, D/A module；Described D/A module includes DAC900E module and two pieces of AD9708 modules.Described alpha ray calibration pulse launching technique includes step 1) first demand waveform is analyzed, it is 30MHz by the frequency division of the frequency of clock signal；2) in MifMaker, draw waveform and obtain the mif file of correspondence, mif file is saved in Quartus II；3) mif file is solidified in the ROM module expanding module into FPGA；4) FPGA expands module and sends the signal producing waveform according to the mif file in ROM module；Then receive waveshape signal by D/A module, and launch alpha ray calibration pulse.Using this device and method to control simple, processing speed is fast, and capacity of resisting disturbance is strong and signal integrity good.
Description
Technical field
The present invention relates to simulation produce alpha ray pulse signal field, especially one can produce three kinds different types of
Signal, to meet alpha ray basic pulse generator and the launching technique of different alpha ray pulse signal input demands.
Background technology
Known: alpha ray, is high speed alpha-particle stream produced by radioactive substance, it can by multiple alpha activity nucleic (as
Radium) emit.The energy of alpha-particle is up to 4～9MeV.The direction deflected electric field and magnetic field from alpha-particle, it is known that it with
Positive charge.Owing to the quality of alpha-particle is more much bigger than electronics, by easily making atomic ionization therein during material and off-energy,
So the ability of its energy penetrating material is than β ray much weaker, is easily stopped by coating substances, but it has the strongest ionization to make
With.The operation principle of α-ray detector is interaction based on alpha-particle Yu detector material.When alpha ray is by detection implements
During matter, detector material just absorbs its all or part of energy and produces ionization or excitation, and then produces the signal of telecommunication, passes through
Analysis to the signal of telecommunication just can differentiate Alpha-ray information.Owing to alpha ray is hazardous to the human body, therefore can be by a kind of equipment to α
The signal that ray produces is simulated.
Along with greatly developing of electronic computer technology especially embedded technology, FPGA (Field-Programmable
Gate Array, field programmable gate array) technology obtained developing widely and application.FPGA is because of its parallel processing capability
By force, control the features such as logic is simple and progressively become the core processor of very advantageous.
(1) high conversion speed: the data processing speed of Modern Digital System is more and more faster, it is desirable to obtain the speed of data also
Improve constantly.
(2) in high precision: the resolution of Modern Digital System is improving constantly, the I measured value of senior instrument is constantly
Reduce.
(3) low-power consumption: SOC(system on a chip) (SOC) has become as the trend of integrated circuit development, existing on same chip
Analog circuit has again digital circuit.In order to complete the systemic-function of complexity, in big system, the power consumption of each submodule should be as far as possible
Ground is low.
Summary of the invention
The technical problem to be solved is to provide one can produce three kinds of different types of signals, to meet not
The alpha ray basic pulse generator of same alpha ray pulse signal input demand.
The technical solution adopted for the present invention to solve the technical problems is: alpha ray calibration pulse generating means, including electricity
Source, FPGA expansion module, D/A module；Described FPGA has FPGA main controller, Buffer module and ROM module；
Described power supply is for providing electric energy for FPGA expansion module, D/A module；
The ROM module that described FPGA expansion module has for storing required waveform parameter,
Described FPGA main controller is for reading the waveform parameter in ROM module, and waveform parameter is converted into waveform number
According to；
Described Buffer module carries out caching division arithmetic for the Wave data sending FPGA expansion module；
Described D/A module includes DAC900E module and at least two pieces of AD9708 modules；
Described DAC900E module is used for receiving the Wave data that FPGA expansion module sends, and according to the waveform received
Data launch corresponding alpha ray calibration pulse；
Described AD9708 module is for receiving the Wave data after Buffer module carries out division arithmetic；And launch correspondence
Alpha ray calibration pulse.
Concrete, described FPGA expansion module includes FPGA controller, and described FPGA controller is provided with control module
And expansion module；
Described control module and expansion module are connected with FPGA controller respectively；
Described control module is for inputting data to FPGA controller；Described expansion module is used for showing at FPGA controller
Reason data or output data.
Concrete, described control module includes that mouse and keyboard, described mouse and keyboard are all connected with FPGA controller；Institute
Stating expansion module and use display, described display is connected with FPGA controller.
Present invention also offers a kind of alpha ray calibration pulse launch party using above-mentioned alpha ray calibration pulse generating means
Method, comprises the following steps:
1) being first analyzed demand waveform, the clock signal expanded by FPGA in module divides, make frequency dividing with
After the frequency of clock signal be 30MHz；
2) in Waveform generator software MifMaker, demand waveform is drawn；Correspondence is obtained by MifMaker
Mif file, is saved in mif file in Quartus II；
3) produce function by the ROM in Quartus II software, mif file is solidified the ROM expanding module into FPGA
In module；
4) the address module for reading and writing DDS and counting module count of required ROM module are set in FPGA expansion module；Will
The spacing value of counting module count is set to 2249；When the clock signal in counting module count is rising edge so that
Enumerator count module starts counting up, and carries out " adding 1 " calculating；The variable cnt of counting module count when counting up to 2249,
Wave data in ROM module is read out by FPGA main controller by DDS module；And in counting module count time
Clock signal divides, and obtains the clock frequency of 30MHz, expands module pin by FPGA and is connected respectively to DAC900E module
Clock pins and AD9708 module in clock pins；When enabling signal ena in count module and being low level, location is read
Address value in writing module DDS adds 1, the Wave data in the ROM module of FPGA main controller output simultaneously；When in count module
When enable signal ena is high level, the address value in the module for reading and writing DDS of location resets；
Accept waveshape signal by DAC900E module and launch alpha ray calibration pulse；
Produced the ROM of random number by MifMaker, then by Quartus II, random number is solidified into FPGA expansion
In the ROM module of module；When rising edge clock signal is effective, by the ripple in the ROM module that Buffer module will receive
Graphic data carries out division arithmetic with random number in ROM module；The waveform number after carrying out division arithmetic is received by AD9708 module
According to, launch the alpha ray pulse after amplitude regulation.
Further, in step 4) in the spacing value of counting module count on FPGA expansion module is set to a number
According to variable Time, and encapsulation interval random number in the ROM module of FPGA expansion module, when in counting module count
When clock signal is rising edge so that counting module count starts counting up, carry out " adding interval random number " calculating；Counting module
Count Wave data when being added to 1036, in FPGA main controller output ROM module；Continue cumulative, as digital-to-analogue block count
Count value cnt identical with the numerical value in variable Time time, counting module count reset, produce enable signal ena；At clock
When signal rising edge is effective, by the Wave data in the ROM module that Buffer module will receive and random number in ROM module
Carry out division arithmetic；Receive the Wave data after carrying out division arithmetic by AD9708 module, launch corresponding interval time and width
The alpha ray pulse of value.
The invention has the beneficial effects as follows: alpha ray calibration pulse generating means of the present invention uses FPGA to expand module
With the module that D/A module is combined into alpha ray output signal；Whole module has that control is simple, it is few to take resource, processing speed fast,
The feature that capacity of resisting disturbance is strong, function is complete and signal integrity is good.Alpha ray calibration pulse launching technique of the present invention
Realize producing three kinds of different types of signals by using above-mentioned alpha ray calibration pulse generating means, to meet not
Same alpha ray pulse signal input demand.
Accompanying drawing explanation
Fig. 1 is alpha ray calibration pulse generating means structured flowchart in the embodiment of the present invention；
Fig. 2 is the oscillogram drawn in MifMaker in the embodiment of the present invention；
Fig. 3 is DAC900E module principle figure in the embodiment of the present invention；
Fig. 4 is AD9708 module principle figure in the embodiment of the present invention；
Fig. 5 is that in the embodiment of the present invention, signal amplifies, and filters adjusting module schematic diagram.
Detailed description of the invention
The present invention is further described with embodiment below in conjunction with the accompanying drawings.
Alpha ray calibration pulse generating means the most of the present invention, including power supply, FPGA expanded mode
Block, D/A module；Described FPGA has FPGA main controller, Buffer module and ROM module；
Described power supply is for providing electric energy for FPGA expansion module, D/A module；
The ROM module that described FPGA expansion module has for storing required waveform parameter,
Described FPGA main controller is for reading the waveform parameter in ROM module, and waveform parameter is converted into waveform number
According to；
Described Buffer module carries out caching division arithmetic for the Wave data sending FPGA expansion module；
Described D/A module includes DAC900E module and at least two pieces of AD9708 modules；
Described DAC900E module is used for receiving the Wave data that FPGA expansion module sends, and according to the waveform received
Data launch corresponding alpha ray calibration pulse；
Described AD9708 module is for receiving the Wave data after Buffer module carries out division arithmetic；And launch correspondence
Alpha ray calibration pulse.
Concrete, power supply uses 5V power supply, the I/O pin of FPGA expansion module is expanded to bottom edge simultaneously, convenient
It is connected with various expansion module plates, builds the system of difference in functionality.
Described D/A module is mainly made up of the DAC900E high speed D/A switch chip of a piece of 10Bit, 165MSPS, permissible
Meeting the requirement that user produces for high speed signal, user can utilize DDS technology to produce in real time by fpga core module board
Point frequency, linear frequency modulation, the various forms of digital signal such as ASK, FSK, and obtain required mould by controlling high-speed d/a conversion
Intend signal.
Described FPGA expansion module includes FPGA controller, and described FPGA controller is provided with control module and expansion
Module；Described control module and expansion module are connected with FPGA controller respectively；Needed for described FPGA controller is used for receiving
Waveform parameter, and waveform parameter is converted into Wave data occurs to D/A module；Described control module is for FPGA control
Device input data；Described expansion module is used for showing that FPGA controller processes data or output data.
Described control module includes that mouse and keyboard, described mouse and keyboard are all connected with FPGA controller；Described expansion
Module uses display, and described display is connected with FPGA controller.
In sum, alpha ray calibration pulse generating means of the present invention uses FPGA to expand module and D/A module group
The module of synthesis alpha ray output signal；Whole module has that control is simple, it is few to take resource, processing speed fast, capacity of resisting disturbance
By force, the feature that function is complete and signal integrity is good.
Present invention also offers a kind of alpha ray calibration pulse launch party using above-mentioned alpha ray calibration pulse generating means
Method, comprises the following steps:
1) being first analyzed demand waveform, the clock signal expanded by FPGA in module divides, make frequency dividing with
After the frequency of clock signal be 30MHz；
2) in Waveform generator software MifMaker, demand waveform is drawn；Correspondence is obtained by MifMaker
Mif file, is saved in mif file in Quartus II；
3) produce function by the ROM in Quartus II software, mif file is solidified the ROM expanding module into FPGA
In module；
4) the address module for reading and writing DDS and counting module count of required ROM module are set in FPGA expansion module；Will
The spacing value of counting module count is set to 2249；When the clock signal in counting module count is rising edge so that
Enumerator count module starts counting up, and carries out " adding 1 " calculating；The variable cnt of counting module count when counting up to 2249,
Wave data in ROM module is read out by FPGA main controller by DDS module；And in counting module count time
Clock signal divides, and obtains the clock frequency of 30MHz, expands module pin by FPGA and is connected respectively to DAC900E module
Clock pins and AD9708 module in clock pins；When enabling signal ena in count module and being low level, location is read
Address value in writing module DDS adds 1, the Wave data in the ROM module of FPGA main controller output simultaneously；When in count module
When enable signal ena is high level, the address value in the module for reading and writing DDS of location resets；
Accept waveshape signal by DAC900E module and launch alpha ray calibration pulse；
Produced the ROM of random number by MifMaker, then by Quartus II, random number is solidified into FPGA expansion
In the ROM module of module；When rising edge clock signal is effective, by the ripple in the ROM module that Buffer module will receive
Graphic data carries out division arithmetic with random number in ROM module；The waveform number after carrying out division arithmetic is received by AD9708 module
According to, launch the alpha ray pulse after amplitude regulation.
In step 4) in by DAC900E module accept waveshape signal launch alpha ray calibration pulse；By by Wave data
Carry out division arithmetic with random number thus regulate the amplitude of alpha ray impulse waveform, received by AD9708 module and carry out division fortune
Wave data after calculation, launches the alpha ray pulse after amplitude regulation；Thus realize carrying out the alpha ray pulse of multiple waveforms sending out
Penetrate.
Further so that waveform produced by pulse generator, it is possible not only to fixing pattern interval time,
The random alpha ray pulse of each WFS time can also be launched.In step 4) in by counting module on FPGA expansion module
The spacing value of count is set to a data variable Time, and encapsulation interval is random in the ROM module of FPGA expansion module
Number, when the clock signal in counting module count is rising edge so that counting module count starts counting up, carries out " adding
Interval random number " calculate；Counting module count waveform number when being added to 1036, in FPGA main controller output ROM module
According to；Continuing cumulative, when count value cnt of digital-to-analogue block count is identical with the numerical value in variable Time, counting module count is clear
Zero, produce and enable signal ena；Produced the ROM of random number by MifMaker, then by Quartus II, random number is solidified
Enter in the ROM module that FPGA expands module；When rising edge clock signal is effective, the ROM that will be received by Buffer module
Wave data in module carries out division arithmetic with random number in ROM module；Received by AD9708 module and carry out division arithmetic
After Wave data, launch corresponding interval time and the alpha ray pulse of amplitude.By above-mentioned steps thus realize to alpha ray arteries and veins
Rush the interval time of waveform and the regulation of amplitude, it is hereby achieved that the alpha ray pulse of time arbitrary interval and amplitude.
Embodiment
As it is shown in figure 1, alpha ray calibration pulse generating means, including power supply, FPGA expansion module, D/A module；Described DA mould
Block includes DAC900E module and two pieces of AD9708 modules；Described FPGA expansion module has FPGA main controller, Buffer module
And ROM module.
Concrete, power supply uses 5V power supply, the I/O pin of FPGA expansion module is expanded to bottom edge simultaneously, convenient
It is connected with various expansion module plates, builds the system of difference in functionality.
Described D/A module is mainly made up of the DAC900E high speed D/A switch chip of a piece of 10Bit, 165MSPS, permissible
Meeting the requirement that user produces for high speed signal, user can utilize DDS technology to produce in real time by fpga core module board
Point frequency, linear frequency modulation, the various forms of digital signal such as ASK, FSK, and obtain required mould by controlling high-speed d/a conversion
Intend signal.
Described FPGA expansion module includes FPGA controller, and described FPGA controller is provided with control module and expansion
Module；Described control module and expansion module are connected with FPGA controller respectively；Needed for described FPGA controller is used for receiving
Waveform parameter, and waveform parameter is converted into Wave data occurs to D/A module；Described control module is for FPGA control
Device input data；Described expansion module is used for showing that FPGA controller processes data or output data.
Described control module includes that mouse and keyboard, described mouse and keyboard are all connected with FPGA controller；Described expansion
Module uses display, and described display is connected with FPGA controller.
The operation principle of above-mentioned alpha ray calibration pulse generating means is:
Described FPGA expands module and uses 5V DC source to power, and crystal oscillator clock is 40MHz.Above-mentioned alpha ray calibration pulse
Generating means is launched the method for alpha ray calibration pulse and is comprised the following steps:
1, being first analyzed demand waveform, the clock signal expanded by FPGA in module divides, make frequency dividing with
After the frequency of clock signal be 30MHz.The input pin of clock signal is PIN153.In follow-up design, in order to ensure
Modules can work normally, and clock frequency all uses the clock clk by frequency division module DivClk1.
2, according to the feature of alpha ray pulse signal, first draw in waveform produces software.MifMaker is a
Waveform generator software about Quartus II software.Being configured waveform parameter in this software, data length is just used
1024, a width of the 8 of data, the form of data is 16 systems, and sample frequency is 1000；According to design requirement, due to waveform peak
Between 20mV～100mV, when drawing waveform, the amplitude peak of waveform is 0x80.Final drafting waveform such as accompanying drawing 2 institute
Showing, the rise time of waveform is 3 μ s, and fall time is 25 μ s, and the cycle is 35 μ s.Under random model, during the interval of adjacent waveform
Between be not quite similar, under fixed model, the interval time of adjacent waveform is 40 μ s, and the amplitude of waveform is 50mV.
3, corresponding alpha ray calibration pulse is produced by D/A module；
3.1 launch alpha ray calibration pulse by DAC900E
The address module for reading and writing DDS and counting module count that required ROM module is set in module is expanded at FPGA；Will meter
The spacing value of digital-to-analogue block count is set to 2249.In counting module count module, when clock signal is rising edge, counting
Device starts action, carries out " adding 1 " calculating.Owing to the time cycle of required waveform requires to be 35 μ s, by can be calculated, enumerator
Variable cnt when counting up to 1024 points, the basic cycle of the model of generation is about 35 μ s, the interval of adjacent two waveforms
Time requirement is 40 μ s, and the variable cnt of enumerator is when counting up to 2249, and the interval time of adjacent two waveforms is 40 μ s.Ground
In the read module DDS of location, by assign statement so that the clock frequency of the 30MHz that frequency dividing produces, expand module by FPGA
The chip clock pin that is connected in DAC900E module of PIN139 pin.Meanwhile, in DDS module, Wave data is existed
Address in ROM is read out, and when enabling signal ena in count module and being low level, address value adds 1, simultaneously output waveform
Data.Accept waveshape signal by DAC900E module and launch alpha ray calibration pulse.As the enable signal ena in count module
During for high level, address value resets.The value of the ROM that the FPGA of random period expands module substantially remain in 1024～4096 it
Between, so when design, it is ensured that the required cycle can completely export, incomplete waveform will not be produced, and then generation is appointed
Meaning interval time and the random waveform of amplitude.
3.2 by penetrating alpha ray pulse after AD9708 module transmitted waveform amplitude adjusted；
Mif file produced by MifMaker software is saved in Quartus II under corresponding project file folder, logical
Cross the ROM in Quartus II software and produce function, the mif file of generation is solidified in the ROM module expanding module into FPGA.
Between waveform and frequency-dividing clock module, write address module for reading and writing DDS and the counting module of the ROM of required FPGA expansion module
count.In counting module count module, when clock signal is rising edge, enumerator starts action, carries out " adding 1 " meter
Calculate.Owing to the time cycle of required waveform requires to be 35 μ s, by can be calculated, the variable cnt of enumerator is counting up to 1024
When individual, the basic cycle of the model of generation is about 35 μ s, and it is 40 μ s that the interval time of adjacent two waveforms requires, enumerator
Variable cnt when counting up to 2249, the interval time of adjacent two waveforms is 40 μ s.In the read module DDS of address, pass through
Assign statement so that the clock frequency of the 30MHz that frequency dividing produces, the PIN139 pin being expanded module by FPGA is connected to
Chip clock pin in DAC900E module.Meanwhile, in DDS module, Wave data address in ROM is read out,
When enabling signal ena in count module and being low level, address value adds 1, simultaneously output waveform data.When in count module
When enable signal ena is high level, address value resets.The value of the ROM that the FPGA of random period expands module substantially remains in
Between 1024～4096, so when design, it is ensured that the required cycle can completely export, and will not produce incomplete ripple
Shape, and then produce time arbitrary interval and the random waveform of amplitude.
As shown in Figure 4, requirement according to demand, different wave requires that its shape is identical, but its produce waveform amplitude with
Machine changes, and therefore expands in the ROM module of module at FPGA, by added behind at FPGA expansion module data output interface
Buffer module, in buffer module, uses and output data is carried out division arithmetic, and corresponding divisor is encapsulated in FPGA
Expand in the ROM module aaa of module.Produced the ROM of random number by MifMaker, then generating in Quartus II should
ROM module, named aaa.Address read module DDS3.The design of buffer module, when rising edge clock signal is effective, defeated
Entering numerical nomenclature is q, and the named data of random divisor data, after two groups of data carry out division arithmetic, is connect by AD9708 module
Take in the Wave data after row division arithmetic, launch the alpha ray pulse after amplitude regulation.
3.3 by AD9708 module transmitted waveform amplitude and penetrate alpha ray pulse after all regulating interval time；
The address module for reading and writing DDS and counting module count that required ROM module is set in module is expanded at FPGA；Will meter
The spacing value of digital-to-analogue block count is set to a data variable Time, by random number packaged in ROM, when in count module
When clock signal in block count is rising edge so that counting module count starts counting up, carry out " adding interval random number " meter
Calculate；The value making each enumerator cumulative by the Time variable in count1 module random number is unfixed.By meter
Digital-to-analogue block count, when being added to 1036, the Wave data in FPGA main controller output ROM module；Continue cumulative, work as digital-to-analogue
When count value cnt of block count is identical with the numerical value in variable Time, counting module count resets, and produces and enables signal ena；
Enable the normal output waveform of follow-up ROM.The value of the ROM of random period substantially remains between 1024～4096, so
When design, it is ensured that the required cycle can completely export, and will not produce incomplete waveform.
Produced the ROM of random number by MifMaker, then by Quartus II, random number is solidified into FPGA expansion
In the ROM module of module；When rising edge clock signal is effective, by the ripple in the ROM module that Buffer module will receive
Graphic data carries out division arithmetic with random number in ROM module；The waveform number after carrying out division arithmetic is received by AD9708 module
According to, launch corresponding interval time and the alpha ray pulse of amplitude.By above-mentioned steps thus between realizing alpha ray impulse waveform
Interval and the regulation of amplitude, it is hereby achieved that the alpha ray pulse of time arbitrary interval and amplitude.
Claims (5)
1. alpha ray calibration pulse generating means, it is characterised in that: include power supply, FPGA expansion module, D/A module；Described FPGA
Expansion module has FPGA main controller, Buffer module and ROM module；
Described power supply is for providing electric energy for FPGA expansion module, D/A module；
The ROM module that described FPGA expansion module has for storing required waveform parameter,
Described FPGA main controller is for reading the waveform parameter in ROM module, and waveform parameter is converted into Wave data；
Described Buffer module carries out caching division arithmetic for the Wave data sending FPGA expansion module；
Described D/A module includes DAC900E module and at least two pieces of AD9708 modules；
Described DAC900E module is used for receiving the Wave data that FPGA expansion module sends, and according to the Wave data received
Launch corresponding alpha ray calibration pulse；
Described AD9708 module is for receiving the Wave data after Buffer module carries out division arithmetic；And launch the α of correspondence
Ray calibration pulse.
2. alpha ray calibration pulse generating means as claimed in claim 1, it is characterised in that: described FPGA expansion module includes
FPGA controller；Connect in described FPGA controller and have control module and expand module；
Described control module is for inputting data to FPGA controller；Described expansion module is used for showing that FPGA controller processes number
According to or output data.
3. alpha ray calibration pulse generating means as claimed in claim 1, it is characterised in that: described control module includes mouse
And keyboard, described mouse and keyboard are all connected with FPGA controller；Described expansion module use display, described display with
FPGA controller connects.
4. the alpha ray of employing alpha ray calibration pulse generating means as described in any one claim in claims 1 to 3
Calibration pulse launching technique, it is characterised in that comprise the following steps:
1) being first analyzed demand waveform, the clock signal expanded by FPGA in module divides, and makes frequency dividing later
The frequency of clock signal is 30MHz；
2) in Waveform generator software MifMaker, demand waveform is drawn；The mif of correspondence is obtained by MifMaker
File, is saved in mif file in Quartus II；
3) produce function by the ROM of Quartus II, mif file is solidified in the ROM module expanding module into FPGA；
4) the address module for reading and writing DDS and counting module count of required ROM module are set in FPGA expansion module；Will counting
The spacing value of module count is set to 2249；When the clock signal in counting module count is rising edge so that counting
Device count module starts counting up, and carries out " adding 1 " calculating；The variable cnt of counting module count when counting up to 2249, FPGA master
Wave data in ROM module is read out by control device by DDS module；And to the clock signal in counting module count
Divide, obtain the clock frequency of 30MHz, expand module pin by FPGA and be connected respectively to the clock of DAC900E module
Clock pins in pin and AD9708 module；When count module enabling signal ena and being low level, location module for reading and writing
Address value in DDS adds 1, the Wave data in the ROM module of FPGA main controller output simultaneously；When the enable in count module is believed
When number ena is high level, the address value in the module for reading and writing DDS of location resets；
Accept waveshape signal by DAC900E module and launch alpha ray calibration pulse；
Produced the ROM of random number by MifMaker, then by Quartus II, random number is solidified into FPGA expansion module
ROM module in；When rising edge clock signal is effective, by the waveform number in the ROM module that Buffer module will receive
Division arithmetic is carried out according to random number in ROM module；Receive the Wave data after carrying out division arithmetic by AD9708 module, send out
Penetrate the alpha ray pulse after amplitude regulation.
5. alpha ray calibration pulse discharger as claimed in claim 4, it is characterised in that: in step 4) in FPGA is extended
In module, the spacing value of counting module count is set to a data variable Time, and at the ROM module of FPGA expansion module
Middle encapsulation interval random number, when the clock signal in counting module count is rising edge so that counting module count opens
Begin counting, carries out " adding interval random number " calculating；Counting module count is when being added to 1036, and FPGA main controller exports ROM mould
Wave data in block；Continue cumulative, when count value cnt of digital-to-analogue block count is identical with the numerical value in variable Time, counting
Module count resets, and produces and enables signal ena；When rising edge clock signal is effective, will be received by Buffer module
Wave data in ROM module carries out division arithmetic with random number in ROM module；Received by AD9708 module and carry out division fortune
Wave data after calculation, launches corresponding interval time and the alpha ray pulse of amplitude.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113960676A (en) * | 2021-10-22 | 2022-01-21 | 中国地质科学院地球物理地球化学勘查研究所 | Time domain aviation electromagnetic multi-wave pulse transmitting device based on FPGA |
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| CN105116183A (en) * | 2015-08-24 | 2015-12-02 | 中国科学院微电子研究所 | Multichannel waveform signal generator |
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| CN1831541A (en) * | 2006-04-14 | 2006-09-13 | 北京航空航天大学 | Multichannel synchronous sinusoidal signal generator |
| CN200941168Y (en) * | 2006-08-25 | 2007-08-29 | 王悦 | DDS siguals generator |
| CN102109874A (en) * | 2009-12-28 | 2011-06-29 | 北京普源精电科技有限公司 | Multi-path signal generator |
| CN105116183A (en) * | 2015-08-24 | 2015-12-02 | 中国科学院微电子研究所 | Multichannel waveform signal generator |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113960676A (en) * | 2021-10-22 | 2022-01-21 | 中国地质科学院地球物理地球化学勘查研究所 | Time domain aviation electromagnetic multi-wave pulse transmitting device based on FPGA |
| CN113960676B (en) * | 2021-10-22 | 2023-06-16 | 中国地质科学院地球物理地球化学勘查研究所 | FPGA-based time domain aviation electromagnetic multi-wave pulse transmitting device |
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