CN106206449A - There is the high yield RRAM unit of the film scheme of optimization - Google Patents
There is the high yield RRAM unit of the film scheme of optimization Download PDFInfo
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- CN106206449A CN106206449A CN201510310463.2A CN201510310463A CN106206449A CN 106206449 A CN106206449 A CN 106206449A CN 201510310463 A CN201510310463 A CN 201510310463A CN 106206449 A CN106206449 A CN 106206449A
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Abstract
The present invention relates to a kind of formation and there is the method for resistive random access memory (RRAM) unit of good yield and relevant device.In certain embodiments, by forming hearth electrode above lower metal interconnection layer, and formation has the variable-resistance dielectric data accumulation layer of the first thickness to implement the method on hearth electrode.Dielectric data accumulation layer is formed cover layer.Cover layer has the second thickness, in the range of thicker than the first thickness about 2 times to about 3 times of the second thickness.The most square one-tenth top electrode, and above top electrode, form upper metal interconnection layer.The present invention relates to the high yield RRAM unit with the film scheme of optimization.
Description
Cross-Reference to Related Applications
The application is the part of the U. S. application the 14/242nd, 983 in submission on April 2nd, 2014
Continuation application.
Technical field
The present invention relates to the high yield RRAM unit with the film scheme of optimization.
Background technology
Many modern electronic devices contain the electronic memory being configured to store data.Electronic memory can
To be volatile memory or nonvolatile memory.Volatile memory stores data when it is energized,
And nonvolatile memory can store data when its power-off.Resistive random access memory
(RRAM) become due to its simple structure and with the compatibility of CMOS logic manufacturing process
One promising candidate of non-volatile memory technologies of future generation.RRAM unit includes vertically
Resistance-type data storage layer between two electrodes, wherein, two electrodes are arranged on back-end process
(BEOL) in metal layer.
Summary of the invention
In order to solve problems of the prior art, according to an aspect of the invention, it is provided one
Plant the method forming resistive random access memory (RRAM) unit, including: in lower metal
Upperside interconnection layer forms hearth electrode；Described hearth electrode is formed there is the variable-resistance of the first thickness
Dielectric data accumulation layer；Described dielectric data accumulation layer is formed cover layer, wherein, described covering
Layer has the second thickness, the scope of thicker than described first thickness about 2 times to about 3 times of described second thickness
In；Top electrode is formed above described cover layer；And above described top electrode, form upper metal
Interconnection layer.
In the above-mentioned methods, described first thickness of described dielectric data accumulation layer is at about 40 angstroms of peace treaties
In the range of 60 angstroms.
In the above-mentioned methods, described second thickness of described cover layer is at about 75 angstroms and the model of about 150 angstroms
In enclosing.
In the above-mentioned methods, also include: implement to retain after forming described dielectric data accumulation layer and dry
Roasting, wherein, in the range of about 150 DEG C and about 250 DEG C at a temperature of implement described reservation and toast, and
And the persistent period is in the range of about 24 hours and about 100 hours.
In the above-mentioned methods, described dielectric data accumulation layer include following in one or more: oxidation
Hafnium tantalum (HfTaO), tantalum aluminum oxide (TaAlO), hafnium silicon oxide (HfSiO) and tantalum oxide silicon (TaSiO).
In the above-mentioned methods, described dielectric data accumulation layer includes hafnium oxide aluminum (HfAlO).
In the above-mentioned methods, form described dielectric data accumulation layer to include: implement to form hafnium oxide respectively
(HfO) multiple first ald (ALD) deposition cycle of layer；And implement respectively under
Multiple second ALD deposition cycles of aluminium oxide (AlO) layer are formed on hafnium oxide (HfO) layer in face.
In the above-mentioned methods, form described HfO layer, including: implement the first precursor gas pulses and hold
Continuous first burst length is with by water (H2O) introduce in process chamber；Described H is discharged from described process chamber2O；
Implement the second precursor gas pulses and persistently the second burst length with by hafnium tetrachloride (HfCl4) introduce institute
Stating in process chamber, wherein, described first burst length is more than described second burst length；And from institute
State process chamber and discharge described HfCl4。
In the above-mentioned methods, described first burst length continues at about 1000 milliseconds and about 2000 milliseconds
In the range of.
According to a further aspect in the invention, a kind of formation resistive random access memory is additionally provided
(RRAM) method of unit, including: form hearth electrode；Formed above described hearth electrode and have
The dielectric data accumulation layer of the first thickness；Implement to retain after forming described dielectric data accumulation layer to dry
Roasting；Forming cover layer in described dielectric data accumulation layer, wherein, it is thick that described cover layer has second
Degree, in the range of thicker than described first thickness about 2 times to about 3 times of described second thickness；And institute
State formation top electrode above cover layer.
In the above-mentioned methods, described dielectric data accumulation layer includes using atom layer deposition process to be formed
Hafnium oxide aluminum (HfAlO), forms described dielectric data accumulation layer and includes: implement to form oxidation respectively
Multiple first ald (ALD) deposition cycle of hafnium (HfO) layer；And implement to exist respectively
Multiple second ALD deposition weeks of aluminium oxide (AlO) layer are formed on following hafnium oxide (HfO) layer
Phase.
In the above-mentioned methods, deposit described hafnium oxide (HfO) layer, including: by water (H2O) precursor
Introduce process chamber interior and lasting first burst length to form described H2The monolayer of O；From described process chamber
Discharge described H2O precursor；By hafnium tetrachloride (HfCl4) precursor introduces in described process chamber and continue the
Two burst lengths, described second burst length than described first burst length short twice more than, wherein,
Described HfCl4Precursor and described H2The monolayer of O is reacted to form described hafnium oxide (HfO) layer；With
And discharge described HfCl from described process chamber4Precursor.
In the above-mentioned methods, described first burst length continues at about 1000 milliseconds and about 2000 milliseconds
In the range of.
In the above-mentioned methods, described first thickness of described dielectric data accumulation layer is at about 40 angstroms of peace treaties
In the range of 60 angstroms.
In the above-mentioned methods, described second thickness of described cover layer is at about 75 angstroms and the model of about 150 angstroms
In enclosing.
In the above-mentioned methods, also include: at lower metal interconnection layer disposed thereon bottom electrode layer；Institute
State and on bottom electrode layer, deposit described dielectric data accumulation layer；Described dielectric data accumulation layer deposits institute
State cover layer；Described cover layer deposits top electrode layer；Optionally pattern described top electrode layer
With described cover layer to form the described top electrode with the first width；And optionally pattern institute
Give an account of electricity data storage layer and described bottom electrode layer, to be formed, there is the second width more than described first width
The described hearth electrode of degree.
In the above-mentioned methods, depositing described dielectric data accumulation layer and depositing between described cover layer
Time, in the range of about 150 DEG C and about 250 DEG C at a temperature of implement described to retain baking, and hold
The continuous time is in the range of about 24 hours and about 100 hours.
According to another aspect of the invention, a kind of resistive random access memory is additionally provided
(RRAM) unit, including: hearth electrode, it is arranged on above lower metal interconnection layer；Variable resistance
Dielectric data accumulation layer, there is the first thickness and be positioned at above described hearth electrode；Cover layer, position
In described dielectric data accumulation layer, wherein, described cover layer has the second thickness, and described second is thick
Spend in the range of thicker than described first thickness about 2 times to about 3 times；Top electrode, is arranged on described covering
Above Ceng；And upper metal interconnection layer, it is arranged on described top electrode.
In above-mentioned RRAM unit, described first thickness of described dielectric data accumulation layer is about 40
Angstrom and about 60 angstroms in the range of；And wherein, described second thickness of described cover layer is at about 75 angstroms
In the range of about 150 angstroms.
In above-mentioned RRAM unit, described dielectric data accumulation layer includes hafnium oxide aluminum (HfAlO).
Accompanying drawing explanation
When reading in conjunction with the accompanying drawings, from described in detail below can best understanding each aspect of the present invention.
It should be noted that according to the standard practices in industry, all parts not drawn on scale.It practice, be
Clearly discussing, the size of all parts can at random increase or reduce.
Fig. 1 shows that use ald (ALD) technique is to form hearth electrode and in-situ deposition work
Skill forms resistive random access memory (RRAM) with the dielectric data accumulation layer formed above
The flow chart of some embodiments of the method for unit.
Fig. 2 shows and is configured to implement an ALD technique in situ to form hearth electrode and the 2nd ALD
Technique is to form the block diagram of some embodiments of the handling implement of dielectric data accumulation layer above.
Fig. 3 A shows have the hearth electrode by ALD process deposits and original position dielectric data above
The sectional view of some embodiments of the RRAM unit of accumulation layer.
Fig. 3 B shows the hearth electrode of RRAM unit and the exemplary of original position dielectric data accumulation layer
The figure of some embodiments of XPS depth profile.
Fig. 4 shows and uses ALD technique to form hearth electrode and in-situ deposition technique to be formed above
Dielectric data accumulation layer forms the flow chart of some extra embodiments of the method for RRAM unit.
Fig. 5 to Figure 12 shows that use ALD technique is to form hearth electrode and original position ALD technique with shape
One-tenth high-k dielectric material above forms some embodiments of the sectional view of the method for RRAM unit.
Figure 13 shows the sectional view of some embodiments of the RRAM unit of the yield with improvement.
Figure 14 shows the sectional view of some extra embodiments of RRAM unit.
Figure 15 shows some the extra embodiments of the method forming RRAM unit.
Figure 16 shows the atom layer deposition process for forming the data storage layer including hafnium oxide aluminum
The exemplary timing chart of some embodiments.
Figure 17 shows the known good tube core yield of the integrated chip with multiple RRAM unit
Some embodiments of figure.
Figure 18 shows the reservation yield (retention of the integrated chip with multiple RRAM unit
Yield) some embodiments of figure.
Detailed description of the invention
Disclosure below provides many different enforcements for realizing the different characteristic of provided theme
Example or example.The instantiation of assembly and layout is described below to simplify the present invention.Certainly, these
It is only example, and is not intended to limit the present invention.Such as, in the following description, on second component
Square or upper formation first component can include that first component is formed as the reality directly contacted with second component
Execute example, and can also be included between first component and second component and can form extra parts,
So that the embodiment that first component and second component can be not directly contacted with.Additionally, the present invention can
Repeat reference numerals and/or letter in various embodiments.This repeats to be for purposes of simplicity and clarity,
And itself do not indicate the relation between each embodiment discussed and/or configuration.
And, for ease of describing, this can use such as " ... under ", " in ... lower section ",
" bottom ", " ... on ", the space relative terms on " top " etc., in order to describe such as figure
A shown element or parts and another (or other) element or the relation of parts.Except figure
Shown in orientation outside, space relative terms is intended to include device different azimuth in use or operation.
Device can otherwise orient (90-degree rotation or in other orientation), and sky as used herein
Between relative descriptors can explain the most accordingly.
Resistive random access memory (RRAM) unit has hearth electrode, and hearth electrode passes through dielectric
Data storage layer separates with top electrode above.Generally, physical vapor deposition (PVD) skill is used
Art is at substrate disposed thereon hearth electrode.Then, above hearth electrode, ex situ forms dielectric data storage
Layer.It will be appreciated, however, that use PVD formed hearth electrode (such as, TiN) remove from
The oxygen that high k dielectric layer spreads towards hearth electrode.Oxygen makes the boundary between hearth electrode and dielectric data accumulation layer
Degenerating in face, makes RRAM unit have and low yield of devices can be caused (such as, due at crystal round fringes
Near leakage current increase) high leakage current.
Therefore, the present invention relates to be formed the resistive random access memory of the leakage current with reduction
(RRAM) method of unit and relevant apparatus.In certain embodiments, the method includes using shape
Ald (ALD) technique becoming at least top of hearth electrode is square on lower metal interconnection layer
Become hearth electrode.When behind the top forming hearth electrode, the top of hearth electrode is formed in situ dielectric data
Accumulation layer.Then, above dielectric data accumulation layer, form top electrode, and square on top electrode
Become upper metal interconnection layer.By using ALD technique be formed in situ the top of hearth electrode and formed above
Dielectric data accumulation layer, improve the interface performance between hearth electrode and dielectric data accumulation layer, lead
Cause leakage current reduces, and improves leakage current distribution and the yield of devices of RRAM unit.
Fig. 1 shows that use ALD technique is to form hearth electrode and original position ALD technique to be formed above
Dielectric data accumulation layer form the resistive random access memory with low current leakage
(RRAM) some embodiments of the method 100 of unit.
In a step 102, use ald (ALD) technique to form at least top of hearth electrode
Portion and above lower metal interconnection layer formed hearth electrode.ALD technique can include any kind of former
Sublayer depositing operation, includes but not limited to the ALD (PEALD) of ALD or plasma enhancing.
Use ALD technique with the top forming hearth electrode can suppress the oxygen in hearth electrode to external diffusion, thus
Improve the integrity at interface between hearth electrode and dielectric data accumulation layer above.
At step 104, along with the formation of hearth electrode, the top of hearth electrode is formed in situ and has
Variable-resistance dielectric data accumulation layer.By the dielectric data accumulation layer shown in frame 103 and hearth electrode
Be formed in situ prevent oxide interface layer (electrical property of RRAM unit can be reduced) the end electricity
Formation on the layer of pole.In certain embodiments, dielectric data accumulation layer can be formed by ALD technique.
In other embodiments, dielectric data accumulation layer can be formed by other deposition techniques.
In step 106, above dielectric data accumulation layer, top electrode is formed.
In step 108, above top electrode, upper metal interconnection layer is formed.In certain embodiments,
Upper metal interconnection layer can include the upper metal via layer being formed on top electrode.Implement at other
In example, upper metal interconnection layer can also include that the upper metal being arranged in upper metal via layer is drawn
Line layer.
Fig. 2 shows and is configured to implement ALD technique in situ to form hearth electrode and ALD technique with shape
Become some embodiments of the handling implement 200 of the above dielectric data accumulation layer for RRAM unit
Block diagram.
Handling implement 200 includes being connected to the first of the second process chamber 218 by wafer transfer chamber 212
Process chamber 202.First process chamber the 202, second process chamber 218 and wafer transfer chamber 212 are connected to one
Individual or multiple vacuum units 224 (such as, vacuum pump), vacuum unit 224 is configured at first
Lower pressure environment is produced in reason room the 202, second process chamber 218 and wafer transfer chamber 212.Real at some
Executing in example, lower pressure environment can have such as about 10-3Torr and about 10-5Pressure in the range of torr.
First process chamber 202 includes the first wafer support element being configured to keep Semiconductor substrate 206
204 (such as, wafer electrostatic chuck), wherein RRAM unit will be formed in Semiconductor substrate 206
On.First process chamber 202 also includes that ALD deposition element 208, ALD deposition element 208 are configured to
At least top by the hearth electrode of ALD process deposits RRAM unit.In certain embodiments,
ALD deposition element 208 is configurable to deposit whole hearth electrode.ALD deposition element 208 can wrap
Include and be configured to disposably introduce vapor precursor (such as, TiCl in the first process chamber 2024And NH3
Or N2/H2Precursor is to form TiN) gas access and be configured to discharge vapor precursor expulsion element.
During each growth cycle, the precursor molecule of vapor precursor is anti-with the molecule in Semiconductor substrate 206
Atomic layer should be formed.In certain embodiments, ALD deposition element 208 can include that plasma increases
Strong ALD element, the ALD element of plasma enhancing farther includes to be configured to generate raising the
The RF plasma generating element of the plasma of the sedimentation rate in one process chamber 202.
In certain embodiments, the first process chamber 202 may further include PVD deposition element 210,
PVD deposition element 210 is configured to pass physical vapor deposition (PVD) process deposits RRAM unit
The bottom of hearth electrode.In such embodiments, PVD deposition element 210 is configured to form end electricity
The bottom of pole, and ALD deposition element 208 is configured to be formed the top of hearth electrode on the bottom of hearth electrode
Portion.
Wafer transfer chamber 212 connects with the first process chamber 202 and includes that wafer transmits element 214 (example
As, wafer transfer robot).Wafer transmits element 214 and is configured to Semiconductor substrate 206 from the
One process chamber 202 moves to the second process chamber 218.Owing to wafer transfer chamber 212 keeps under vacuo,
Wafer transmits element 214 can be sent to the second process chamber 218 (i.e., in situ by Semiconductor substrate 206
Do not break lower pressure environment).
Second process chamber 218 includes the second wafer support element being configured to keep Semiconductor substrate 206
220.Second process chamber also includes that ALD deposition element 222, ALD deposition element 222 are configured to lead to
Cross ALD technique and (such as, use HfCl in the deposited on portions dielectric data accumulation layer of hearth electrode4With
H2O precursor includes HfO to be formedxDielectric data accumulation layer)
Fig. 3 A shows the RRAM unit 300 with the hearth electrode 310 formed by ALD technique
Sectional view.
RRAM unit 300 includes being arranged on bottom dielectric layer 306 and lower metal interconnection layer 302
Diffusion impervious layer 308, lower metal interconnection layer 302 by be positioned at BEOL (back-end process) metallization
Interlayer dielectric (ILD) layer 304 in stack around.In certain embodiments, lower metal interconnection
Layer 302 can include being arranged on diffusion impervious layer 308 and following Semiconductor substrate (not shown) it
Between multiple metal interconnecting layers in one.Hearth electrode 310 is arranged on diffusion impervious layer 308.Expand
Dissipate barrier layer 308 to be configured to prevent material from diffusing to hearth electrode 310 from lower metal interconnection layer 302.
Hearth electrode 310 has the end face 311 formed by ALD technique.Such as, implement at some
In example, hearth electrode 310 can be formed by continuous print ALD technique.In other embodiments, permissible
Hearth electrode 310 is formed, in two benches depositing operation, by PVD work by two benches depositing operation
Skill forms the bottom 310a of hearth electrode, and is formed the top 310b of hearth electrode by ALD technique.?
In some embodiments, the bottom 310a of hearth electrode can have bigger than the top 310b of hearth electrode
Thickness.
Dielectric data accumulation layer 312 (that is, utilizes following bottom electrode layer 310 to be formed in situ in situ
Dielectric data accumulation layer) be arranged on the end face 311 of hearth electrode 310, so that this dielectric number
Directly contact according to the end face 311 of accumulation layer 312 with the hearth electrode 310 formed by ALD technique.Former
Position dielectric data accumulation layer 312 includes the variable resistance metal-oxide being configured to storing data state
Layer.Such as, induced synthesis is crossed over dielectric number by the voltage being applied to dielectric data accumulation layer 312 in situ
According to the conductive path (such as, Lacking oxygen) of accumulation layer 312, thus reduce dielectric data storage in situ
The resistance of layer 312.Depending on applied voltage, dielectric data accumulation layer 312 will be at high electricity in situ
Experience reversible change between resistance state and low resistance state.
Because utilizing hearth electrode 310 to be formed in situ dielectric data accumulation layer 312, dielectric data is deposited in situ
Reservoir 312 abuts directly against hearth electrode 310 and dielectric data accumulation layer 312 and hearth electrode 310 in position
Between do not get involved oxide interface layer, and when utilize hearth electrode 310 ex situ to form dielectric number in situ
According to forming oxide interface layer during accumulation layer 312.Moreover, it will be appreciated that use ALD technique with
Forming hearth electrode 310 causes hearth electrode 310 ratio to use physical vapor deposition (PVD) technique to be formed
Hearth electrode 310 has lower O2Concentration.
Such as, Fig. 3 B shows exemplary X-ray photoelectron spectroscopy (XPS) depth profile 324
Some embodiments of Figure 32 2, exemplary X-ray photoelectron spectroscopy (XPS) depth profile 324
Show the oxygen content (along section line A-A ') of hearth electrode 310.Figure 32 2 further illustrates
Use the XPS depth profile 326 of the oxygen content of the hearth electrode of PVD formation.
As shown in XPS depth profile 324, the oxygen content of hearth electrode 310 is close to hearth electrode 310 He
With relatively small slope before the position at the interface 328 between dielectric data accumulation layer 312 above
Increase.XPS depth profile 324 reaches the maximum oxygen content of about 2.5% at interface 328.XPS is deep
Degree distribution 326 shows that the oxygen content of the hearth electrode using PVD to be formed is with significantly greater slope
Increase and reach at interface 328 about 10% maximum oxygen content.
Referring again to Fig. 3 A, in certain embodiments, cover layer 314 can be arranged on dielectric data and deposit
Above reservoir 312.Cover layer 314 is configured to store oxygen, and this can promote dielectric data accumulation layer 312
Interior resistance variations.In certain embodiments, cover layer 314 can include that oxygen concentration is relatively low
Metal or metal-oxide.Top electrode 316 is arranged on above cover layer 314, and upper metal is mutual
Even layer 319 is arranged on above top electrode 316.In certain embodiments, upper metal interconnection layer 319
Upper metal via layer 320 and the top comprising conductive material (such as, copper, aluminum etc.) can be included
Metal wiring layer 322.
Fig. 4 shows that use ALD technique is to form hearth electrode and original position ALD technique to be formed above
Dielectric data accumulation layer form some extra embodiments of method 400 of RRAM unit.
Although disclosed method (such as, method 100,400 and 1500) is shown and described as
A series of behavior or event, but it is to be understood that these shown behaviors or the order of event are not
Should be interpreted that limited significance.Such as, some behaviors can occur in a different order and/or with except this
Shown in literary composition and/or the behavior or other behaviors of event or the event that describe occur simultaneously.Additionally, not
All behaviors illustrated are all to implement one or more aspects of the present invention or embodiments of the invention are musted
Must.Furthermore, it is possible to perform shown herein with one or more single behaviors and/or stage
One or more behaviors.
In step 402, above lower metal interconnection layer, bottom dielectric layer is formed.Bottom dielectric layer
There is the opening exposing lower metal interconnection layer.
In step 404, in certain embodiments, can be in lower metal interconnection layer and bottom dielectric
Diffusion impervious layer is formed above Ceng.Diffusion impervious layer can deposit to expose following metal interconnecting layer
Bottom dielectric layer in opening in so that diffusion impervious layer adjoins metal layer below.
In a step 406, ALD technique the most square one-tenth bottom electrode layer is used.One
In a little embodiments, in a step 408, it is possible to use PVD deposits first on the diffusion barrier
Bottom electrode layer forms bottom electrode layer.Subsequently, in step 410, it is possible to use ALD technique is
The second bottom electrode layer directly contacted with the first bottom electrode layer is formed on one bottom electrode layer.
In step 412, along with the formation of bottom electrode layer, above bottom electrode layer, it is formed in situ dielectric
Data storage layer.Dielectric data accumulation layer has and is configured to depend on to apply to hearth electrode or top electrode
Voltage and between high resistance state and low resistance state, experience reversible change variable resistance.At some
In embodiment, dielectric data accumulation layer can include high k dielectric layer.
In step 414, implement to retain baking.Retain baking and improve the switching window of RRAM unit
Mouth (that is, improve the difference between the data mode of RRAM unit).In certain embodiments,
Implement to retain baking at a temperature of rising in the range of about 150 DEG C and about 250 DEG C, and when continuing
Between in the range of about 24 hours and about 100 hours.
In step 416, in certain embodiments, can be formed above dielectric data accumulation layer and cover
Cap rock.
In step 418, the most square one-tenth top electrode layer.
At step 420, top electrode layer and cover layer are optionally patterned according to masking layer.Top electricity
The selectivity patterning of pole layer forms the top electrode of RRAM unit.
In step 422, the opposite sides of top electrode and cover layer forms sidewall spacer.
In step 424, deposit according to masking layer and sidewall spacer optionally patterned dielectric data
Reservoir, bottom electrode layer and diffusion impervious layer.Optionally patterning bottom electrode layer forms RRAM unit
Hearth electrode.
In step 426, above top electrode, form upper metal interconnection layer.In certain embodiments,
Upper metal interconnection layer can include the upper metal via layer being formed on top electrode and be formed at top
Upper metal trace layer on metal throuth hole layer.
Fig. 5 to Figure 13 shows that use ALD technique is to form hearth electrode and original position ALD technique with shape
One-tenth dielectric data accumulation layer above forms some enforcements of the sectional view of the method for RRAM unit
Example.Although associated methods 400 describes Fig. 5 to Figure 13, but it is to be understood that at Fig. 5 to Figure 13
Disclosed in structure be not restricted to the method, on the contrary, the single structure independent of method can be represented.
Fig. 5 shows some embodiments of the sectional view 500 corresponding to step 402 to 404.
As shown in sectional view 500, it is situated between bottom the position formation on lower metal interconnection layer 302
Electric layer 306, wherein, lower metal interconnection layer 302 is arranged in interlayer dielectric (ILD) layer 304.
Bottom dielectric layer 306 includes the opening 504 exposing lower metal interconnection layer 302.Diffusion impervious layer 502
Deposition technique (such as, chemical vapor deposition, physical vapor deposition etc.) can be used to be deposited on opening
In 504 and be deposited on above bottom dielectric layer 306.
In certain embodiments, lower metal interconnection layer 302 can include the conductive gold of such as copper or aluminum
Belong to.In certain embodiments, ILD layer 304 can include oxide, low K dielectrics or ultralow k
Electrolyte.In certain embodiments, such as, bottom dielectric layer 306 can include carborundum (SiC)
Or silicon nitride (SiN).In certain embodiments, diffusion impervious layer 502 can include such as (Al),
Manganese (Mn), cobalt (Co), titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), stannum (Sn),
The conductive oxide of metal, nitride or the nitrogen oxides of magnesium (Mg) etc..
Fig. 6 A to Fig. 6 B shows some enforcements of the sectional view 600 and 604 corresponding to step 406
Example.
Fig. 6 A shows sectional view 600, wherein, uses continuous print ALD deposition technique to form end electricity
Pole layer 602.Bottom electrode layer 602 can be formed on diffusion impervious layer 502.In certain embodiments,
ALD technique can include ALD (PEALD) technique of plasma enhancing, its use RF etc. from
Daughter is to realize higher sedimentation rate compared with traditional ALD technique (that is, higher volume of production)
Film electrical property with the improvement under low temperature.In various embodiments, bottom electrode layer 602 can include gold
Belong to nitride or metal.Such as, in certain embodiments, bottom electrode layer 602 can include titanium nitride
Or tantalum nitride (TaN) (TiN).In other embodiments, bottom electrode layer 602 can include tungsten (W)
Or copper (Cu).
Fig. 6 B shows sectional view 604, wherein, uses two benches depositing operation to form bottom electrode layer 602,
Two benches depositing operation use physical vapor deposition (PVD) process deposits the first bottom electrode layer 602a and
Follow-up ALD technique is used to form the second bottom electrode layer 602b.In certain embodiments, first end
Electrode layer 602a can use PVD to be formed as having the first thickness.Second bottom electrode layer 602b
ALD technique can be used subsequently to be formed at first bottom electrode layer 602a the up to second thickness, second
Thickness is less than the first thickness.
Two benches depositing operation is used to improve the volume of production of method 400 to form bottom electrode layer 602,
Still provide the end face that the electrical property improved can be provided to RRAM simultaneously.This is because PVD work
Skill provides high deposition rate, and ALD technique provides the oxygen in suppression bottom electrode layer 602 to extending out
The end face dissipated.In certain embodiments, the first bottom electrode layer 602a can be formed as having about 50
Angstrom and about 100 angstroms in the range of the first thickness, and the second bottom electrode layer 602b can be formed as having
The second thickness in the range of about 15 angstroms and about 30 angstroms.Second thickness be enough to allow to suppress hearth electrode
Layer 602 in oxygen to external diffusion.
Fig. 7 shows some embodiments of the sectional view 700 corresponding to step 412.
As shown in sectional view 700, by bottom electrode layer 602 original position (example above bottom electrode layer 602
As, not do not take out substrate from vacuum) formed there is variable-resistance dielectric data accumulation layer 702.?
Improve by forming dielectric data accumulation layer 702 above the bottom electrode layer 602 of ALD process deposits
The electrical property (such as, reducing leakage current) of RRAM device.Such as, by ALD process deposits
The TiN bottom electrode layer that has than being deposited by PVD of titanium nitride (TiN) bottom electrode layer less
Oxygen concentration gradient.Therefore, TiN can be suppressed by the TiN bottom electrode layer of ALD process deposits
Oxygen in bottom electrode layer to external diffusion, thus between TiN bottom electrode layer and dielectric data accumulation layer
Interface provide more preferable interface integrity.Additionally, be formed in situ bottom electrode layer 602 and dielectric
Data storage layer 702 prevents the formation of oxide interface layer, and the formation of oxide interface layer is permissible
Reduce the electrical property (such as, increasing the leakage current of RRAM unit) of RRAM unit.
In certain embodiments, ALD process deposits dielectric data accumulation layer 702 can be passed through.ALD
Technique provides the good of the interface between improvement bottom electrode layer 602 and dielectric data accumulation layer 702
Stepcoverage.In certain embodiments, dielectric data accumulation layer 702 can include high-k dielectric material.
Such as, in various embodiments, dielectric data accumulation layer 702 can include hafnium oxide (HfOX)、
Zirconium oxide (ZrOX), aluminium oxide (AlOX), nickel oxide (NiOX), tantalum oxide (TaOx)
Or titanium oxide (TiOx).
Fig. 8 shows some embodiments of the sectional view 800 corresponding to step 414 to 416.
As shown in sectional view 800, cover layer 802 can be formed in dielectric data accumulation layer 702.
In certain embodiments, cover layer 802 can include such as titanium (Ti), hafnium (Hf), platinum (Pt),
And/or the metal of aluminum (Al).In other embodiments, cover layer 802 can include such as titanium oxide
(TiOx), hafnium oxide (HfOX), zirconium oxide (ZrOX), germanium oxide (GeOX), oxidation
Caesium (CeOX) metal-oxide.
Top electrode layer 804 is formed above cover layer 802.Can by vapor deposition technique (such as,
Physical vapor deposition, chemical vapor deposition etc.) deposition top electrode layer 804.In various embodiments,
Top electrode layer 804 can include metal nitride or metal.Such as, in certain embodiments, top electricity
Pole layer 804 can include titanium nitride (TiN) or tantalum nitride (TaN).In other embodiments, top
Electrode layer 804 can include tungsten (W) or copper (Cu).
Fig. 9 shows some embodiments of the sectional view 900 corresponding to step 418.
As shown in sectional view 900, form masking layer 902 in top electrode layer 804 property selected over.
Masking layer 902 is configured to limit the top electrode of RRAM unit.In certain embodiments, masking layer 902
Hard mask layer can be included.Such as, masking layer 902 can include hard mask material, such as silicon oxide
(SiO2), silicon nitride (SiN), silicon oxynitride (SiON) or carborundum (SiC).
Figure 10 shows some embodiments of the sectional view corresponding to step 418 to 420.
As shown in sectional view 1000, implement the first Patternized technique and with patterning top electrode layer 804 and cover
Cap rock 802.Top in the region that the most masked layer 902 is optionally covered by the first Patternized technique
Electrode layer 804 and cover layer 802 are exposed to etchant 1002, thus generate top electrode 316 and pattern
The cover layer 314 changed.Top electrode has the first width.Then top electrode 316 and covering of patterning
Sidewall spacer 1004 is formed in the opposite sides of cap rock 314.In certain embodiments, can pass through
By on nitride deposition to dielectric data accumulation layer 702 and be etched selectively to nitride to form side
The mode of wall distance piece 1004 forms sidewall spacer 1004.
Figure 11 shows the sectional view 1100 of some embodiments corresponding to step 422.
As shown in sectional view 1100, implement the second Patternized technique with patterned dielectric data storage layer
702, bottom electrode layer 602 and diffusion impervious layer 308.Second Patternized technique optionally will not covered
Cover the dielectric data accumulation layer 702 in the region of layer 902 or sidewall spacer 1004 covering, hearth electrode
Layer 602 and diffusion impervious layer 308 are exposed to etchant 1102, thus generate the dielectric data of patterning
Accumulation layer 312, hearth electrode 310 and the diffusion impervious layer 308 of patterning.Hearth electrode has more than top electricity
Second width of the first width of pole is (owing to bottom electrode layer 602 is by between masking layer 902 and sidewall
Spacing body 1004 patterning).
Figure 12 shows the sectional view 1200 of some embodiments corresponding to step 424.
As shown in sectional view 1200, above top electrode 316, form upper metal interconnection layer 319.?
In some embodiments, upper metal interconnection layer 319 can include upper metal via layer 320 and top
Metal wiring layer 322.In certain embodiments, can be by depositing on RRAM memory cell
Dielectric layer 318 forms upper metal interconnection layer 319.Then, etch process is implemented to form extension
Through the opening of dielectric layer 318 and hard mask layer 1202 to expose top electrode 316.Subsequently, with metal
(such as, copper, aluminum etc.) fills opening to form upper metal via layer 320 and upper metal lead-in wire
Layer 322.
Figure 13 shows the cross section of some embodiments of the RRAM unit 1300 of the yield with improvement
Figure.
RRAM unit 1300 includes the dielectric data being arranged between hearth electrode 310 and top electrode 316
Accumulation layer 312.Dielectric data accumulation layer 312 can include that high k dielectric layer (such as, has and is more than
The dielectric layer of the dielectric constant of 3.9).Cover layer 314 be arranged on hearth electrode 310 and top electrode 316 it
Between and be positioned at dielectric data accumulation layer 312 above and the position of adjacent dielectric data storage layer 312.
In certain embodiments, cover layer 314 can include metal (such as, Ti, Hf, Pt and/or Al)
Or metal-oxide (such as, TiOX、HfOX、ZrOX、GeOXAnd/or CeOX)。
It is to be understood that, although be formed in situ hearth electrode 310 and dielectric data accumulation layer 312 can be improved
RRAM unit performance, the yield including the integrated chip of RRAM unit depends on that dielectric data stores
Thickness ratio between layer 312 and cover layer 314.Therefore, in certain embodiments, by making
Cover layer 314 has the thickness t in dielectric data accumulation layer 3121About 2 again in the range of 3 times
Thickness t2, yield can be improved.Such as, in certain embodiments, dielectric data accumulation layer 312
Can have the thickness t in the range of about 40 angstroms and about 60 angstroms1, and cover layer 314 can have
Thickness t in the range of about 75 angstroms and about 150 angstroms2。
In various embodiments, dielectric data accumulation layer 312 can include hafnium oxide aluminum (HfAlO),
Hafnium oxide tantalum (HfTaO), tantalum aluminum oxide (TaAlO), hafnium silicon oxide (HfSiO) and/or oxidation
Tantalum silicon (TaSiO).Generally, during forming the dielectric data accumulation layer 312 including HfAlO,
Due to the precursor substance used in the formation of HfAlO layer, chlorine (Cl) atomic deposition is in HfAlO.
Chlorine atom produces the hole trap of the performance that can reduce RRAM unit 1300.Recognize the most further
Knowledge is arrived, and the quantity reducing the chlorine atom in dielectric data accumulation layer 312 can improve RRAM further
The yield of unit 1300.Therefore, in certain embodiments, dielectric data accumulation layer 312 can have
The chlorine impurity content of about 0.9%.
Therefore, by adjusting the thickness ratio (example between dielectric data accumulation layer 312 and cover layer 314
As, the value of C/D ratio is between about 2 to about 3) and it is used in combination the number with low chlorine impurity content
According to accumulation layer, RRAM unit 1300 provides the integrated chip (IC) of the yield with improvement.
Figure 14 shows the sectional view of some extra embodiments of RRAM unit 1400.
RRAM unit 1400 includes the insulation being arranged between RRAM stack and dielectric layer 318
Layer 1402.Insulating barrier 1402 adjoins diffusion impervious layer 308, hearth electrode, dielectric data accumulation layer and side
The sidewall of wall distance piece.Insulating barrier 1402 can adjoin the top of hard mask layer 1202 further.Absolutely
Edge layer 1402 protects RRAM stack during manufacture, thus prevents the damage to stack and change
Enter yield.In certain embodiments, such as, insulating barrier 1402 can include carborundum (SiC) or
Silicon nitride (SiN).
Figure 15 shows some the extra embodiments of the method 1500 forming RRAM unit.Method
1500 form data storage layer and cover layer in the way of improving the yield of the RRAM unit generated.
In step 1502, form bottom electrode layer.In certain embodiments, it is possible to use atomic layer deposition
Long-pending (ALD) technique forms bottom electrode layer above substrate.
In step 1504, above bottom electrode layer, form dielectric data accumulation layer.In some embodiments
In, dielectric data accumulation layer can utilize the bottom electrode layer of formation to be formed in situ.Dielectric data accumulation layer
Have and be configured to according to applying to hearth electrode or the voltage of top electrode at high resistance state and low resistance shape
Reversible change variable resistance is experienced between state.
In certain embodiments, dielectric data accumulation layer can include the high k formed by ALD technique
Dielectric layer.Such as, dielectric data accumulation layer can include the hafnium oxide aluminum using ALD technique to be formed
(HfAlO) layer, ALD technique is to form hafnium oxide (HfO) layer (step 1506) respectively many
The individual period 1 and formed respectively aluminium oxide (AlO) layer (step 1508) multiple second rounds it
Between alternately.The quantity of multiple period 1 and multiple second round will depend upon which dielectric data accumulation layer
Thickness.
In step 1510, in certain embodiments, it is possible to implement retain baking.In some embodiments
In, implement at a temperature of the rising in the range of about 150 DEG C and about 250 DEG C to retain baking, and hold
The continuous time is in the range of about 24 hours and about 100 hours.
In step 1512, above dielectric data accumulation layer, form cover layer.Can be by deposition work
Cover layer is formed as having by skill (such as, CVD, PE-CVD, PVD etc.) to be deposited at dielectric data
About the 2 of the thickness of reservoir are again to the thickness in the range of about 3 times.
In step 1514, the most square one-tenth top electrode layer.
In step 1516, optionally pattern top electrode layer and cover layer according to masking layer.Select
Property pattern top electrode layer formed RRAM unit top electrode.
In step 1518, in certain embodiments, can be in top electrode and the opposite sides of cover layer
Upper formation sidewall spacer.
In step 1520, deposit according to masking layer and sidewall spacer optionally patterned dielectric data
Reservoir and bottom electrode layer.Optionally patterning bottom electrode layer forms the hearth electrode of RRAM unit.
In step 1522, above the RRAM stack of patterning, form insulating barrier and dielectric layer.
In certain embodiments, dielectric layer can include interlayer dielectric (ILD) layer, interlayer dielectric (ILD)
Layer includes low k dielectric, ultra low k dielectric materials or pole low k dielectric.
In step 1524, above top electrode, form upper metal interconnection layer.In certain embodiments,
Upper metal interconnection layer can include the upper metal via layer being formed on top electrode and be formed at top
Upper metal trace layer on metal throuth hole layer.
Figure 16 shows for forming dielectric data accumulation layer former including hafnium oxide aluminum (HfAlO)
The exemplary timing chart 1600 of some embodiments of sublayer deposition (ALD) technique.ALD technique uses
Deposition cycle c1 alternately of the layer of difference deposit hafnium oxides (HfO) and aluminium oxide (AlO) and c2
Form HfAlO.Although illustrating the ALD cycle in a particular order, it will be appreciated that in some embodiments
In can invert this order (such as, H2O pulse can be at HfCl4Implement before pulse).
As shown in sequential chart 1600, during the first deposition cycle c1, can be at time t1Implement the
One precursor gas pulses 1602 is with by water (H2O) introduce in process chamber.First precursor gas pulses 1602
Substrate is formed H2The monolayer of O molecule.Then at time t2-t3Between from process chamber discharge H2O。
Can be at time t3Implement the second precursor gas pulses 1604 with by hafnium tetrachloride (HfCl4) at introducing
Reason indoor.HfCl4With H2The single-layer back of O molecule should be to produce the monolayer of HfO on substrate.Then,
Can be at time t4-t5Between from process chamber discharge HfCl4。
During the second deposition cycle c2, can be at time t5Implement the 3rd precursor gas pulses 1606
With by water (H2O) introduce in process chamber.3rd precursor gas pulses 1606 shape on the monolayer of HfO
Become H2The monolayer of O molecule.Then at time t6-t7Between from process chamber discharge H2O.Can be in the time
t7Implement the 4th precursor gas pulses 1608 with by trimethyl aluminium (Al2(CH3)6Or TMA) at introducing
Reason indoor.TMA and H2The single-layer back of O molecule should be to produce the monolayer of AlO on the monolayer of HfO.
It is then possible at time t8-t9Between from process chamber discharge TMA.
The first and second deposition cycle c1 and c2 can be iteratively repeated, to control the thickness of HfAlO layer.
This is because each deposition cycle c1 and/or c2 will form the atomic layer of material.Therefore, the ALD of enforcement
Deposition cycle is the most, and the thickness of HfAlO data storage layer is the biggest.
Under normal circumstances, during forming the monolayer of HfO, due to HfCl4Chlorine in precursor, chlorine (Cl)
Atomic deposition is in the monolayer of HfO.Chlorine atom produces in the monolayer of HfO can reduce RRAM
The hole trap of the performance of unit.Should be appreciated that by increasing H2O burst length pt1Can reduce
Chlora matter in HfO.Therefore, by increasing relative to HfCl4Burst length pt2H2The arteries and veins of O
Rush time pt1, form the monolayer of the HfO of the chlora matter with minimizing.Such as, the first burst length
pt1Can be than the second burst length pt2Long more than 2 times.Increase H2O burst length pt1Increase further
O (-OH) content.The OH content increased improves devices switch and performance uniformity.Real at some
Execute in example, the H during the first deposition cycle c12O burst length pt1Can have about 1000
Millisecond (ms) and about 2000ms in the range of persistent period and during the second deposition cycle c2
H2O burst length pt1' can have in the range of about 500ms and about 1500ms lasting time
Between.
Figure 17 shows the known good tube core (KGD) of the integrated chip with multiple RRAM unit
Some embodiments of Figure 170 0 of yield.Figure 170 0 shows the overburden cover along x-axis and Jie
KGD yield on the ratio (C/D ratio) of electricity data storage layer thickness and y-axis is (that is, unencapsulated
The yield of IC tube core).
As shown in Figure 170 0, in first area 1702, along with the thickness of cover layer increases, cover
Layer thickness also increases with the ratio (C/D ratio) of dielectric data accumulation layer thickness.The increasing of C/D ratio
Add and the KGD yield of RRAM unit is improved to the first value V1。
In second area 1704, the thickness of cover layer and dielectric data accumulation layer keeps constant, but
H in the ALD technique forming dielectric data accumulation layer2The O burst length increases.H2O pulse
The increase of time decreases chlorine impurity content in produced dielectric data accumulation layer and adds hydrogen and divide
Sub-content, thus the KGD yield of RRAM unit is improved to the second value V2。
In the 3rd region 1706, increase the thickness of cover layer further.The increase of the thickness of cover layer
Increase C/D ratio.But, in the 3rd region, the increase of the thickness of cover layer is corresponding to RRAM
The KGD yield of unit reaches the 3rd value V3Relatively small raising.
In the 4th region 1708, the thickness of dielectric data accumulation layer increases.Increase dielectric data storage
The thickness (simultaneously increasing the thickness of cover layer) of layer reduces C/D ratio.But, it is situated between by increase
The thickness of electricity data storage layer, KGD yield can be further increased to the 4th value V4。
Therefore, as shown in Figure 170 0, by adjusting the ratio of the thickness of cover layer and dielectric data accumulation layer
Rate (such as, between 2 and 3) is used in combination has high hydrogen molecule content and low chlorine impurity content
Dielectric data accumulation layer, the yield of the integrated chip with RRAM unit can increase about 1.2 times
(that is, 1.5 >=V between about 1.5 times4/V1≥1.2)。
Figure 18 shows Figure 180's 0 retaining yield of the integrated chip with multiple RRAM unit
Some embodiments.Figure 180 0 shows the overburden cover along x-axis and dielectric data accumulation layer thickness
Ratio (C/D ratio) and y-axis on reservation yield (that is, retain baking after IC yield).
As shown in Figure 180 0, in first area 1802, along with the thickness of cover layer increases, cover
Layer thickness also increases with the ratio (C/D ratio) of dielectric data accumulation layer thickness.The increasing of C/D ratio
Add and the yield of RRAM unit is improved to the first value V1’。
In second area 1804, the thickness of cover layer and dielectric data accumulation layer keeps constant, but
H in the ALD technique forming dielectric data accumulation layer2The O burst length increases.H2O pulse
The increase of time decreases chlorine impurity content in produced dielectric data accumulation layer and adds hydrogen and divide
Sub-content, thus the yield of RRAM unit is improved to the second value V2’。
In the 3rd region 1806, increase the thickness of cover layer further.The increase of the thickness of cover layer
Increase C/D ratio.But, in the 3rd region, the increase of the thickness of cover layer is corresponding to RRAM
The yield of unit reaches the 3rd value V3' relatively small reduction.
In the 4th region 1808, the thickness of dielectric data accumulation layer increases.Increase dielectric data storage
The thickness (simultaneously increasing the thickness of cover layer) of layer reduces C/D ratio.But, it is situated between by increase
The thickness of electricity data storage layer, yield can be further increased to the 4th value V4’。
Therefore, as shown in Figure 180 0, by adjusting the ratio of the thickness of cover layer and dielectric data accumulation layer
Rate (such as, between 2 and 3), is used in combination and has high hydrogen molecule content and low chlora matter contains
The dielectric data accumulation layer of amount, the yield of the integrated chip with RRAM unit can increase about 2.5
Times and about 3 times between (that is, 3 >=V4’/V1’≥2)。
Therefore, the present invention relates to the resistive random access memory that a kind of formation has the yield of improvement
(RRAM) method of unit and relevant device.
In certain embodiments, the present invention relates to a kind of formation resistive random access memory
(RRAM) method of unit.This is implemented by forming hearth electrode above lower metal interconnection layer
Method.Hearth electrode is formed there is the variable-resistance dielectric data accumulation layer of the first thickness, and
Cover layer is formed in dielectric data accumulation layer.Cover layer has the second thickness, and the second thickness is thicker than the first
In the range of degree thickness about 2 times to about 3 times.The most square one-tenth top electrode, and on top electrode
Square one-tenth upper metal interconnection layer.
In other embodiments, the present invention relates to a kind of formation resistive random access memory
(RRAM) method of unit.The method includes being formed hearth electrode, and forms tool above hearth electrode
There is the dielectric data accumulation layer of the first thickness.After the method is additionally included in formation dielectric data accumulation layer
Implement to retain baking.The method is additionally included in dielectric data accumulation layer formation cover layer, wherein, covers
Cap rock has the second thickness, in the range of thicker than the first thickness about 2 times to about 3 times of the second thickness.Should
Method is additionally included in formation top electrode above cover layer.
In yet other embodiment, the present invention relates to a kind of resistive random access memory
(RRAM) unit.This RRAM unit has the hearth electrode being arranged on above lower metal interconnection layer,
With the variable-resistance dielectric data accumulation layer with the first thickness being positioned at above hearth electrode.Should
RRAM unit also includes the cover layer being positioned in dielectric data accumulation layer.Cover layer has the second thickness,
In the range of thicker than the first thickness about 2 times to about 3 times of second thickness.RRAM unit also includes arranging
The top electrode of side and the upper metal interconnection layer being arranged on top electrode on the cover layer.
Foregoing has outlined the feature of some embodiments so that those skilled in the art may be better understood
The aspect of the present invention.It should be appreciated by those skilled in the art that they can readily use the present invention and make
Based on design or revise for realizing the purpose identical with in this introduced embodiment and/or realization
Other techniques of identical advantage and structure.Those skilled in the art are it should also be appreciated that the isomorphism such as this
Make without departing from the spirit and scope of the present invention, and in the feelings without departing substantially from the spirit and scope of the present invention
Under condition, at this, they can make multiple change, replace and change.
Claims (10)
1. the method forming resistive random access memory (RRAM) unit, including:
Hearth electrode is formed above lower metal interconnection layer；
Described hearth electrode is formed the variable-resistance dielectric data accumulation layer with the first thickness；
Forming cover layer in described dielectric data accumulation layer, wherein, it is thick that described cover layer has second
Degree, in the range of thicker than described first thickness about 2 times to about 3 times of described second thickness；
Top electrode is formed above described cover layer；And
Upper metal interconnection layer is formed above described top electrode.
Method the most according to claim 1, wherein, described the of described dielectric data accumulation layer
One thickness is in the range of about 40 angstroms and about 60 angstroms.
Method the most according to claim 1, wherein, described second thickness of described cover layer exists
In the range of about 75 angstroms and about 150 angstroms.
Method the most according to claim 1, also includes:
Implement to retain baking after described dielectric data accumulation layer being formed, wherein, at about 150 DEG C and
Implement described reservation at a temperature of in the range of about 250 DEG C to toast, and the persistent period was at about 24 hours
In the range of about 100 hours.
Method the most according to claim 1, wherein, described dielectric data accumulation layer includes following
In one or more:
Hafnium oxide tantalum (HfTaO), tantalum aluminum oxide (TaAlO), hafnium silicon oxide (HfSiO) and oxygen
Change tantalum silicon (TaSiO).
Method the most according to claim 1, wherein, described dielectric data accumulation layer includes oxidation
Hafnium aluminum (HfAlO).
Method the most according to claim 6, wherein, forms described dielectric data accumulation layer and includes:
Implement to be formed respectively multiple first alds (ALD) deposition of hafnium oxide (HfO) layer
Cycle；And
Implement to be formed on following hafnium oxide (HfO) layer respectively multiple the of aluminium oxide (AlO) layer
Two ALD deposition cycles.
Method the most according to claim 7, wherein, forms described HfO layer, including:
Implement the first precursor gas pulses and persistently the first burst length with by water (H2O) introducing processes
Indoor；
Described H is discharged from described process chamber2O；
Implement the second precursor gas pulses and persistently the second burst length with by hafnium tetrachloride (HfCl4) draw
Entering in described process chamber, wherein, described first burst length is more than described second burst length；And
Described HfCl is discharged from described process chamber4。
9. the method forming resistive random access memory (RRAM) unit, including:
Form hearth electrode；
The dielectric data accumulation layer with the first thickness is formed above described hearth electrode；
Implement to retain baking after forming described dielectric data accumulation layer；
Forming cover layer in described dielectric data accumulation layer, wherein, it is thick that described cover layer has second
Degree, in the range of thicker than described first thickness about 2 times to about 3 times of described second thickness；And
Top electrode is formed above described cover layer.
10. resistive random access memory (RRAM) unit, including:
Hearth electrode, is arranged on above lower metal interconnection layer；
Variable-resistance dielectric data accumulation layer, has the first thickness and is positioned at above described hearth electrode；
Cover layer, is positioned in described dielectric data accumulation layer, and wherein, it is thick that described cover layer has second
Degree, in the range of thicker than described first thickness about 2 times to about 3 times of described second thickness；
Top electrode, is arranged on above described cover layer；And
Upper metal interconnection layer, is arranged on described top electrode.
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| US14/592,340 US9876167B2 (en) | 2014-04-02 | 2015-01-08 | High yield RRAM cell with optimized film scheme |
| US14/592,340 | 2015-01-08 |
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