CN106206429B - Preparation method, array substrate and the display device of array substrate - Google Patents
Preparation method, array substrate and the display device of array substrate Download PDFInfo
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- CN106206429B CN106206429B CN201610804271.1A CN201610804271A CN106206429B CN 106206429 B CN106206429 B CN 106206429B CN 201610804271 A CN201610804271 A CN 201610804271A CN 106206429 B CN106206429 B CN 106206429B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
Abstract
The present invention provides a kind of preparation methods of array substrate, and active area materials layer is formed on substrate；Source-drain electrode material layer is formed on active area materials layer；Patterning processes are executed using gray level mask plate, so that source-drain electrode material layer is formed the figure including data line and active area materials layer is made to form the first area being located at below the figure that source-drain electrode material layer is formed and the second area on the outside of first area；Gate insulation layer is formed on the substrate for being formed with data line, first area and second area；Gate material layers are formed on gate insulation layer, so that gate material layers is formed the figure of grid using a patterning processes, and keep grid corresponding with the part as active area of second area；The area conductors positioned at grid two sides for making second area, active area to be electrically connected with data line, pixel electrode respectively；Pixel electrode is formed on the substrate for be formed with grid.It can reduce by a masking process, so that simple process and reduction production cost.
Description
Technical field
The invention belongs to field of display technology, and in particular to a kind of preparation method of array substrate, array substrate and display
Device.
Background technique
The minimum constituent unit of array substrate is pixel, it is crucial that semiconductor devices in pixel, semiconductor devices
Property determines the quality of entire display panel.Currently, large scale, high-resolution, high-frequency drive OLED are that the development shown becomes
Gesture is exactly sufficiently high on-state current and lower leakage current to array substrate and semiconductor devices requirement.For example divide
Resolution is higher, frequency is higher, and the charging time for leaving one-row pixels for is shorter, just necessary in order to complete charging in the shorter time
Improve the on-state current of semiconductor devices；And for OLED product, due to being electric current driving, more require semiconductor devices that can provide
Sufficiently high and sufficiently stable operating current.
To improve semiconductor devices on-state current, the semiconductor material of high mobility is selected, what is used on a large scale at present is non-
Crystal silicon (a-Si) semiconductor, mobility have 0.5cm2/VS.In order to improve performance, currently, developing metal oxide (oxide)
Semiconductor devices and low temperature polycrystalline silicon (LTPS) semiconductor devices, mobility have respectively reached 30cm2/ VS and 100cm2/VS.But
It is that oxide semiconductor devices stability is poor, it is easy to by the destruction of hydrogen ion or other impurities, therefore, process window is small,
It needs to design extremely complex compensation circuit to make up the problem, causes to be difficult to always universal on a large scale.Low temperature polycrystalline silicon
(LTPS) material shows the semiconductor material of equipment due to high mobility, can be used as high-performance LCD, AMOLED,
And can be integrated on the glass substrate by cmos circuit, realize narrow frame and low-power consumption.But LTPS backboard process difficulty compared with
Greatly, other than the control of amorphous silicon anneal uniformity, doping control difficulty are big, which is also improved to the strict demand of material
Threshold.
For conventional top-gated autoregistration LTPS HADS+Resin structure, each layer sequence is light shield layer → buffer layer → low
Warm polysilicon layer → gate insulating layer → gate patterns → interlayer insulating film → source-drain electrode layer → organic insulator → public electrode
ITO → passivation layer → pixel electrode ITO, wherein form light shield layer, low-temperature polycrystalline silicon layer, gate patterns, source-drain electrode layer, active
Insulating layer, public electrode ITO, passivation layer and pixel electrode ITO respectively need a Mask technique, and gate insulating layer and interlayer are exhausted
Edge layer needs a Mask technique therefore to need 9 Mask techniques in total, this makes the process for preparing array substrate excessively multiple
It is miscellaneous, cause higher cost.
Currently, needing a kind of preparation method of array substrate for reducing Mask technique number.
Summary of the invention
The present invention is directed at least solve one of the technical problems existing in the prior art, a kind of system of array substrate is proposed
Preparation Method, array substrate and display device.
One of in order to solve the above problem, the present invention provides a kind of preparation methods of array substrate, comprising the following steps:
Active area materials layer is formed on substrate；
Source-drain electrode material layer is formed on the active area materials layer；
Patterning processes are executed using gray level mask plate, forming the source-drain electrode material layer includes the figure of data line
And the active area materials layer is made to form the first area being located at below the figure that the source-drain electrode material layer is formed and be located at
Second area on the outside of the first area；
Gate insulation layer is formed on the substrate for being formed with data line, first area and second area；
Gate material layers are formed on the gate insulation layer, so that the gate material layers is formed grid using a patterning processes
The figure of pole, and keep the grid corresponding with the part as active area of the second area；
The area conductors positioned at the grid two sides for making the second area, to by the active area respectively with institute
State data line, pixel electrode electrical connection；
The pixel electrode is formed on the substrate for being formed with the grid.
Preferably, the use gray level mask plate executes a patterning processes, forms the source-drain electrode material layer and includes
The step of figure of data line, comprising:
Using gray level mask plate by a patterning processes, forming the source-drain electrode material layer includes the figure of data line
Shape, the source electrode and data line electrical connection；
The area conductors positioned at the grid two sides for making the second area, to distinguish the active area
The step of being electrically connected with the data line, pixel electrode, comprising:
Make the two side areas conductor positioned at the grid in the second area, to respectively by the active area and
The source electrode, drain electrode electrical connection；
It is described the step of forming the pixel electrode on the substrate for being formed with the grid, comprising:
It is formed on the substrate for being formed with the grid and the pixel electrode for draining and being electrically connected.
It is preferably, described that the pixel electrode is formed on the substrate for being formed with the grid, comprising the following steps:
Interlayer insulating film is formed on the substrate for being formed with the grid；
Organic insulator is formed on the interlayer insulating film；
The first via hole is formed in the organic insulator using a patterning processes；
Passivation layer is formed on the substrate for being formed with the organic insulator with the first via hole；
It crosses hole location described first using a patterning processes and is formed and run through the passivation layer, the interlayer insulating film
With the second via hole and third via hole of the gate insulating layer, second via hole corresponds to the second area and the data line
At the position of electrical connection；The third via hole corresponds at the position that the second area is electrically connected with the pixel electrode；
Pixel electrode material layer is formed on the substrate with second via hole and the third via hole；
Using a patterning processes make the pixel electrode material layer formed include pixel electrode and with the second via hole and
The figure of the corresponding connection electrode of third via hole.
Preferably, the step that passivation layer is formed on the substrate for being formed with the organic insulator with the first via hole
Suddenly, comprising:
Public electrode material layer is formed on the substrate for being formed with the organic insulator with the first via hole；
The public electrode material layer is set to form public electrode using a patterning processes；
The passivation layer is formed on the substrate for being formed with the public electrode.
It is preferably, described the step of forming active area materials layer on substrate, comprising:
It is formed with light-shielding material layers on the substrate；
The light-shielding material layers are made to form light shield layer using a patterning processes, for blocking the active area；
The active area materials layer is formed on the substrate for being formed with the light shield layer.
It is preferably, described the step of forming the active area materials layer on the substrate for being formed with the light shield layer,
Further include:
Buffer layer is formed on the substrate for being formed with the light shield layer；
The active area materials layer is formed on the substrate for being formed with the buffer layer.
Preferably, the active area materials layer is amorphous silicon material layer；
Before forming source-drain electrode material layer on the active area materials layer, further includes:
The amorphous silicon material layer is handled as polysilicon material layer.
The present invention also provides a kind of array substrates, are obtained using the preparation method preparation of above-mentioned array substrate provided by the invention
.
The present invention also provides a kind of display device, including array substrate, the array substrate is using the above-mentioned offer of the present invention
Array substrate.
The invention has the following advantages:
Preparation method, array substrate and the display device of array substrate provided by the invention, only with one-time process
Form active area, source-drain electrode and data line, this is compared with prior art, it is possible to reduce a masking process, so as to so that
It obtains simple process and reduces production cost.
Detailed description of the invention
Fig. 1 is the schematic diagram after step S1 of the preparation method of array substrate provided in an embodiment of the present invention；
Fig. 2 is the schematic diagram upon step s 2 of the preparation method of array substrate provided in an embodiment of the present invention；
Fig. 3 a~Fig. 3 e is multiple during the step S3 of the preparation method of array substrate provided in an embodiment of the present invention
Schematic diagram；
Fig. 4 is the schematic diagram after step s4 of the preparation method of array substrate provided in an embodiment of the present invention；
Fig. 5 is the schematic diagram after step s 5 of the preparation method of array substrate provided in an embodiment of the present invention；
Fig. 6 is the schematic diagram after step S6 of the preparation method of array substrate provided in an embodiment of the present invention；
Fig. 7 is the schematic diagram after step S71 of the preparation method of array substrate provided in an embodiment of the present invention；
Fig. 8 is the signal after step S72 and S73 of the preparation method of array substrate provided in an embodiment of the present invention
Figure；
Fig. 9 is the signal after step S741 and S742 of the preparation method of array substrate provided in an embodiment of the present invention
Figure；
Figure 10 is the schematic diagram after step S743 of the preparation method of array substrate provided in an embodiment of the present invention；
Figure 11 is the schematic diagram after step S75 of the preparation method of array substrate provided in an embodiment of the present invention；
Figure 12 is the signal after step S76 and S77 of the preparation method of array substrate provided in an embodiment of the present invention
Figure.
Specific embodiment
To make those skilled in the art more fully understand technical solution of the present invention, come with reference to the accompanying drawing to the present invention
Preparation method, array substrate and the display device of the array substrate of offer are described in detail.
Embodiment 1
Below with reference to the preparation method for the array substrate that Fig. 1~Figure 12 the present invention is described in detail embodiment provides, including with
Lower step:
S1 forms active area materials layer on substrate.
In the present embodiment, specifically, referring to Fig. 1, step S1 includes:
S11 is formed with light-shielding material layers on the substrate 1.
S12 makes the light-shielding material layers form light shield layer 2, for blocking the active area using a patterning processes.Into
Specifically, light shield layer can be Mo film layer, thickness to one step
S13 forms the active area materials layer 4 on the substrate 1 for being formed with the light shield layer.
Further specifically, above-mentioned steps S13 includes:
S131 forms buffer layer 3 on the substrate for be formed with the light shield layer.Buffer layer can be but be not limited to
SiNx/SiOxFilm layer.
S132 forms the active area materials layer 4 on the substrate for being formed with the buffer layer.
In addition, specifically, the active area materials layer 4 is amorphous silicon material layer；Between step S1 and step S2, also
It include: to handle the amorphous silicon material layer for polysilicon material layer.Further specifically, dehydrogenation is carried out to amorphous silicon material layer
And ELA anneals to form polysilicon material layer.
S2 forms source-drain electrode material layer 5, as shown in Figure 2 on the active area materials layer 4.
Specifically, source-drain electrode material layer 5 can be but be not limited to Ti/Al/Ti film layer or Mo/Al/Mo film layer, with a thickness of
S3 executes a patterning processes using gray level mask plate, and forming the source-drain electrode material layer 5 includes data line
The figure of data and the active area materials layer 4 is made to form the be located at below the figure that the source-drain electrode material layer 5 is formed
One region 41 and the second area on the outside of the first area, as shown in Figure 3 e.
Specifically, so-called gray level mask plate refer to mask plate there are the light transmission rate of different zones difference.Such as Fig. 3 a~figure
Shown in 3e, a layer photoresist PR is initially formed in source-drain electrode material layer 5, the photoresist PR under gray level mask plate is by light
The denaturation degrees of irradiation, different zones are different, in this case, can be formed shown in Fig. 3 e by a patterning processes.
S4 forms gate insulation layer on the substrate for being formed with data line data, first area 41 and second area 42
6, as shown in Figure 4.
S5 forms gate material layers on the gate insulation layer 6, makes the gate material layers shape using a patterning processes
At the figure of grid 7, and keep the grid 7 corresponding with the part as active area 421 of the second area 42, such as Fig. 5
It is shown.
S6 makes the conductor of region 422 and 423 positioned at the grid two sides of the second area 42, to will be described
Active area 421 is electrically connected with the data line data, pixel electrode respectively, as shown in fig. 6, region 422 is for connecting active area
421 and data line data；Region 423 is for connecting active area 421 and pixel electrode.
Specifically, the conductor of region 422 and 423 is made by doping process；And, it is preferable that carry out lightly doped drain
(Lightly Doped Drain, LDD) doping can improve and weaken drain region electric field, to improve thermoelectron degradation effect.
S7 forms the pixel electrode on the substrate for being formed with the grid.
In this embodiment, it is preferred that step S7 the following steps are included:
S71 forms interlayer insulating film 8, as shown in Figure 7 on the substrate 1 for being formed with the grid 7.
S72 forms organic insulator 9 on the interlayer insulating film 8.
S73 forms the first via hole 91 in the organic insulator 9 using a patterning processes, as shown in Figure 8.
S74 forms passivation layer 10 on the substrate for being formed with the organic insulator 9 with the first via hole 91.
Specifically, in the present embodiment, above-mentioned steps S74 the following steps are included:
S741 forms public electrode material on the substrate 1 for being formed with the organic insulator 9 with the first via hole 91
Layer.
S742 makes the public electrode material layer form public electrode 11, as shown in Figure 9 using a patterning processes.
S743 forms the passivation layer 10, as shown in Figure 10 on the substrate 1 for being formed with the public electrode 11.
S75 is formed using a patterning processes at 91 position of the first via hole through the passivation layer 10, the layer
Between insulating layer 8 and the gate insulating layer 6 the second via hole 12 and third via hole 13, second via hole 12 corresponding described second
At the position that region 42 is electrically connected with the data line data, as shown in figure 11；Corresponding secondth area of the third via hole 13
At the position that domain 42 is electrically connected with the pixel electrode, as shown in figure 11.
Using a step etching technics Etch Passivation 10, interlayer insulating film 8 and gate insulating layer 6, thickness difference is smaller, because
This, advantageously reduces bad.
S76 forms pixel electrode material layer on the substrate 1 with second via hole 12 and the third via hole 13.
S77, forming the pixel electrode material layer using a patterning processes includes pixel electrode 14 and with second
The figure of via hole 12 and the corresponding connection electrode 15 and 16 of third via hole 13, as shown in figure 12.It can be effective using connection electrode 15
Improve the switching performance of data line data and region 422；Pixel electrode and region 423 can be effectively improved using connection electrode 15
Switching performance.
From the foregoing, it will be observed that the preparation method of array substrate provided in an embodiment of the present invention, can form only with one-time process
Active area, source-drain electrode (region 422 and region 423) and data line, this is compared with prior art, it is possible to reduce a composition work
Skill (for example, MASK technique), so that simple process and reduction production cost.
In addition, passivation layer, interlayer insulating film and gate insulating layer use a composition work in above-mentioned steps S75 of the present invention
Skill, this compared with prior art, and can reduce by a patterning processes.
Therefore, equally it is the array substrate to form the top gate structure with identical film layer, has only used 7 Mask in the present invention
Technique, this reduces 2 Mask techniques, to largely make technique compared with the prior art needs 9 Mask techniques
Simple and reduction production cost.
In addition, since source-drain electrode (region 422 and region 423) can directly be in contact with semiconductor layer, it can reduce
Pixel electrode layer overlapped resistance.
It needs described herein to be that in practical applications, the use gray level mask plate in step S2 executes a structure
Figure technique makes the source-drain electrode material layer form the figure for including the steps that data line, can also include: using gray level mask plate
By a patterning processes, forming the source-drain electrode material layer includes the figure of data line, the source electrode and the data line
Electrical connection；In this case, above-mentioned steps S6 includes: to make in two lateral areas positioned at the grid 7 of the second area 42
Domain conductor, to be respectively electrically connected the active area and the source electrode, the drain electrode；Above-mentioned steps S7 includes: to be formed
There is the pixel electrode for being formed on the substrate of the grid and being electrically connected with the drain electrode, to finally realize active area by source
Pole is adjacent with data line, and active area is connected by drain electrode with pixel electrode.
Embodiment 2
The present invention also provides a kind of array substrate, the array substrate uses the array base of the above embodiment of the present invention offer
The preparation method of plate prepares.
Array substrate provided in an embodiment of the present invention, due to its array substrate for using the above embodiment of the present invention to provide
Preparation method obtains, it is thus possible to improve yield and at low cost.
Embodiment 3
The embodiment of the present invention also provides a kind of display device, including array substrate, and the array substrate is using in the present invention
The array substrate of the offer of embodiment 2 is provided.
Array substrate provided in an embodiment of the present invention, since it uses the array substrate of the offer of the above embodiment of the present invention 2,
Therefore at low cost.
It is understood that the principle that embodiment of above is intended to be merely illustrative of the present and the exemplary implementation that uses
Mode, however the present invention is not limited thereto.For those skilled in the art, essence of the invention is not being departed from
In the case where mind and essence, various changes and modifications can be made therein, these variations and modifications are also considered as protection scope of the present invention.
Claims (8)
1. a kind of preparation method of array substrate, which comprises the following steps:
Active area materials layer is formed on substrate；
Source-drain electrode material layer is formed on the active area materials layer；
Patterning processes are executed using gray level mask plate, make the source-drain electrode material layer formed include data line figure and
The active area materials layer is set to form the first area being located at below the figure that the source-drain electrode material layer is formed and be located at described
Second area on the outside of first area；
Gate insulation layer is formed on the substrate for being formed with data line, first area and second area；
Gate material layers are formed on the gate insulation layer, so that the gate material layers is formed grid using a patterning processes
Figure, and keep the grid corresponding with the part as active area of the second area；
The area conductors positioned at the grid two sides for making the second area, to by the active area respectively with the number
It is electrically connected according to line, pixel electrode；
The pixel electrode is formed on the substrate for being formed with the grid, comprising the following steps:
Interlayer insulating film is formed on the substrate for being formed with the grid；
Organic insulator is formed on the interlayer insulating film；
The first via hole is formed in the organic insulator using a patterning processes；
Passivation layer is formed on the substrate for being formed with the organic insulator with the first via hole；
It crosses hole location described first using a patterning processes and is formed and run through the passivation layer, the interlayer insulating film and institute
The second via hole and third via hole of gate insulating layer are stated, second via hole corresponds to the second area and is electrically connected with the data line
At the position connect；The third via hole corresponds at the position that the second area is electrically connected with the pixel electrode；
Pixel electrode material layer is formed on the substrate with second via hole and the third via hole；
Using a patterning processes make the pixel electrode material layer formed include pixel electrode and with the second via hole and third
The figure of the corresponding connection electrode of via hole.
2. the preparation method of array substrate according to claim 1, which is characterized in that described to be executed using gray level mask plate
Patterning processes make the source-drain electrode material layer form the figure for including the steps that data line, comprising:
Using gray level mask plate by a patterning processes, forming the source-drain electrode material layer includes the figure of data line, institute
Data line is stated to be electrically connected with source electrode；
The area conductors positioned at the grid two sides for making the second area, to by the active area respectively with institute
The step of stating data line, pixel electrode electrical connection, comprising:
Make the two side areas conductor positioned at the grid in the second area, to respectively by the active area and described
Data line, pixel electrode electrical connection；
It is described the step of forming the pixel electrode on the substrate for being formed with the grid, comprising:
The pixel electrode being electrically connected with drain electrode is formed on the substrate for being formed with the grid.
3. the preparation method of array substrate according to claim 2, which is characterized in that described to be formed with the first mistake
The step of passivation layer is formed on the substrate of the organic insulator in hole, comprising:
Public electrode material layer is formed on the substrate for being formed with the organic insulator with the first via hole；
The public electrode material layer is set to form public electrode using a patterning processes；
The passivation layer is formed on the substrate for being formed with the public electrode.
4. the preparation method of array substrate according to claim 1, which is characterized in that described to form active area on substrate
The step of material layer, comprising:
It is formed with light-shielding material layers on the substrate；
The light-shielding material layers are made to form light shield layer using a patterning processes, for blocking the active area；
The active area materials layer is formed on the substrate for being formed with the light shield layer.
5. the preparation method of array substrate according to claim 4, which is characterized in that described to be formed with the light shield layer
The substrate on the step of forming the active area materials layer, further includes:
Buffer layer is formed on the substrate for being formed with the light shield layer；
The active area materials layer is formed on the substrate for being formed with the buffer layer.
6. the preparation method of array substrate according to claim 1, which is characterized in that the active area materials layer is amorphous
Silicon material layer；
Before forming source-drain electrode material layer on the active area materials layer, further includes:
The amorphous silicon material layer is handled as polysilicon material layer.
7. a kind of array substrate, which is characterized in that using the preparation method of array substrate as claimed in any one of claims 1 to 6
It prepares.
8. a kind of display device, including array substrate, which is characterized in that the array substrate uses battle array as claimed in claim 7
Column substrate.
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|---|---|
| CN106206429A (en) | 2016-12-07 |
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