CN106206272B - The preparation method of metal silicide is formed on grating of semiconductor element - Google Patents
The preparation method of metal silicide is formed on grating of semiconductor element Download PDFInfo
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- CN106206272B CN106206272B CN201510230753.6A CN201510230753A CN106206272B CN 106206272 B CN106206272 B CN 106206272B CN 201510230753 A CN201510230753 A CN 201510230753A CN 106206272 B CN106206272 B CN 106206272B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 81
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 62
- 239000002184 metal Substances 0.000 title claims abstract description 62
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 27
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 27
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 100
- 229920005591 polysilicon Polymers 0.000 claims abstract description 99
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 60
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 60
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 46
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 46
- 239000010703 silicon Substances 0.000 claims abstract description 46
- 238000000034 method Methods 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 8
- 239000000243 solution Substances 0.000 claims description 28
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 claims description 20
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 18
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 18
- 239000007789 gas Substances 0.000 claims description 18
- 150000002500 ions Chemical class 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 9
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 230000001681 protective effect Effects 0.000 claims description 6
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 4
- 239000011259 mixed solution Substances 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 239000011261 inert gas Substances 0.000 claims description 3
- 238000001459 lithography Methods 0.000 claims description 3
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 2
- 239000000908 ammonium hydroxide Substances 0.000 claims description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 2
- -1 phosphonium ion Chemical class 0.000 claims description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims 2
- 239000004020 conductor Substances 0.000 claims 1
- 238000001259 photo etching Methods 0.000 abstract description 4
- 230000005611 electricity Effects 0.000 abstract description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 15
- 229910052757 nitrogen Inorganic materials 0.000 description 7
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 4
- 239000002253 acid Substances 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 229910000077 silane Inorganic materials 0.000 description 4
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 241000790917 Dioxys <bee> Species 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- XFDJMIHUAHSGKG-UHFFFAOYSA-N chlorethoxyfos Chemical compound CCOP(=S)(OCC)OC(Cl)C(Cl)(Cl)Cl XFDJMIHUAHSGKG-UHFFFAOYSA-N 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- VTGARNNDLOTBET-UHFFFAOYSA-N gallium antimonide Chemical compound [Sb]#[Ga] VTGARNNDLOTBET-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- OCGWQDWYSQAFTO-UHFFFAOYSA-N tellanylidenelead Chemical compound [Pb]=[Te] OCGWQDWYSQAFTO-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides the preparation method that metal silicide is formed on a kind of grating of semiconductor element, this method comprises: after sequentially forming gate oxide, resistance lowering polysilicon layer on the surface of semiconductor silicon substrate；The deposited silicon nitride on the surface of resistance lowering polysilicon layer forms silicon nitride layer；Grid is formed after photoetching, etching, re-forms body area, source region and drain region；Oxide layer is formed on the surface of entire device；The oxide layer on silicon nitride layer surface is removed, silicon nitride layer is removed；After covering metal layer on entire device surface, the metal layer on resistance lowering polysilicon layer surface, which reacts, to form metal silicide, then removes unreacted metal layer.The problem of preventing semiconductor devices from leaking electricity is realized, the reliability of semiconductor devices is improved.
Description
Technical field
The present invention relates to metal silicide is formed in field of semiconductor technology more particularly to a kind of grating of semiconductor element
Preparation method.
Background technique
Semiconductor devices is the common device in industry production, needs to form metal silication on the grid of semiconductor devices
Object reduces the resistance of grid.
On the grating of semiconductor element provided in the prior art formed metal silicide the preparation method comprises the following steps: in semiconductor silicon
Deposited silicon nitride on polysilicon layer in substrate, so as to form silicon nitride layer；Then, more from the upper direction of semiconductor silicon substrate
N-type ion is injected in crystal silicon layer, so that polysilicon layer becomes resistance lowering polysilicon layer；Then to silicon base carry out photoetching, etching,
With the processes such as thermal oxidation, oxide layer is formed on the surface of silicon base；Again using on acid solution removal silicon nitride layer
Oxide layer；After removal silicon nitride layer and deposited metal, metal silicide is formed on the grid of semiconductor devices.
However in the prior art, when N-type ion is injected in the upper direction polysilicon layer from semiconductor silicon substrate, nitrogen
Also it can be entered N-type ion in SiClx layer, to encourage the formation of the oxide layer on silicon nitride layer, need to soak semiconductor devices
It steeps in the container for filling acid solution, takes a long time and acid solution is allowed to remove the oxidation on silicon nitride layer
Layer, so that it is more also to make the oxide layer in other regions of silicon base lose；After metal deposition, silicon base other regions
Silicon can pass through oxide layer and react with metal, go to form metal silicide, the shape not merely on the grid of semiconductor devices
At metal silicide.The phenomenon that cause semiconductor devices electric leakage, and then semiconductor devices is damaged, reduce semiconductor device
The reliability of part.
Summary of the invention
The present invention provides the preparation method that metal silicide is formed on a kind of grating of semiconductor element, existing to solve
The phenomenon that preparation method causes semiconductor devices to leak electricity, and then semiconductor devices is damaged, reduce semiconductor device reliability
Problem.
The present invention provides the preparation method that metal silicide is formed on a kind of grating of semiconductor element, comprising:
After forming gate oxide on the surface of semiconductor silicon substrate, resistance lowering is formed on the surface of the gate oxide
Polysilicon layer；
The deposited silicon nitride on the surface of the resistance lowering polysilicon layer forms silicon nitride layer；
Lithography and etching is carried out to the gate oxide, the resistance lowering polysilicon layer and the silicon nitride layer, forms institute
State the grid of semiconductor devices；
Form body area, source region and the drain region of semiconductor devices；
On the surface of the source region, the drain region and the silicon nitride layer and the side of the resistance lowering polysilicon layer
Oxide layer is formed on face；
Using hydrofluoric acid solution, the oxide layer on the silicon nitride layer surface is removed；
Using hot phosphoric acid solution, the silicon nitride layer is removed；
Metal layer is covered on entire device surface；
Using inert gas as protective gas, the high temperature anneal is carried out to the silicon base, to pass through the low-resistance
Change polysilicon layer and the metal layer on resistance lowering polysilicon layer surface reacts to form metal silicide；
Remove the metal layer not reacted with the resistance lowering polysilicon layer.
The preparation method that metal silicide is formed on grating of semiconductor element provided by the invention, in semiconductor silicon substrate
After forming gate oxide on surface, resistance lowering polysilicon layer is formed on the surface of gate oxide；Again in resistance lowering polysilicon layer
Surface on deposited silicon nitride, formed silicon nitride layer；To gate oxide, resistance lowering polysilicon layer and silicon nitride layer carry out photoetching and
Etching, forms the grid of semiconductor devices；Re-form body area, source region and the drain region of semiconductor devices；In source region, drain region and nitridation
Oxide layer is formed on the surface of silicon layer and on the side of resistance lowering polysilicon layer；Using hydrofluoric acid solution, silicon nitride layer is removed
Oxide layer on surface；Using hot phosphoric acid solution, silicon nitride layer is removed；Metal layer is covered on entire device surface；Using lazy
Property gas as protective gas, the high temperature anneal is carried out to silicon base, by resistance lowering polysilicon layer and to be located at resistance lowering
Metal layer on polysilicon layer surface reacts to form metal silicide；Remove the metal layer not reacted with resistance lowering polysilicon layer.
Can be relatively thin to form the thickness of oxide layer on silicon nitride layer, it is easily removed, it is only necessary to which semiconductor devices is being filled into acidity
The short period is impregnated in the container of solution, so that it may be removed the oxide layer on silicon nitride layer, while will not be made other areas of silicon base
The oxide layer loss in domain is more, and then only can form metal silicide on the grid of semiconductor devices in subsequent steps；
The phenomenon that not will cause semiconductor devices electric leakage, improves the reliability of semiconductor devices.
Detailed description of the invention
The stream of the preparation method of metal silicide is formed on the grating of semiconductor element that Fig. 1 provides for the embodiment of the present invention one
Journey schematic diagram；
Fig. 2 is the diagrammatic cross-section of grating of semiconductor element in step 101 implementation procedure of embodiment one；
Fig. 3 is another diagrammatic cross-section of grating of semiconductor element in step 101 implementation procedure of embodiment one；
Fig. 4 is the diagrammatic cross-section of grating of semiconductor element in step 102 implementation procedure of embodiment one；
Fig. 5 is the diagrammatic cross-section of grating of semiconductor element in step 103 implementation procedure of embodiment one；
Fig. 6 is the diagrammatic cross-section of grating of semiconductor element in step 104 implementation procedure of embodiment one；
Fig. 7 is the diagrammatic cross-section of grating of semiconductor element in step 105 implementation procedure of embodiment one；
Fig. 8 is the diagrammatic cross-section of grating of semiconductor element in step 106 implementation procedure of embodiment one；
Fig. 9 is the diagrammatic cross-section of grating of semiconductor element in step 107 implementation procedure of embodiment one；
Figure 10 is the diagrammatic cross-section of grating of semiconductor element in step 108 implementation procedure of embodiment one；
Figure 11 is the diagrammatic cross-section of grating of semiconductor element in step 109 implementation procedure of embodiment one；
Figure 12 is the diagrammatic cross-section of grating of semiconductor element in step 110 implementation procedure of embodiment one.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction in this hair embodiment
Attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is this
Invention a part of the embodiment, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art exist
Every other embodiment obtained under the premise of creative work is not made, shall fall within the protection scope of the present invention.
The stream of the preparation method of metal silicide is formed on the grating of semiconductor element that Fig. 1 provides for the embodiment of the present invention one
Journey schematic diagram, in order to understand to the method in the present embodiment the description of system, as shown in Figure 1, method includes:
Step 101 after forming gate oxide on the surface of semiconductor silicon substrate, is formed low on the surface of gate oxide
Resistanceization polysilicon layer.
In the present embodiment, specifically, Fig. 2 is grating of semiconductor element in step 101 implementation procedure of embodiment one
Diagrammatic cross-section, shown in Fig. 2, semiconductor silicon substrate label 11 is indicated, semiconductor silicon substrate 11 includes that substrate and setting are serving as a contrast
Epitaxial layer on bottom surface, epitaxial layer are one or more layers semiconductive thin film；Gate oxide label 12 indicates, resistance lowering polycrystalline
Silicon layer label 14 indicates.
Wherein, semiconductor silicon substrate 11 can be semiconductor element, such as monocrystalline silicon, polysilicon or non crystalline structure silicon or
SiGe (SiGe), or mixed semiconductor structure, such as silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide, arsenic
Change gallium or gallium antimonide, alloy semiconductor or combinations thereof.The present embodiment is not limited herein.
It is passed through oxygen in reacting furnace, at high temperature, forms gate oxide 12 on the surface of semiconductor silicon substrate 11.
Fig. 3 is another diagrammatic cross-section of grating of semiconductor element in step 101 implementation procedure of embodiment one, Fig. 3 institute
Show, polysilicon layer label 13 indicates.Resistance lowering polysilicon layer 14 is formed on the surface of gate oxide 12, it can be in gate oxidation
Polysilicon layer 13 is formed on the surface of layer 12, N-type ion is injected into polysilicon layer 13, forms resistance lowering polysilicon layer 14, mistake
Journey are as follows: use low-pressure chemical vapor deposition method, silane (SiH is passed through in reacting furnace4) gas, silane gas divides at high temperature
Solution is at polysilicon, and polysilicon deposition is on the surface of gate oxide 12, to form polysilicon layer on the surface of gate oxide 12
13；N-type ion is injected into polysilicon layer 13, to reduce the resistance of polysilicon layer 13, so that polysilicon layer 13 becomes resistance lowering
Polysilicon layer 14；The energy of the N-type ion of injection is between 40 kiloelectron-volts~100 kiloelectron-volts, and implantation dosage is in 1E15 original
Between subnumber/square centimeter~1E16 atomicity/square centimeter；Wherein, N-type ion is arsenic ion or phosphonium ion.
Alternatively, resistance lowering polysilicon layer 14 is formed on the surface of gate oxide 12, it can also be in the table of gate oxide 12
Polysilicon layer 13 is formed on face, phosphorus oxychloride gas is adulterated into polysilicon layer 13, forms resistance lowering polysilicon layer 14, process
Are as follows: low-pressure chemical vapor deposition method is used, forms polysilicon layer 13 on the surface of gate oxide 12；By nitrogen (N2) be passed through
To equipped with liquid phosphorus oxychloride (POCl3) container in, the flow of nitrogen is 600 ml/mins~1200 ml/mins, from
The nitrogen outputed in the container has phosphorus oxychloride steam；Under conditions of 800 degrees Celsius~1000 degrees Celsius of temperature, it will take
Nitrogen with phosphorus oxychloride steam is passed into reacting furnace, so that phosphorus oxychloride steam enters in polysilicon layer 13, this
Reaction time is half an hour to 2 hours, to be doped with phosphorus oxychloride gas in polysilicon layer 13, polysilicon layer 13 becomes low
Resistanceization polysilicon layer 14；Wherein, the flow of nitrogen is bigger, and the phosphorus oxychloride steam that nitrogen carries is more, to there is more three
Chlorethoxyfos steam enters in polysilicon layer 13, and the resistance of resistance lowering polysilicon layer 14 is with regard to smaller.Alternatively, in gate oxide 12
Resistance lowering polysilicon layer 14 is formed on surface, and the polysilicon adulterated in situ, shape can also be deposited on the surface of gate oxide 12
At resistance lowering polysilicon layer 14, process are as follows: use low-pressure chemical vapor deposition method, silane (SiH is passed through in reacting furnace4) gas
Body and phosphine (PH3) gas, silane gas resolves into polysilicon at high temperature, while phosphine gas is taken the photograph 500 degrees Celsius~800
It decomposes under the hot conditions of family name's degree, so that P elements have been entrained in polysilicon, is doped with the polysilicon deposition of P elements
On the surface of gate oxide 12, to form resistance lowering polysilicon layer 14 on the surface of gate oxide 12.
Step 102, the deposited silicon nitride on the surface of resistance lowering polysilicon layer form silicon nitride layer.
In the present embodiment, specifically, Fig. 4 is grating of semiconductor element in step 102 implementation procedure of embodiment one
Diagrammatic cross-section, shown in Fig. 4, silicon nitride layer label 15 is indicated.
Using low-pressure chemical vapor deposition method, dichlorosilane (SiH is passed through in reacting furnace2Cl2) and ammonia (NH3) gas
Body, at high temperature, two kinds of gases chemically react, and generate silicon nitride, table of the nitride deposition in resistance lowering polysilicon layer 14
On face, silicon nitride layer 15 is formed.
Wherein, silicon nitride layer 15 with a thickness of between 200 angstroms~500 angstroms.
Step 103 carries out lithography and etching to gate oxide, resistance lowering polysilicon layer and silicon nitride layer, forms semiconductor
The grid of device.
In the present embodiment, specifically, Fig. 5 is grating of semiconductor element in step 103 implementation procedure of embodiment one
Diagrammatic cross-section, shown in Fig. 5.
Photoetching is carried out to gate oxide 12, resistance lowering polysilicon layer 14 and silicon nitride layer 15, is then performed etching again,
In, the mode of etching can include but is not limited to reactive ion etching (Reactive-Ion Etching, abbreviation RIE) and induction
Coupled plasma etch (Inductively Coupled Plasma, abbreviation ICP), and then form the grid of semiconductor devices
Pole.
Step 104, body area, source region and the drain region for forming semiconductor devices.
In the present embodiment, specifically, Fig. 6 is grating of semiconductor element in step 104 implementation procedure of embodiment one
Diagrammatic cross-section, shown in Fig. 6, body area label 16 indicates that source region label 17 indicates, drain region label 18 indicates.
Ion is inputted into silicon base 11, the region for injecting N-type ion forms source region 17 and drain region 18, injecting p-type ion
Region formed body area 16, to form N-type semiconductor device；Or the region of injecting p-type ion forms source region 17 and drain region
18, the region formed body area 16 of N-type ion is injected, to form P-type semiconductor device.
Step 105 is formed on the surface of source region, drain region and silicon nitride layer and on the side of resistance lowering polysilicon layer
Oxide layer.
In the present embodiment, specifically, Fig. 7 is grating of semiconductor element in step 105 implementation procedure of embodiment one
Diagrammatic cross-section, shown in Fig. 7, oxide layer label 19 is indicated.
It is passed through oxygen at high temperature in reacting furnace, thermal oxidation is carried out to silicon base 11, source region 17 and drain region 18
Oxide layer 19 is formed on surface and the side of resistance lowering polysilicon layer 14；Silicon nitride layer 15 can react with oxygen simultaneously,
Oxide layer 19 is formed on the surface of silicon nitride layer 15.
Wherein, thermal oxidation, surface and resistance lowering polysilicon in source region 17 and drain region 18 are carried out to silicon base 11
It is silicon dioxide layer that oxide layer 19 is formed on the side of layer 14, and it is nitrogen oxidation that oxide layer 19 is formed on the surface of silicon nitride layer 15
Silicon layer；And the thickness of silicon oxynitride layer is less than the thickness of silicon dioxide layer, the dioxy right with a thickness of 30 Izods of silicon oxynitride layer
SiClx layer with a thickness of 300 Izods the right side.
Step 106, using hydrofluoric acid solution, remove the oxide layer on silicon nitride layer surface.
In the present embodiment, specifically, Fig. 8 is grating of semiconductor element in step 106 implementation procedure of embodiment one
Diagrammatic cross-section shown in Fig. 8, eliminates the oxide layer on 15 surface of silicon nitride layer.Hydrofluoric acid solution can be used, is completely removed
Silicon oxynitride layer on 15 surface of silicon nitride layer is in this process, more on the surface in source region 17 and drain region 18 and resistance lowering
Oxide layer 19 on the side of crystal silicon layer 14 can also be removed the 40 Izods right side, there remains 260 angstroms.To on 15 surface of silicon nitride layer
Oxide layer can be completely removed；And on the surface in source region 17 and drain region 18 and the side of resistance lowering polysilicon layer 14
Oxide layer there remains very much, can play a protective role
Wherein, hydrofluoric acid solution can use water and hydrofluoric acid ratio for the solution of 100:1.
Step 107 utilizes hot phosphoric acid solution, removal silicon nitride layer.
In the present embodiment, specifically, Fig. 9 is grating of semiconductor element in step 107 implementation procedure of embodiment one
Diagrammatic cross-section shown in Fig. 9, eliminates silicon nitride layer.
Silicon nitride layer is removed using hot phosphoric acid solution, since the characteristic of phosphoric acid solution is only to react with silicon nitride,
Without reacting with oxide layer 19, so this step can't have corrosiveness to oxide layer 19.
Wherein it is possible to remove silicon nitride layer using 170 degrees Celsius of hot phosphoric acid solution.
Step 108 covers metal layer on entire device surface.
In the present embodiment, specifically, Figure 10 is grating of semiconductor element in step 108 implementation procedure of embodiment one
Diagrammatic cross-section, shown in Figure 10, metal layer label 20 is indicated.
Using physical vapour deposition (PVD) (Physical Vapor Deposition, abbreviation PVD) method, Ar -bombardment is used
Metal, so that metal deposit forms metal layer 20 on the surface of entire device；Wherein, metal can be titanium (Ti) or cobalt (Co)
Or nickel (Ni).
Step 109, using inert gas as protective gas, the high temperature anneal is carried out to silicon base, to pass through low-resistance
Change polysilicon layer and the metal layer on resistance lowering polysilicon layer surface reacts to form metal silicide.
In the present embodiment, specifically, Figure 11 is grating of semiconductor element in step 109 implementation procedure of embodiment one
Diagrammatic cross-section, shown in Figure 11, metal silicide label 21 is indicated.
Using inert nitrogen gas as protective gas, short annealing processing, resistance lowering are carried out to silicon base 11 at high temperature
Polysilicon layer 14 reacts with metal layer 21, forms the metal silicide 21 of 49 phases；Meanwhile in the table of source region 17 and drain region 18
Because there is the protection of oxide layer 19, metal will not occur metal layer 20 on face and the side of resistance lowering polysilicon layer 14 with silicon
Reaction, metal will not react with oxide layer 19, thus surface and resistance lowering polysilicon in source region 17 and drain region 18
Metal layer 20 on the side of layer 14 will not become metal silicide.
The metal layer that step 110, removal are not reacted with resistance lowering polysilicon layer.
In the present embodiment, specifically, Figure 12 is grating of semiconductor element in step 110 implementation procedure of embodiment one
Diagrammatic cross-section shown in Figure 12, eliminates the metal layer not reacted with resistance lowering polysilicon layer 14.
Can use the mixed solution of sulfuric acid and hydrogen peroxide or the mixed solution of ammonium hydroxide and hydrogen peroxide, removal not with it is low
The metal layer of resistanceization polysilicon layer reaction.
The present embodiment injects N-type ion or doping phosphorus oxychloride gas into polysilicon layer by first, or directly in grid
The surface of oxide layer deposits the polysilicon adulterated in situ, removes the resistance for reducing polysilicon layer, forms resistance lowering polysilicon layer；Exist again
Deposited silicon nitride on the surface of resistance lowering polysilicon layer forms silicon nitride layer.To form the thickness of oxide layer on silicon nitride layer
Degree can be relatively thin, is easily removed, it is only necessary to semiconductor devices be impregnated the short period in the container for filling acid solution, so that it may go
Silicon oxynitride layer this layer of oxide layer on silicon nitride layer, while the oxide layer in other regions of silicon base will not be made to lose more
It is more, and then in subsequent steps only metal silicide can be formed on the grid of semiconductor devices；It not will cause semiconductor device
The phenomenon that part leaks electricity, improves the reliability of semiconductor devices.
Further, on the basis of the above embodiments, after step 110, further includes: high temperature is carried out to silicon base and is moved back
Fire processing.
In the present embodiment, specifically, eliminating the metal layer not reacted with resistance lowering polysilicon layer and then right
Silicon base carry out a high temperature anneal so that on resistance lowering polysilicon layer 49 phases metal silicide, be converted into 54 phases
Metal silicide.
Present embodiment is by carrying out the high temperature anneal to silicon base again, by the metal silication of 49 phases on polysilicon gate layer
Object is converted into the metal silicide of lower 54 phase of resistance value.So that semiconductor devices has the function of preferably to be connected.
Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
Present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: it still may be used
To modify the technical solutions described in the foregoing embodiments or equivalent replacement of some of the technical features；
And these are modified or replaceed, technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution spirit and
Range.
Claims (10)
1. forming the preparation method of metal silicide on a kind of grating of semiconductor element characterized by comprising
After forming gate oxide on the surface of semiconductor silicon substrate, resistance lowering polycrystalline is formed on the surface of the gate oxide
Silicon layer；
The deposited silicon nitride on the surface of the resistance lowering polysilicon layer forms silicon nitride layer；
Lithography and etching is carried out to the gate oxide, the resistance lowering polysilicon layer and the silicon nitride layer, forms described half
The grid of conductor device；
Form body area, source region and the drain region of semiconductor devices；
On the surface of the source region, the drain region and the silicon nitride layer and on the side of the resistance lowering polysilicon layer
Form oxide layer；
Using hydrofluoric acid solution, the oxide layer on the silicon nitride layer surface is removed；
Using hot phosphoric acid solution, the silicon nitride layer is removed；
Metal layer is covered on entire device surface；
Using inert gas as protective gas, the high temperature anneal is carried out to the silicon base, with more by the resistance lowering
Crystal silicon layer and the metal layer on resistance lowering polysilicon layer surface react to form metal silicide；
Remove the metal layer not reacted with the resistance lowering polysilicon layer；
On the surface of the silicon nitride layer formed silicon oxide layer thickness be less than the source region and the drain region surface with
And silicon oxide layer thickness is formed on the side of the resistance lowering polysilicon layer.
2. the method according to claim 1, wherein what the removal was not reacted with the resistance lowering polysilicon layer
After metal layer, further includes:
The high temperature anneal is carried out to the silicon base.
3. the method according to claim 1, wherein described form resistance lowering on the surface of the gate oxide
Polysilicon layer, comprising:
Polysilicon layer is formed on the surface of the gate oxide；
N-type ion is injected into the polysilicon layer, forms the resistance lowering polysilicon layer；
Wherein, the N-type ion is arsenic ion or phosphonium ion.
4. the method according to claim 1, wherein described form resistance lowering on the surface of the gate oxide
Polysilicon layer, comprising:
Polysilicon layer is formed on the surface of the gate oxide；
Phosphorus oxychloride gas is adulterated into the polysilicon layer, forms the resistance lowering polysilicon layer.
5. the method according to claim 1, wherein described form resistance lowering on the surface of the gate oxide
Polysilicon layer, comprising:
The polysilicon adulterated in situ is deposited on the surface of the gate oxide, forms the resistance lowering polysilicon layer.
6. the method according to claim 1, wherein what the removal was not reacted with the resistance lowering polysilicon layer
Metal layer, comprising:
Using the mixed solution or ammonium hydroxide of sulfuric acid and hydrogen peroxide and the mixed solution of hydrogen peroxide, removal not with the resistance lowering
The metal layer of polysilicon layer reaction.
7. the method according to claim 1, wherein described in the source region, the drain region and the silicon nitride
Oxide layer is formed on the surface of layer and on the side of the resistance lowering polysilicon layer, comprising:
Thermal oxidation, surface and the resistance lowering polysilicon in the source region and the drain region are carried out to the silicon base
Silicon dioxide layer is formed on the side of layer, forms silicon oxynitride layer on the surface of the silicon nitride layer；
Wherein, the thickness of the silicon oxynitride layer is less than the thickness of the silicon dioxide layer.
8. the method according to claim 1, wherein the hydrofluoric acid solution use water and hydrofluoric acid ratio for
The solution of 100:1.
9. the method according to claim 1, wherein the silicon nitride layer with a thickness of 200 angstroms~500 angstroms.
10. -9 any method according to claim 1, which is characterized in that utilize hot phosphoric acid solution, remove the silicon nitride
Layer, comprising:
Using 170 degrees Celsius of hot phosphoric acid solution, the silicon nitride layer is removed.
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|---|---|---|---|---|
| US20030017657A1 (en) * | 2001-06-29 | 2003-01-23 | Myoung-Sik Han | Method of forming a gate electrode in a semiconductor device and method of manufacturing a non-volatile memory device using the same |
| US20080160706A1 (en) * | 2006-12-27 | 2008-07-03 | Jin Hyo Jung | Method for fabricating semiconductor device |
| CN104347374A (en) * | 2013-07-30 | 2015-02-11 | 北大方正集团有限公司 | Manufacturing method of semiconductor device |
| CN104425572A (en) * | 2013-09-09 | 2015-03-18 | 北大方正集团有限公司 | Self-aligned silicide transistor and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030017657A1 (en) * | 2001-06-29 | 2003-01-23 | Myoung-Sik Han | Method of forming a gate electrode in a semiconductor device and method of manufacturing a non-volatile memory device using the same |
| US20080160706A1 (en) * | 2006-12-27 | 2008-07-03 | Jin Hyo Jung | Method for fabricating semiconductor device |
| CN104347374A (en) * | 2013-07-30 | 2015-02-11 | 北大方正集团有限公司 | Manufacturing method of semiconductor device |
| CN104425572A (en) * | 2013-09-09 | 2015-03-18 | 北大方正集团有限公司 | Self-aligned silicide transistor and manufacturing method thereof |
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