CN106201766A - Data storage control method and data server - Google Patents
Data storage control method and data server Download PDFInfo
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- CN106201766A CN106201766A CN201610590235.XA CN201610590235A CN106201766A CN 106201766 A CN106201766 A CN 106201766A CN 201610590235 A CN201610590235 A CN 201610590235A CN 106201766 A CN106201766 A CN 106201766A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
Abstract
The invention discloses a kind of data storage control method and data server, the method includes: when data server receives the first data, the first data is stored in fpga chip；After the first data receiver completes, call the verification data of the first data of storage during the correcting and eleting codes of storage calculates fpga chip in fpga chip, and calculate the first data and the stored ratio of verification data of storage in fpga chip；Split, according to stored ratio, the first data stored in fpga chip and verification data obtain multiple second data, and the second data are respectively stored in each memory element of memorizer.Present invention reduces correcting and eleting codes memorizer running space is taken, improve the data storage capacities of memorizer, and then improve the computational efficiency of correcting and eleting codes.
Description
Technical field
The present invention relates to technical field of data storage, particularly relate to a kind of data storage control method and data server.
Background technology
Deposit to distributed from independent hard disk redundancy array (Redundant Arrays Independent Disks, RAID)
Storage system, correcting and eleting codes is extensively stored in storage system, for the data writing in storage system and reading are carried out backup and
Storage management, to ensure normal read-write and data safety.But it is as data and presents explosive growth trend, correcting and eleting codes logarithm
According to amount of calculation the most increasing, therefore take the running space that storage system is more, the data not only resulting in storage system are deposited
Energy storage power reduces, and reduces the computational efficiency of correcting and eleting codes.
Summary of the invention
Present invention is primarily targeted at a kind of data storage control method of offer and data server, it is intended to solve storage
The problem that the data-handling capacity of system is low.
For achieving the above object, a kind of data storage control method that the present invention provides, described data storage control method
Including:
When data server receives the first data, described first data are stored in fpga chip；
After described first data receiver completes, call in the correcting and eleting codes described fpga chip of calculating of storage in fpga chip
The verification data of the first data of storage, and calculate the first data of storage in described fpga chip and described verification data
Stored ratio；
Split, according to described stored ratio, the first data stored in described fpga chip and described verification data obtain
Multiple second data, and described second data are respectively stored in each memory element of described memorizer.
Preferably, the step in described each memory element that described second data store described memorizer includes:
Call each described second data successively, and store corresponding memory element；
When calling described second data every time, it is judged that whether memory element corresponding to described second data to be stored
Storage fault occurs；
The most then send interrupt message to the memory element that described second data are corresponding, corresponding for described second data
Memory element according to described interrupt message stop store described second data；
If it is not, then described second data called are stored in the memory element of correspondence.
Preferably, described according to the first data stored in the described stored ratio described fpga chip of fractionation and described school
Test data to obtain the step of the second data and include:
The first fractionation amount of the first data of storage and described is determined in described fpga chip according to described stored ratio
Second fractionation amount of verification data；
Split the first data of storage in described fpga chip according to described first fractionation amount, and split according to described second
Amount split described verification data, and will split after described fpga chip in storage the first data with split after described verification
Data are as described second data.
Preferably, described data storage control method also includes:
When described data server receives data read command, call described FPGA according to described data read command
Correcting and eleting codes in chip；
According to continuing of storing in each described memory element that the described correcting and eleting codes described data read command of restructuring is corresponding
Fetch data.
Preferably, in described each described memory element corresponding according to the described correcting and eleting codes described data read command of restructuring
The step of the data to be read of storage includes:
It is successively read in each described memory element that described data read command is corresponding the data to be read of storage；
After described digital independent to be read completes, it is judged that whether the data described to be read of reading exist failure number
According to；
When there is fail data in described data to be read, use non-failure-data recovery institute in described data to be read
State fail data, and according to described correcting and eleting codes, the described fail data after described non-fail data and recovery is recombinated；
When there is not fail data in described data to be read, according to described correcting and eleting codes, described data to be read are carried out
Restructuring.
Additionally, for achieving the above object, the present invention also provides for a kind of data server, and described data server includes:
Described first data, for when data server receives the first data, are stored in by the first memory module
In fpga chip；
Split module, for after described first data receiver completes, call the correcting and eleting codes of storage in fpga chip and calculate
The verification data of the first data of storage in described fpga chip, and calculate storage in described fpga chip the first data and
The stored ratio of described verification data；
Second memory module, for split according to described stored ratio storage in described fpga chip the first data and
Described verification data obtain multiple second data, and each storage that described second data are respectively stored into described memorizer is single
In unit.
Preferably, described second memory module includes:
Call unit, for calling each described second data successively, and stores corresponding memory element；
First judging unit, for when calling described second data every time, it is judged that described second data to be stored
Whether corresponding memory element there is storage fault；
, if there is storage fault for the memory element that described second data to be stored are corresponding, then to institute in transmitting element
State memory element corresponding to the second data and send interrupt message, for memory element corresponding to described second data according in described
Disconnected message stops storing described second data；
Memory element, if there is not storage fault for the memory element that described second data to be stored are corresponding, then will
Described second data called store in the memory element of correspondence.
Preferably, described second memory module also includes:
Determine unit, for determining that the first of the first data stored in described fpga chip are torn open according to described stored ratio
Component and the second fractionation amount of described verification data；
Split cells, for splitting the first data of storage in described fpga chip, and root according to described first fractionation amount
According to described second fractionation amount split described verification data, and will split after described fpga chip in storage the first data with tear open
Described verification data after Fen are as described second data.
Preferably, described data server also includes:
Calling module, for when described data server receives data read command, refers to according to described digital independent
The correcting and eleting codes in described fpga chip is called in order；
Recombination module, for each described memory element corresponding according to the described correcting and eleting codes described data read command of restructuring
The data to be read of middle storage.
Preferably, described recombination module includes:
Read unit, for being successively read in each described memory element that described data read command is corresponding treating of storage
Read data；
Second judge module, for after described digital independent to be read completes, it is judged that the data described to be read of reading
In whether there is fail data；
First recomposition unit, in time there is fail data in described data to be read, uses described data to be read
In fail data described in non-failure-data recovery, and according to described correcting and eleting codes to described non-fail data and after recovering described in
Fail data is recombinated；
Second recomposition unit, in time there is not fail data in described data to be read, according to described correcting and eleting codes pair
Described data to be read are recombinated.
First data, by when data server receives the first data, are stored in fpga chip by the present invention,
After first data receiver completes, call the school of the first data of storage during the correcting and eleting codes of storage calculates fpga chip in fpga chip
Test data, and calculate the first data of storage in fpga chip and verify the stored ratio of data, split according to stored ratio
In fpga chip, the first data and the verification data of storage obtain multiple second data, and the second data are respectively stored into and deposit
In each memory element of reservoir.Owing to correcting and eleting codes is stored in fpga chip, when data server receives the first data, will
These first data are temporarily stored in fpga chip, and the correcting and eleting codes calling the storage of this fpga chip calculates this first data correspondence
Check number according to this and the stored ratio of these first data and these verification data, these first data and this verification data are being pressed
Carry out after fractionation obtains multiple second data, these second data being respectively stored into each storage of memorizer according to this stored ratio
In unit, hence in so that the stored ratio that correcting and eleting codes is to the fractionation of data, the determination verifying data and data with verification data
Calculating all carry out in fpga chip, and memorizer is only responsible for distribution memory element and is stored the data after this fractionation and verification
Data, thus reduce correcting and eleting codes and memorizer running space is taken, improve the data storage capacities of memorizer, enter
And improve the computational efficiency of correcting and eleting codes.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the first embodiment of data storage control method of the present invention；
Fig. 2 is each storage that described second data are respectively stored in data storage control method of the present invention memorizer
The schematic flow sheet of the refinement step in unit；
Fig. 3 is to split storage in described fpga chip according to described stored ratio in data storage control method of the present invention
First data and described verification data obtain the schematic flow sheet of the refinement step of multiple second data；
Fig. 4 is the schematic flow sheet of the second embodiment of data storage control method of the present invention；
Fig. 5 is the schematic flow sheet of the refinement step of step S220 in the second embodiment shown in Fig. 4 of the present invention；
Fig. 6 is the high-level schematic functional block diagram of the first embodiment of data server of the present invention；
Fig. 7 be data server of the present invention the second embodiment in the refinement high-level schematic functional block diagram of the second memory module；
Fig. 8 be data server of the present invention the 3rd embodiment in the second memory module another refinement functional module signal
Figure；
Fig. 9 is the high-level schematic functional block diagram of the 4th embodiment of data server of the present invention；
Figure 10 be data server of the present invention the 5th embodiment in the refinement high-level schematic functional block diagram of recombination module.
The realization of the object of the invention, functional characteristics and advantage will in conjunction with the embodiments, are described further referring to the drawings.
Detailed description of the invention
Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
Based on the problems referred to above, the present invention provides a kind of data storage control method.
Schematic flow sheet with reference to the first embodiment that Fig. 1, Fig. 1 are data storage control method of the present invention.
In the present embodiment, described data storage control method includes:
First data, when data server receives the first data, are stored in fpga chip by step S110；
In the present embodiment, correcting and eleting codes is stored in fpga chip, and this fpga chip is applied to data storage server
In, separate with the CPU in data server and memorizer.The first data of outside write are received at data server
Time, the first data received are temporarily stored in the high-speed memory of fpga chip by this data server.Wherein, these data
Server includes PC end, smart mobile phone, intelligent television, panel computer；This high-speed memory includes solid state hard disc (Solid
State Disk, SSD).
Step S120, after the first data receiver completes, calls the correcting and eleting codes of storage in fpga chip and calculates fpga chip
The verification data of the first data of middle storage, and calculate the first data and the storage ratio of verification data of storage in fpga chip
Example；
Determining that these first data receive, and after storing completely in the high-speed memory of this fpga chip, should
Data server calls the correcting and eleting codes of storage in this fpga chip, calculates according to the algorithm of this correcting and eleting codes and is temporarily stored in this high speed
The verification data of the first data in memorizer, and calculate the storage ratio of the first data and these verification data in this high-speed memory
Example.Such as, during the first data of totally 3 bytes store the high-speed memory of fpga chip completely after, this PC end calls FPGA
In chip, the correcting and eleting codes of storage calculates the verification data of these the first data is 1 byte, then calculate in this high-speed memory first
Data are 3:1 with the stored ratio of these verification data.Wherein, these verification data are for obtaining after these first data carry out check code
To character string, when part loss of data in these first data, correcting and eleting codes by these verification data and these first data not
The data lost recover the data of the loss in these first data.
Step S130, splits, according to stored ratio, the first data stored in fpga chip and verification data obtains multiple
Second data, and the second data are respectively stored in each memory element of memorizer.
Determine these first data with verification data stored ratio time, according to this stored ratio split these first data with
And verification data obtain multiple second data, this data server distributes and this second data bulk from the memorizer of local terminal
Consistent unit to be stored, and the byte-sized of the storage size of each unit to be stored and these the second data matches,
These second data are respectively stored in each unit to be stored of memorizer.Wherein, each unit to be stored stores one only
Individual second data.Such as, after the stored ratio of the first data Yu these verification data is 3:1, these first data are split into 3
Data slot, each data slot is 1 byte, and the verification data in conjunction with a byte obtain 4 one byte the second data,
This PC end distributes 4 memory element from the memorizer of local terminal, and the memory space of these 4 memory element is a byte,
Second data of these 4 bytes are respectively stored in 4 memory element.
It should be noted that when these verification data are split into M fragment, and these first data are split into K fragment, should
The total internal memory Y shared by M fragment K/mono-equal to shared total internal memory X of this K fragment, i.e. Y=X*1/K.
First data, by when data server receives the first data, are stored in fpga chip by the present embodiment,
After the first data receiver completes, call the first data of storage during the correcting and eleting codes of storage calculates fpga chip in fpga chip
Verification data, and calculate the first data and the stored ratio of verification data of storage in fpga chip, tear open according to stored ratio
The first data and the verification data of dividing storage in fpga chip obtain multiple second data, and the second data are respectively stored into
In each memory element of memorizer.Owing to correcting and eleting codes is stored in fpga chip, when data server receives the first data,
These first data are temporarily stored in fpga chip, and the correcting and eleting codes calling the storage of this fpga chip calculates this first data pair
The check number answered according to this and the stored ratio of these first data and these verification data, by these first data and this verification data
Carrying out after fractionation obtains multiple second data according to this stored ratio, each that these second data are respectively stored into memorizer is deposited
In storage unit, hence in so that the storage ratio that correcting and eleting codes is to the fractionation of data, the determination verifying data and data with verification data
The calculating of example is all carried out in fpga chip, and memorizer is only responsible for distribution memory element and is stored the data after this fractionation and school
Test data, thus reduce correcting and eleting codes and memorizer running space is taken, improve the data storage capacities of memorizer,
And then improve the computational efficiency of correcting and eleting codes.
Further, refer to Fig. 2, for the flow process signal of the refinement step of step S130 in first embodiment of the invention
Figure, described each memory element that described second data are respectively stored into memorizer includes:
Step S131, calls each the second data successively, and stores corresponding memory element；
In the present embodiment, distribute consistent with this second data bulk from the memorizer of local terminal at data server,
And after the unit to be stored that matches of the byte-sized of storage size and these the second data, this correcting and eleting codes gives this list to be stored
Unit sends and prepares message, and each preparation message includes target second data that each unit needs to be stored store, when
After this unit to be stored receives this preparation message, generate according to this preparation message and prepare daily record, in the standard of this unit to be stored
After standby daily record, send response message to this fpga chip, when this FPGA receives this response message, call this correcting and eleting codes to this
Unit to be stored sends storage message, indicates the write of this unit to be stored to prepare target second data in daily record.Wherein,
This preparation daily record is saved in unit to be stored, needs a target second number of storage for temporarily storing this unit to be stored
According to.
It should be noted that before in the unit to be stored that each second data are stored successively correspondence, to each
Second data distribute a storage address, and the mode increased successively according to number of addresses stores ground to this each the second data distribution
Location.Such as, the first data are split into the second data a, the second data b, the second data c and the second data d, by this second
Before data a, the second data b, the second data c and the second data d store in corresponding unit to be stored successively, according to ground
These second data a of the mode that location number increases successively, the second data b, the second data c and the second data d distribution storage address, point
It is not 0001,0010,0011,0100.
Step S132, when calling the second data every time, it is judged that the memory element that the second data to be stored are corresponding is
No there is storage fault；
When storage the second data every time, it is judged that whether the to be stored unit corresponding with these the second data to be stored feeds back
Response message, if receive the response message of unit to be stored feedback, it is determined that storage fault does not occurs in this unit to be stored,
If do not receive the response message of band memory element feedback, it is determined that storage fault occurs in this unit to be stored.
Step S133, the most then send interrupt message to the memory element that the second data are corresponding, corresponding for the second data
Memory element according to interrupt message stop storage the second data；
When determining that storage fault occurs in this unit to be stored, call this correcting and eleting codes and disappear to the transmission interruption of this unit to be stored
Breath, this unit to be stored deletes according to this interrupt message and prepares daily record, interrupt storage to these target the second data, this target the
Two data and etc. to be stored, if the storage fault recovery of this memory element being detected in Preset Time, then by this target second
Data store in this unit to be stored, if being not detected by the storage fault recovery of this memory element in Preset Time, then should
Data server is redistributed out and the unit to be stored of this target the second Data Matching from the memorizer of local terminal, by this target
Second data store in this unit to be stored.
Step S134, if it is not, then store the second data called in the memory element of correspondence.
When determining that fault does not occurs storing in this unit to be stored, the second data called are stored the storage list of correspondence
In unit.
The present embodiment is by calling each the second data successively, and stores corresponding memory element, is calling every time
During the second data, it is judged that whether memory element corresponding to the second data to be stored storage fault occurs, the most then to the second number
Send interrupt message according to corresponding memory element, stop storage for memory element corresponding to the second data according to interrupt message
Two data, if it is not, then store the second data called in the memory element of correspondence.Owing to each storage of memorizer is to single
Unit is the most all likely to occur storage fault during storage the second data, therefore detects each of this memorizer by the moment
Memory element, it is to avoid during storing these second data, sends storage disorder, causes loss of data, thus ensure data
Safety.
Further, refer to Fig. 3, for the flow process signal of the refinement step of step S130 in first embodiment of the invention
Figure, described splits the first data of storage in described fpga chip according to described stored ratio and described verification data obtain many
Individual second data include:
Step S135, determines the first fractionation amount and verification of the first data of storage in fpga chip according to stored ratio
Second fractionation amount of data；
In the present embodiment, after the stored ratio determining these first data and these verification data is M:K, determine this first
First fractionation amount of data is M, and the second fractionation amount of these verification data is K.
Step S136, splits the first data of storage in fpga chip according to the first fractionation amount, and according to the second fractionation amount
Split verification data, and will split after fpga chip in storage the first data with split after verification data as second number
According to.
According to this first fractionation amount M, these first data are split into M fragment, according to this second fractionation amount K by this verification
Data split into K fragment, thus constitute M+K the second data.
The present embodiment by determine in fpga chip according to stored ratio the first data of storage the first fractionation amount and
Second fractionation amount of verification data, splits the first data of storage in fpga chip according to the first fractionation amount, and tears open according to second
Component splits verification data, and in the fpga chip after splitting the first data of storage with split after verification data as the
Two data.After data a bit of after whole segment data being split according to certain stored ratio due to correcting and eleting codes, the most conveniently deposit
The reservoir storage to the data after this fractionation, and the problem cannot recovered after avoiding the occurrence of the data failure in memorizer.
Further, based on above-mentioned first embodiment, refer to Fig. 4, propose the of data storage control method of the present invention
The schematic flow sheet of two embodiments, in this second embodiment, this data storage control method includes:
Step S210, when data server receives data read command, calls FPGA core according to data read command
Correcting and eleting codes in sheet；
Step S220, reads the peek of continuing of storage in each memory element that instruction is corresponding according to correcting and eleting codes recombination data
According to.
In the present embodiment, when data server receives data read command, such as, receive at data server
During the data read command that client sends, call the correcting and eleting codes of storage in this fpga chip, according to the data in this correcting and eleting codes
Data convert to be read, from storage restructuring direction from small to large, address, is become whole segment data by redundancy feature.Wherein, these data are superfluous
Complementary work can include carrying out splitting into multiple fragment by data according to preset rules, and can be according to the plurality of fragment of this preset rules
Data before reassembling into.
The present embodiment is by when data server receives data read command, calling FPGA according to data read command
Correcting and eleting codes in chip, reads the peek of continuing of storage in each memory element that instruction is corresponding according to correcting and eleting codes recombination data
According to, by correcting and eleting codes, data to be read are recombinated so that these data to be read can normally be read, and improves memorizer
Fault-tolerant ability.
Further, refer to Fig. 5, for the flow process signal of the refinement step of step S220 in second embodiment of the invention
Figure, the refinement step of this step S220 includes:
Step S221, is successively read in each memory element that data read command is corresponding the data to be read of storage；
Step S222, after digital independent to be read completes, it is judged that whether there is failure number in the data to be read of reading
According to；
In the present embodiment, after calling the correcting and eleting codes in fpga chip according to data read command, this correcting and eleting codes to
In each memory element that this data read command is corresponding, the data to be read of storage send data call instruction, read with these data
Locally stored data to be read are sent to this fpga chip according to this call instruction by each memory element corresponding to instruction fetch
In, and be temporarily stored in the high-speed memory in this fpga chip, after digital independent to be read completes, it is judged that treating of reading
Read in data and whether there is fail data.
Step S223, when there is fail data in data to be read, uses non-failure-data recovery in data to be read
Fail data, and according to correcting and eleting codes, the fail data after non-fail data and recovery is recombinated；
In data to be read, there is fail data, and the quantity of this fail data less than preset value time, correcting and eleting codes based on
Data redundancy function, by failure-data recovery fail data non-in data to be read, after recovering fail data, is deleted according to entangling
Data redundancy function in Ma is from storage restructuring direction from small to large, address, by the failure number after non-fail data and recovery
According to being reduced into whole segment data.Wherein, this preset value is the integer less than the fragment verifying data in these data to be read, as this is treated
The fragment verifying data in reading data is K, then this preset value is the integer less than K.
It should be noted that when the quantity of this fail data is more than or equal to preset value, correcting and eleting codes cannot be based on number
According to redundancy feature by failure-data recovery fail data non-in data to be read, therefore these data to be read cannot normally be read
Take.
Data to be read, when there is not fail data in data to be read, are carried out heavily by step S224 according to correcting and eleting codes
Group.
When there is not fail data in data to be read, according to the data redundancy function in correcting and eleting codes from storage address from
Little to big restructuring direction, data convert to be read is become whole segment data.
The data to be read of storage in each memory element that this enforcement is corresponding by being successively read data read command,
After digital independent to be read completes, it is judged that whether the data to be read of reading exist fail data, deposits in data to be read
When fail data, use non-failure-data recovery fail data in data to be read, and according to correcting and eleting codes to non-fail data
And recover after fail data recombinate, when there is not fail data in data to be read, according to correcting and eleting codes to continuing
Fetch data and recombinate so that the data of inefficacy the most still can normally read, thus ensured the safety of data.
The present invention further provides a kind of data server.
High-level schematic functional block diagram with reference to the first embodiment that Fig. 6, Fig. 6 are data server of the present invention.
In the present embodiment, described data server includes: the first memory module 110, fractionation module 120 and the second storage
Module 130.
First data, for when data server receives the first data, are stored in by described first memory module 110
In fpga chip；
In the present embodiment, correcting and eleting codes is stored in fpga chip, and this fpga chip is applied to data storage server
In, separate with the CPU in data server and memorizer.The first memory module 110 in data server receives
During the first data write to outside, the first data received are temporarily stored in the high speed of fpga chip by this data server
In memorizer.Wherein, this data server includes PC end, smart mobile phone, intelligent television, panel computer；This high-speed memory bag
Include solid state hard disc (Solid State Disk, SSD).
Described fractionation module 120, for after the first data receiver completes, calls the correcting and eleting codes meter of storage in fpga chip
Calculate the verification data of the first data of storage in fpga chip, and calculate the first data and the check number of storage in fpga chip
According to stored ratio；
Determine that these first data receive in the first memory module 110, and storage completely is to the height of this fpga chip
After in speed memorizer, the fractionation module 120 in this data server calls the correcting and eleting codes of storage in this fpga chip, entangles according to this
The algorithm deleting code calculates the verification data being temporarily stored in the first data in this high-speed memory, and calculates in this high-speed memory
First data and the stored ratio of these verification data.Such as, the first data of totally 3 bytes store the height of fpga chip completely
After in speed memorizer, this PC end calls the correcting and eleting codes of storage in fpga chip and calculates the verification data of these the first data is 1 byte,
Then calculating the stored ratio of the first data and these verification data in this high-speed memory is 3:1.Wherein, these verification data are will
These first data obtain character string after carrying out check code, and when part loss of data in these first data, correcting and eleting codes passes through
The data do not lost in these verification data and these first data recover the data of the loss in these first data.
Described second memory module 130, for split according to stored ratio storage in fpga chip the first data and
Verification data obtain multiple second data, and the second data are respectively stored in each memory element of memorizer.
When splitting module 120 and determining these first data with the stored ratio verifying data, the second memory module 130 basis
This stored ratio splits these first data and verification data obtain multiple second data, and this data server is from the storage of local terminal
Device distributes the to be stored unit consistent with this second data bulk, and the storage size of each unit to be stored with should
The byte-sized of the second data matches, and these second data is respectively stored in each unit to be stored of memorizer.Wherein,
Each unit to be stored stores second data only.Such as, the stored ratio in the first data Yu these verification data is 3:1
After, these first data are split into 3 data slots, each data slot is 1 byte, in conjunction with the verification data of a byte
Obtaining 4 one byte the second data, this PC end distributes 4 memory element from the memorizer of local terminal, these 4 memory element
Memory space be a byte, the second data of these 4 bytes are respectively stored in 4 memory element.
It should be noted that when these verification data are split into M fragment, and these first data are split into K fragment, should
The total internal memory Y shared by M fragment K/mono-equal to shared total internal memory X of this K fragment, i.e. Y=X*1/K.
When the present embodiment receives the first data by the first memory module 110 in data server, by the first number
According to being stored in fpga chip, after the first data receiver completes, split module 120 and call the correcting and eleting codes of storage in fpga chip
Calculate the verification data of the first data of storage in fpga chip, and calculate the first data and the verification of storage in fpga chip
The stored ratio of data, the second memory module 130 splits the first data and the school of storage in fpga chip according to stored ratio
Test data and obtain multiple second data, and the second data are respectively stored in each memory element of memorizer.Delete owing to entangling
Code is stored in fpga chip, when data server receives the first data, these first data is temporarily stored in fpga chip
In, and call this fpga chip storage correcting and eleting codes calculate check number corresponding to these the first data according to this and these first data with should
The stored ratio of verification data, obtains multiple these first data and this verification data are carried out fractionation according to this stored ratio
After second data, these second data are respectively stored in each memory element of memorizer, hence in so that correcting and eleting codes is to data
The calculating of fractionation, the verification determination of data and data and the stored ratio of verification data all carry out in fpga chip, and
Memorizer is only responsible for the data after distribution memory element stores this fractionation and verifies data, thus reduces correcting and eleting codes pair
Taking of memorizer running space, improves the data storage capacities of memorizer, and then improves the computational efficiency of correcting and eleting codes.
Further, based on first embodiment, the second embodiment of data server of the present invention is proposed, at the present embodiment
In, with reference to Fig. 7, described second memory module 130 include call unit the 131, first judging unit 132, transmitting element 133 and
Memory element 134.
Described call unit 131, for calling each the second data successively, and stores corresponding memory element；
In the present embodiment, distribute consistent with this second data bulk from the memorizer of local terminal at data server,
And after the unit to be stored that matches of the byte-sized of storage size and these the second data, call unit 131 calls this and entangles
Deleting code and send preparation message to this unit to be stored, each preparation message includes that each unit needs to be stored store
Target the second data, after this unit to be stored receives this preparation message, generate according to this preparation message and prepare daily record, at this
After the preparation daily record of unit to be stored, send response message to this fpga chip, when this FPGA receives this response message, adjust
Send storage message with this correcting and eleting codes to this unit to be stored, indicate the write of this unit to be stored to prepare a target in daily record
Second data.Wherein, this preparation daily record is saved in unit to be stored, needs storage for temporarily storing this unit to be stored
One target the second data.
It should be noted that before in the unit to be stored that each second data are stored successively correspondence, to each
Second data distribute a storage address, and the mode increased successively according to number of addresses stores ground to this each the second data distribution
Location.Such as, the first data are split into the second data a, the second data b, the second data c and the second data d, by this second
Before data a, the second data b, the second data c and the second data d store in corresponding unit to be stored successively, according to ground
These second data a of the mode that location number increases successively, the second data b, the second data c and the second data d distribution storage address, point
It is not 0001,0010,0011,0100.
Described first judging unit 132, for when calling the second data every time, it is judged that the second data pair to be stored
Whether the memory element answered there is storage fault；
When call unit 131 stores the second data every time, the first judging unit 132 judges second number to be stored with this
According to corresponding unit to be stored whether feedback response message, if receive the response message of unit to be stored feedback, it is determined that
There is not storage fault in this unit to be stored, if do not receive the response message of band memory element feedback, it is determined that this waits to deposit
There is storage fault in storage unit.
Described transmitting element 133, if for the memory element that the second data to be stored are corresponding storage fault occurring, then to
The memory element transmission interrupt message that second data are corresponding, the memory element corresponding for the second data stops according to interrupt message
Store the second data；
When the first judging unit 132 determines that storage fault occurs in this unit to be stored, transmitting element 133 calls this and entangles and delete
Code sends interrupt message to this unit to be stored, and this unit to be stored is deleted according to this interrupt message and prepared daily record, interrupts this
The storage of target the second data, these target second data and etc. to be stored, if this memory element being detected in Preset Time
Storage fault recovery, then store in this unit to be stored by these target second data, if being not detected by this in Preset Time
The storage fault recovery of memory element, then this data server is redistributed out and this target the second number from the memorizer of local terminal
According to the unit to be stored of coupling, these target second data are stored in this unit to be stored.
, if there is not storage fault, then for the memory element that the second data to be stored are corresponding in described memory element 134
The second data called are stored in the memory element of correspondence.
When the first judging unit 132 determines that fault does not occurs storing in this unit to be stored, memory element 134 will be called
Second data store in the memory element of correspondence.
The present embodiment is by calling each the second data successively, and stores corresponding memory element, is calling every time
During the second data, it is judged that whether memory element corresponding to the second data to be stored storage fault occurs, the most then to the second number
Send interrupt message according to corresponding memory element, stop storage for memory element corresponding to the second data according to interrupt message
Two data, if it is not, then store the second data called in the memory element of correspondence.Owing to each storage of memorizer is to single
Unit is the most all likely to occur storage fault during storage the second data, therefore detects each of this memorizer by the moment
Memory element, it is to avoid during storing these second data, sends storage disorder, causes loss of data, thus ensure data
Safety.
Further, based on first embodiment, the 3rd embodiment of data server of the present invention is proposed, at the present embodiment
In, with reference to Fig. 8, described second memory module 130 includes determining unit 135, split cells 136.
Described determine unit 135, for determining in fpga chip that the first of the first data of storage tears open according to stored ratio
Component and the second fractionation amount of verification data；
In the present embodiment, determining that unit 135 determines that these first data are M:K with the stored ratio of these verification data
After, determining that the first fractionation amount of these the first data is M, the second fractionation amount of these verification data is K.
Described split cells 136, for splitting the first data stored in fpga chip according to the first fractionation amount, and according to
Second fractionation amount split verification data, and will split after fpga chip in storage the first data with split after verification data
As the second data.
These first data are split into M fragment according to this first fractionation amount M by split cells 136, according to this second fractionation
These verification data are split into K fragment by amount K, thus constitute M+K the second data.
The present embodiment by determine in fpga chip according to stored ratio the first data of storage the first fractionation amount and
Second fractionation amount of verification data, splits the first data of storage in fpga chip according to the first fractionation amount, and tears open according to second
Component splits verification data, and in the fpga chip after splitting the first data of storage with split after verification data as the
Two data.After data a bit of after whole segment data being split according to certain stored ratio due to correcting and eleting codes, the most conveniently deposit
The reservoir storage to the data after this fractionation, and the problem cannot recovered after avoiding the occurrence of the data failure in memorizer.
Further, based on first embodiment, the 4th embodiment of data server of the present invention is proposed, at the present embodiment
In, with reference to Fig. 9, described data server also includes: calling module 210, recombination module 220.
Described calling module 210, for when data server receives data read command, according to data read command
Call the correcting and eleting codes in fpga chip；
Described recombination module 220, deposits for reading in each memory element that instruction is corresponding according to correcting and eleting codes recombination data
The data to be read of storage.
In the present embodiment, when data server receives data read command, such as, receive at data server
During the data read command that client sends, calling module 210 calls the correcting and eleting codes of storage, recombination module in this fpga chip
220 according to the data redundancy function in this correcting and eleting codes from storage restructuring direction from small to large, address, by data convert to be read
Become whole segment data.Wherein, this data redundancy function includes carrying out splitting into multiple fragment according to preset rules by data, and can
Data before reassembling into according to the plurality of fragment of this preset rules.
The present embodiment is by when data server receives data read command, calling FPGA according to data read command
Correcting and eleting codes in chip, reads the peek of continuing of storage in each memory element that instruction is corresponding according to correcting and eleting codes recombination data
According to, by correcting and eleting codes, data to be read are recombinated so that these data to be read can normally be read, and improves memorizer
Fault-tolerant ability.
Further, based on the 4th embodiment, the 5th embodiment of data server of the present invention is proposed, at the present embodiment
In, with reference to Figure 10, described recombination module 220 include reading unit the 221, second judge module the 222, first recomposition unit 223 with
And second recomposition unit 224.
Described reading unit 221, for being successively read in each memory element that data read command is corresponding treating of storage
Read data；
Described second judge module 222, for after digital independent to be read completes, it is judged that in the data to be read of reading
Whether there is fail data；
In the present embodiment, after calling the correcting and eleting codes in fpga chip according to data read command, reading unit 221 should
The data to be read that correcting and eleting codes stores in each memory element corresponding with this data read command send data call instruction,
Locally stored data to be read are sent to by each memory element corresponding with this data read command according to this call instruction
In this fpga chip, and it is temporarily stored in the high-speed memory in this fpga chip, after digital independent to be read completes, the
Two judge modules 222 judge whether there is fail data in the data to be read read.
Described first recomposition unit 223, in time there is fail data in data to be read, uses in data to be read
Non-failure-data recovery fail data, and according to correcting and eleting codes, the fail data after non-fail data and recovery is recombinated；
Determine at the second judge module 222 and data to be read exist fail data, and the quantity of this fail data is less than
During preset value, correcting and eleting codes, is recovering by failure-data recovery fail data non-in data to be read based on data redundancy function
After fail data, according to the data redundancy function in correcting and eleting codes from storage restructuring direction from small to large, address, by non-failure number
Fail data according to this and after recovery is reduced into whole segment data.Wherein, this preset value is less than check number in these data to be read
According to the integer of fragment, the fragment verifying data in data as to be read in this is K, then this preset value is the integer less than K.
It should be noted that when the quantity of this fail data is more than or equal to preset value, correcting and eleting codes cannot be based on number
According to redundancy feature by failure-data recovery fail data non-in data to be read, therefore these data to be read cannot normally be read
Take.
Described second recomposition unit 224, in time there is not fail data in data to be read, treats according to correcting and eleting codes
Read data to recombinate.
When there is not fail data in the second judge module 222 data to be read, the second recomposition unit 224 is deleted according to entangling
Data convert to be read, from storage restructuring direction from small to large, address, is become whole segment data by the data redundancy function in Ma.
The data to be read of storage in each memory element that this enforcement is corresponding by being successively read data read command,
After digital independent to be read completes, it is judged that whether the data to be read of reading exist fail data, deposits in data to be read
When fail data, use non-failure-data recovery fail data in data to be read, and according to correcting and eleting codes to non-fail data
And recover after fail data recombinate, when there is not fail data in data to be read, according to correcting and eleting codes to continuing
Fetch data and recombinate so that the data of inefficacy the most still can normally read, thus ensured the safety of data.
These are only the preferred embodiments of the present invention, not thereby limit the scope of the claims of the present invention, every utilize this
Equivalent structure or equivalence flow process that bright description and accompanying drawing content are made convert, or are directly or indirectly used in other relevant skills
Art field, is the most in like manner included in the scope of patent protection of the present invention.
Claims (10)
1. a data storage control method, it is characterised in that described data storage control method comprises the following steps:
When data server receives the first data, described first data are stored in fpga chip；
After described first data receiver completes, call during the correcting and eleting codes of storage calculates described fpga chip in fpga chip and store
The verification data of the first data, and calculate the first data and the storage of described verification data of storage in described fpga chip
Ratio；
Split, according to described stored ratio, the first data stored in described fpga chip and described verification data obtain multiple
Second data, and described second data are respectively stored in each memory element of memorizer.
2. data storage control method as claimed in claim 1, it is characterised in that described described second data are stored
Step in each memory element of reservoir includes:
Call each described second data successively, and store corresponding memory element；
When calling described second data every time, it is judged that whether the memory element that described second data to be stored are corresponding occurs
Storage fault；
The most then send interrupt message, for described corresponding the depositing of second data to the memory element that described second data are corresponding
Storage unit stops storing described second data according to described interrupt message；
If it is not, then described second data called are stored in the memory element of correspondence.
3. data storage control method as claimed in claim 1, it is characterised in that described split institute according to described stored ratio
State in fpga chip the first data of storage and step that described verification data obtain the second data include:
The first fractionation amount of the first data of storage in described fpga chip and described verification is determined according to described stored ratio
Second fractionation amount of data；
Split the first data of storage in described fpga chip according to described first fractionation amount, and tear open according to described second fractionation amount
In point described verification data, and the described fpga chip after splitting the first data of storage with split after described verification data
As described second data.
4. data storage control method as claimed in claim 1, it is characterised in that described data storage control method also wraps
Include:
When described data server receives data read command, call described fpga chip according to described data read command
In correcting and eleting codes；
According to the peek of continuing of storage in each described memory element that the described correcting and eleting codes described data read command of restructuring is corresponding
According to.
5. data storage control method as claimed in claim 4, it is characterised in that described according to the restructuring of described correcting and eleting codes
In each described memory element that data read command is corresponding, the step of the data to be read of storage includes:
It is successively read in each described memory element that described data read command is corresponding the data to be read of storage；
After described digital independent to be read completes, it is judged that whether the data described to be read of reading exist fail data；
When there is fail data in described data to be read, use in described data to be read and lose described in non-failure-data recovery
Effect data, and according to described correcting and eleting codes, the described fail data after described non-fail data and recovery is recombinated；
When there is not fail data in described data to be read, according to described correcting and eleting codes, described data to be read are carried out heavily
Group.
6. a data server, it is characterised in that described data server includes:
Described first data, for when data server receives the first data, are stored in FPGA core by the first memory module
In sheet；
Split module, for after described first data receiver completes, call the correcting and eleting codes of storage in fpga chip and calculate described
The verification data of the first data of storage in fpga chip, and calculate the first data of storage in described fpga chip and described
The stored ratio of verification data；
Second memory module, for splitting the first data of storage in described fpga chip and described according to described stored ratio
Verification data obtain multiple second data, and described second data are respectively stored in each memory element of memorizer.
7. data server as claimed in claim 6, it is characterised in that described second memory module includes:
Call unit, for calling each described second data successively, and stores corresponding memory element；
First judging unit, for when calling described second data every time, it is judged that described second data to be stored are corresponding
Memory element whether storage fault occurs；
, if there is storage fault for the memory element that described second data to be stored are corresponding, then to described the in transmitting element
The memory element transmission interrupt message that two data are corresponding, the memory element corresponding for described second data disappears according to described interruption
Breath stops storing described second data；
Memory element, if there is not storage fault for the memory element that described second data to be stored are corresponding, then will call
Described second data store correspondence memory element in.
8. data server as claimed in claim 6, it is characterised in that described second memory module also includes:
Determine unit, for determining the first fractionation amount of the first data of storage in described fpga chip according to described stored ratio
And the second fractionation amount of described verification data；
Split cells, for splitting the first data of storage in described fpga chip according to described first fractionation amount, and according to institute
State second fractionation amount split described verification data, and will split after described fpga chip in storage the first data with split after
Described verification data as described second data.
9. data server as claimed in claim 6, it is characterised in that described data server also includes:
Calling module, for when described data server receives data read command, adjusts according to described data read command
With the correcting and eleting codes in described fpga chip；
Recombination module, deposits in each described memory element that described data read command of recombinating according to described correcting and eleting codes is corresponding
The data to be read of storage.
10. data server as claimed in claim 9, it is characterised in that described recombination module includes:
Read unit, for being successively read in each described memory element that described data read command is corresponding the to be read of storage
Data；
Second judge module, for after described digital independent to be read completes, it is judged that in the data described to be read of reading be
No there is fail data；
First recomposition unit, in time there is fail data in described data to be read, uses in described data to be read not
Fail data described in failure-data recovery, and according to described correcting and eleting codes to the described inefficacy after described non-fail data and recovery
Data are recombinated；
Second recomposition unit, in time there is not fail data in described data to be read, according to described correcting and eleting codes to described
Data to be read are recombinated.
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| CN106201766B (en) | 2018-03-20 |
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