CN106160487B - Control circuit, switch mode power and corresponding control method - Google Patents

Control circuit, switch mode power and corresponding control method Download PDF

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Publication number
CN106160487B
CN106160487B CN201510862615.XA CN201510862615A CN106160487B CN 106160487 B CN106160487 B CN 106160487B CN 201510862615 A CN201510862615 A CN 201510862615A CN 106160487 B CN106160487 B CN 106160487B
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signal
delay
switch
relevant
current
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CN106160487A (en
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G·格里蒂
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STMicroelectronics SRL
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STMicroelectronics SRL
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • H02M3/33523—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with galvanic isolation between input and output of both the power stage and the feedback loop
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0016—Control circuits providing compensation of output voltage deviations using feedforward of disturbance parameters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0016—Control circuits providing compensation of output voltage deviations using feedforward of disturbance parameters
    • H02M1/0022—Control circuits providing compensation of output voltage deviations using feedforward of disturbance parameters the disturbance parameters being input voltage fluctuations
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

One kind is for receiving input quantity (Vin) switching regulator current converter switch (M) control circuit (15), including with armature winding (Lp) transformer and generate sensing signal (V relevant to the electric current in armature windingp) sensor element (19).Control circuit has comparator stage (25), the comparator stage (25) is configured as comparing comparison signal (Vcs) relevant with sensing signal with reference signal (VcsREF), and the opening signal (R) for being used for switch is generated, it switchs with the propagation delay (T relative to opening signalD) switching.Comparator stage (25) has comparator element (26) and delay compensating circuit (101).Delay compensating circuit (101) is configurable to generate and input quantity (Vin) and propagation delay (TD) relevant thermal compensation signal (ICOMP).Comparator element (26) generates the opening signal with lead relevant to input quantity and propagation delay.

Description

Control circuit, switch mode power and corresponding control method
Technical field
The present invention relates to the electric current conversions of the current control with primary (primary) winding side and propagation delay compensation Device.Specifically, this disclosure relates to which the converter in the power supply for solid luminescent (SSL) device can be used in, and more More particularly to the device for the lamp for containing light emitting diode (LED) array.
Background technique
It the use of driving power under the line of the light emitting device of LED include control circuit and for being maintained at control circuit and load (LED) transformer of safe insulation between.In these circuits, it is often desirable to use not utilized to obtain in secondary windings side In the case where the feed circuit of signal, the average anode current for driving LED is adjusted.In this way, in the primary side of transformer, no Current measuring element, reference voltage source or failure amplifier are needed, does not also need to be arranged in just for passing to fault-signal The photo-coupler of the control circuit of grade side.Usually, also it is desirable to which (Hi-PF is higher than 0.9) to meet current harmonics high power factor Transmitting limitation (according to European standard IEC 61000-3-2 and Nippon Standard JEITA-MITI).
In order to obtain above-mentioned characteristic, it is known that the Hi-PF flyback switching converter for example manufactured according to the circuit diagram of Fig. 1 (see also C.Adragna's " Primary-Controlled High-PF Flyback Converters Deliver Constant Dc Output Current " Europe Power Electronics Conference, Sept.2011, reference It obtains more details).
Fig. 1 show include bridge rectifier 2 and flyback converter 3 power supply 1.
There are two input terminal 10a, 10b for the tool of bridge rectifier 2, are designed to frequency fLReceive alternating supply voltage Vac, and input voltage V is providedinTwo output terminals of (θ), wherein θ is supply voltage VacPhase.Bridge rectifier 2 Output terminal is connected respectively to the first reference potential line (the first ground connection 12) and input node 13.
Flyback converter 3 includes filter condenser Cin, it is connected between input node 13 and the first ground connection 12 and grasps As high frequency smoothing filter；Including armature winding Lp, secondary windings LsAnd auxiliary winding LauxTransformer 4；Control module 15；Including the first voltage grading resistor RaWith the second voltage grading resistor RbResitstance voltage divider 16；The power formed by power transistor Switch M, such as MOSFET；With resistance RauxAuxiliary sense resistor 21；With resistance RsPrimary sense resistor 19； And clamp circuit 20.
Specifically, the armature winding L of transformer 4pWith the first terminal 4a and Second terminal for being connected to input node 13 4b.Secondary windings LsWith first terminal 4c and Second terminal 4d, the latter is connected to the second reference potential line (the second ground connection 17). Auxiliary winding LauxWith the first terminal 4e and Second terminal 4f for being connected to the first ground connection 12.As illustrated in fig. 1, primary, secondary With auxiliary winding Lp、Ls、LauxIt is coupled with positive terminal 4b, 4c and 4f,.
First voltage grading resistor RaIt is connected between input node 13 and intermediate node 14.Second resistor RbWith connection To intermediate terminal 14 first terminal and be connected to the Second terminal of the first ground connection 12.Intermediate node 14 is coupled to control module 15 First input end MULT and the intrinsic standoff ratio K of resitstance voltage divider 16 is passed through according to equation (1)p=Rb/(Ra+Rb) provide With input voltage Vin(θ) proportional first voltage signal A (θ):
A (θ)=KpVin,pksinθ (1)
Wherein
Auxiliary sense resistor 21 is connected to auxiliary winding LauxSecond terminal 4f and control module 15 the second input terminal Between sub- ZCD.Primary sense resistor 19 is connected between the source terminal of power switch M and the first ground connection 12.In addition, power The source terminal of switch M is connected to the third input terminal CS of control module 15 and provides it sensing voltage Vcs (t, θ), When power transistor M is connected (that is, in armature winding LpMagnetization during) be proportional to armature winding LpIn electric current.In fact, When power switch M is connected, primary sense resistor 19 is detected in armature winding LpThe electric current I of middle flowingp(t,θ)。
Transistor M, which also has, is connected to armature winding LpSecond terminal 4b its source terminal and be connected to control mould Its gate terminal of the output terminal GD of block 15.
Clamp circuit 20 is disposed in armature winding LpThe first and second terminal 4a, 4b between, for limit for example by Due to voltage spikes on the drain terminal of switch M caused by parasitic inductance.
In secondary windings LsSide, flyback converter 3 include output diode D and output capacitor Cout.Output capacitor CoutE.g. electrolytic capacitor type and there is the positive plate for being coupled to first lead-out terminal 22 and second output terminal 23 and negative Pole plate, first lead-out terminal 22 and second output terminal 23 are in turn coupled to load 18.Second output terminal 23 is coupled to second Ground connection 17.Output diode D, which has, is connected to secondary windings LsFirst terminal 4c its anode and have be connected to first Its cathode of face terminals 22.Across output capacitor CoutVoltage therefore be supplied to load 18 output voltage Vout, this In load 18 be a series of diode, such as LED.
Control module 15 includes reference current source level 24 and comparator stage 25.
Specifically, reference current source level 24 (being described in detail in patent application US 2013/0088897) has connection To the first input of the first input end MULT of control module 15, be connected to the forth terminal CT of control module 15 second is defeated Enter, and generating can be according to supply voltage VacPhase theta variation reference voltage VcsREFThe output 27 of (θ), such as hereinafter in detail Carefully explain.
Comparator stage 25 includes the latch flip-flops 28 of comparator 26, Set-Reset type.Driver 30, starting electricity Road 32, the logic gate 34 of OR type and zero-crossing detector (ZCD) 36.
There is comparator 26 the reversed of the output 27 for being connected to reference current source level 24 to input and be connected to control module 15 Third input terminal CS non-return input.
Reset the input R, output Q that the output of comparator 26 is connected to trigger 28 are connected to the input of driver 30, Output terminal GD of the input coupling of driver 30 to control module 15.The output Q of defeated trigger 28 further passes through starting electricity Road 32 is connected to the set input of defeated trigger 28.Specifically, the input of start-up circuit 32 is connected to the output Q of trigger 28, And the output of start-up circuit 32 is connected to the first input of the first logic gate 34.First logic gate 34, which has, is connected to ZCD electricity The second of first output on road 36 inputs and is coupled to the output of the set input of trigger 28.ZCD circuit 36, which has, to be connected to The input of second input terminal ZCD of control module 15.
Reference current source level 24 includes voltage-controlled current source 40, has the control terminal for being connected to intermediate node 14 Son；Divider 41 is connected between node 14 and the fourth node CT of control block 15；First switch 42；Second switch 43； And the 4th resistor RT。
Current source 40, which has, to be provided and input voltage Vin(θ) proportional electric current ICHThe output terminal 44 of (θ).First opens It closes between the output terminal 44 and the first ground connection 12 that 42 are connected to current source 40.Second switch 43 is connected to the output of current source 40 Between terminal 44 and the forth terminal CT of control module 15.4th resistor RTBe coupled in the forth terminal CT of control module 15 with Between first ground connection 12 and generate second voltage signal B (θ).
Phase signal FWN and the FW branch that switch 42,43 passes through the logical type (equal and reverse phase) generated by ZCD circuit 36 Match.The forth terminal CT of control module 15 is connected to the external capacitor C of high levelT, select high level so that second voltage signal AC compounent B (θ) (be equal to supply voltage VacFrequency twice of frequency at) at least with first approximation compared to direct current Component B0It is negligible.The condition be usually satisfied also in that in Hi-PF flyback converter control loop have be far below Supply voltage VacFrequency bandwidth.
The C.Adragna that the operation of the power supply 1 of Fig. 1 is described hereinafter with reference to Fig. 2 and Fig. 3, and is mentioned above Paper in be described in detail.
It should be noted that in flyback converter 3, when being operated under the conditions of Hi-PF, filter condenser CinNot as energy Library operation is measured, so that input voltage VinIt is rectified sine (Vin (θ)=Vin,pk|sinθ|withθ∈(0,π))。
In these conditions, according to equation (1), voltage A (θ) and input voltage Vin(θ) is proportional.In addition, as described above, Because can be by second voltage signal B (θ) relative to D. C. value B0Approximation, so the reference voltage in the output of divider 41 VcsREF(θ) is
Wherein KDIt is proportionality constant, equal to the gain of divider 41.Reference voltage VcsREF(θ) is therefore sinusoidal voltage, Value depends on supply voltage V based on equation (1)acVirtual value.
Comparator 26 is by reference voltage VcsREF(θ) and sensing voltage Vcs (t, θ) compare, sensing voltage Vcs (t, θ) with Armature winding LpIn and (when switch M is connected) electric current I in switch Mp(t, θ) is proportional.
It is assumed that switch M first closure, then pass through armature winding LpElectric current such as sensing voltage Vcs (t, θ) equally initial increase Add.When the latter reaches reference voltage VcsREFWhen (θ), comparator 26 switches and resets the output of trigger 28.Therefore, power switch M is disconnected.In this way, the first voltage signal A (θ) with rectified sinusoidal shape determines armature winding L as mentionedpIn Electric current IpThe peak value of (t, θ), therefore by rectified sinusoidal institute's envelope.
When switch M is disconnected, it is stored in armature winding LpIn energy secondary windings L is passed to by magnetic couplings, and And then it is transmitted to output capacitor CoutWith load 18, until secondary windings LsCompletely by demagnetization.
As long as after the disconnection of switch M and electric current is in secondary windings LsMiddle flowing, the voltage of the drain terminal of switch M Equal to Vin(θ)+VR, wherein VRIt is so-called reflected voltage, is equal to nVout, wherein n is equal to the armature winding L of transformer 4p's The number of turns and secondary windings LsThe number of turns between ratio.
In secondary windings LsDemagnetization after, diode D is disconnected and the drain terminal of switch M becomes floating, and is led to It crosses by parasitic capacitance and armature winding LpThe caused damped oscillation of oscillation, it is intended to it is assumed that voltage is equal to input voltage Vin(θ) Instantaneous value.However, the quick voltage drop on the drain terminal of the switch M of the demagnetization of transformer is followed to be coupled to control Second input terminal ZCD of module 15, and pass through auxiliary winding L in turnauxWith 3rd resistor device RauxIt is coupled to ZCD circuit 36, Such as it is described more fully below.
Whenever the failing edge of the voltage on the second input terminal ZCD that ZCD circuit 36 detects control module 15 is reduced to Threshold value (the V in Fig. 2ZCDt) under when, ZCD circuit 36 generates pulse S in the output that it is connected to comparator 26.The pulse is compeled Make to 28 set of trigger, the output of trigger 28 switches, and connects power switch M and causes the beginning of new switch cycles.
Start-up circuit 32 is made it possible to when flyback transformer 3 is connected by logic gate 34 (that is, when there are no signals to go out When on the second input terminal ZCD of present control module 15), start first switch circulation, and the second of control module 15 In the case that the signal of input terminal ZCD is lost for some reason, flyback converter 3 is further prevented to keep blocking.
ZCD circuit 36 similarly generates phase signal FW and FWN, is provided to (the figure as being directed to signal FW of switch 42,43 2 is illustrated).Specifically, phase signal FW is high during the demagnetization of transformer, and for generating second voltage signal B The right value of (θ), to adjust the desired value of average anode current, as shown in the paper in the C.Adragna of reference.
In the circuit in fig. 1, when switch M is connected, the second input terminal ZCD of control module 15 is (by controller, not Diagram) it is connected to the first ground connection 12.Therefore, the voltage across auxiliary sense resistor 21 is equal to auxiliary winding LauxOn auxiliary electricity Press Vaux.In this period, the voltage drop in primary sense resistor 19 and on switch M is negligible, and input voltage VinSubstantially On be applied in armature winding L completelypOn, between terminal 4a and 4b.Therefore, boost voltage VauxWith auxiliary sense resistor Electric current and input voltage V in 21inIt is proportional.
When switch M is disconnected, the second input terminal ZCD of control module 15 is disconnected from the first ground connection 12 to be coupled, and the The voltage V of two input terminal ZCDZCDAccording to secondary windings LsWith auxiliary winding LauxBetween the associated ratio system of turn ratio Number is to follow output voltage VoutCurve graph.In secondary windings LsDemagnetization after, specifically, on the second input terminal ZCD Voltage tend to rapid decrease, as auxiliary sense resistor 21 in electric current, as being illustrated in detail in Fig. 2.
The example of the signal generated in flyback converter 3 is shown in Fig. 2, wherein following input voltage VinMode Some amount have linear type stretch (rectilinear stretches), it is assumed that switching frequency fs(order of magnitude of kHz) Significantly larger than input voltage VinFrequency fL(generally 50-60Hz).
Specifically, Fig. 2 shows following amounts:
Voltage V between the drain electrode and source terminal of switch MDS；
Voltage Vin,pkSin θ, wherein Vin,pkIt is input voltage VinPeak value；
Auxiliary winding LauxOn voltage Vaux；
Voltage V on second input terminal ZCD of control module 15ZCD；
Voltage VZCDThreshold value VZCDt, wherein ZCD circuit 36 generates the pulse for being provided to logic gate 34；
It is provided to set and reset pulse S, R of trigger 28；
The voltage V of connecting and disconnecting provided on the output terminal GD of control module 15 and driving switch MGD；
Sensing voltage Vcs (t, θ)；
Secondary windings LsIn electric current Is(t,θ)；And
Afterflow (freewheel) phase signal FW when the demagnetization of transformer 4 occurs.
In addition, Fig. 2 highlights the following period:
When switch M connect when and and then indication transformer 4 core magnetized cycle TON；
Cycle T when the core demagnetization of transformer 4FW；And
Cycle TR, that is, in the complete demagnetization of the core of depressor 4 and the connection of subsequent switch M (that is, the core of transformer 4 New magnetized beginning) between period for passing.
Therefore pass through T (θ)=TFW(θ)+TR+TONGive switch periods T.
Obtained electric current I is shown in Fig. 3p(t,θ),Is(t, θ), and corresponding peak Ipkp(θ),IpksThe correspondence of (θ) Envelope and armature winding LpIn electric current the average I recycled one by oneinThe curve of (θ).
For practicality purpose, flyback converter 3 is the type of quasi-resonance.In fact, although there is delay, transistor (being synchronized at the time of that is, becoming 0 with the electric current in secondary windings) synchronous at the time of the connection of M is with the complete demagnetization of transformer 4. On the contrary, theoretically the disconnection of transistor M is by detecting as armature winding LpIn electric current IpThreshold value (V provided by reachingcsREF (θ)/Rs) when determine.In addition, flyback converter 3 is Controlled in Current Mode and Based type, and specifically peak-current mode Control Cooling., it is noted once again that due in sense resistor RsIn and and then in armature winding LpThe peak envelope of the electric current of middle flowing It is sinusoidal, therefore obtains the power factor higher than 0.9.
Shown in the paper of C.Adragna as mentioned above, the direct current after the adjusting flowed in load 18 is defeated Electric current I outoutIt is given by the following equation
Wherein n is the armature winding L of transformer 4pThe number of turns and secondary windings LsThe number of turns between ratio, KDIt is partial pressure The gain (referring to equation (2)) of device 41 and GMIt is the mutual conductance of current source 40.Therefore, be used only in transformer 4 it is primary around Group LpIn the case where the Instantaneous Control scheme of upper available amount, average (mean) exports electric current IoutIdeally being only dependent upon can be with Such as n and R selected by usersExternal parameter or such as GM,RTAnd KDPreset parameter, and be not dependent on output voltage Vout Or input voltage VinOr switching frequency fs=1/T (θ).
However, in the circuit in fig. 1, due to propagation delay, so that reaching reference voltage at sensing voltage Vcs (t, θ) VcsREFWhen (θ), that is, the L in armature windingpElectric current Ip(t, θ) reaches the threshold value V providedcsREF(θ)/RsWhen, transistor M does not have Have and disconnect immediately, but remains up up to referred to as " total propagation delay TD" other a period of time, as shown in Figure 4.Tool Body, total propagation delay TDBy the disconnection of the switching delay of comparator 26, the propagation delay of driver 30 and power switch M The sum of lag characteristic provides.L in subsequent armature windingpElectric current be higher by than ideal value equal to the amount △ I in following equationP(θ)
And the average anode current I after therefore adjustingoutWith input voltage VinVirtual value and increase.
In order to compensate for input voltage VinThe increase of associated peak point current, it is and defeated on the market in available power supply Enter voltage VinProportional forward migration voltage is added in sensing voltage Vcs (t, θ), as illustrated in Figure 5.
Fig. 5 shows the flyback power supply 50 of the power supply 1 similar to Fig. 1.Therefore, the electricity with Fig. 1 of flyback power supply 50 The shared element of those of road figure element will not be repeated again descriptions thereof by as specified by identical appended drawing reference.
Flyback power supply 50 includes feedforward resistors 51, which has resistance RFFAnd it is connected to switch M's Between source terminal and the third input terminal CS of control module 15；And feedforward current source 52, generate feedforward current IFFAnd by It is being generated by ZCD circuit 36 and with the auxiliary current I that flows in auxiliary sense resistor 21auxProportional control electric current IZCDIt dominates, during the period of switch connection, control electric current IZCDIt is being generated by ZCD circuit 36 and with auxiliary sense The auxiliary current I flowed in resistor 21auxIt is proportional.For example, control electric current IZCDEqual to auxiliary current IauxAnd via current mirror Circuit evolving.
On the basis of the hypothesis, as previously mentioned, because in the connection cycle T of transistor MONPeriod controls mould Second input terminal ZCD of block 15 is connected to the first ground connection 12, therefore the auxiliary current flowed in auxiliary sense resistor 21 IauxWith control electric current IZCDFor
Wherein m is auxiliary winding LauxWith armature winding LpBetween turn ratio.
Feedforward current source IFFIt is current mirror, is generated and electric current I according to following relationshipZCDProportional electric current
IFF(θ)=KFFIZCD(θ)
Wherein KFFIt is the gain of current mirror.
Feedforward current IFFFeedforward resistors 51 are provided to, feedforward resistors 51 generate additional feedback voltage VFF.Setting RFF>>RS, it obtains:
Due to propagation delay, so that additional feedback voltage VFFEqual to voltage step size
△VCS(θ)=RS△IP(θ)=VFF(θ)
And it combines, is obtained to the resistance value R for obtaining compensating useful feedforward resistors with equation (4)FF:
In practice, the voltage of comparator 26 is applied to relative to the voltage V in primary sense resistor 19pIncrease by one Value, so that the switching of expected comparator 26, which increases, is equal to total propagation delay TDCertain time.In this way, when comparator 26 switches When, the electric current I that is flowed in primary sense resistor 19PLower than threshold value, and when power switch M is to postpone TDWhen disconnection, electric current IPDesired threshold value is had arrived at, as illustrated in Figure 6.
Then, if total propagation delay TDIt is constant, then as caused by total propagation delay with input voltage VinProportional By secondary windings LsThus the variation of the output electric current of offer can be compensated.However, if total propagation delay TDVariation, should Compensation is equally insufficient.
This is in the solid-state lighting device for obtaining the high accuracy of average anode current (value even lower than ± 3%) ever more important In be a problem, cannot realize high accuracy always using the compensation technique indicated in Fig. 5.
In addition, described power supply is used from different power transistor M according to the application and requirement of user.In the market Available power transistor M has similar static characteristic, especially similar saturation resistance RDS-on, but there is different open Characteristic is closed, switch time is especially different.Therefore, output electric current changes according to the power transistor used.This requires base The value of feedforward resistors 51 is modified and adapted to according to application and power switch in equation (7).However, this set is multiple It is miscellaneous and at high cost.
Summary of the invention
It is an object of the invention to improve the current converter of described type, so that overcome its limitation, in particular so that It is generated and supply voltage VacVariation and propagation delay the unrelated average anode current of both variations.
According to the present invention, provide for for the control circuit of switch of switching regulator current converter, switch mode power, And corresponding control method, as limited in claim 1,11 and 12.
In practice, the control circuit of the disclosure based on providing the principle of feedforward current, the feedforward current not only with input Voltage VinIt is proportional, and with total propagation delay TDIt is proportional.Specifically, the power supply of the disclosure, which provides, has compensation electric current ICOMP Feedforward resistors 51:
ICOMP(θ,TD)=KFF0Vin(θ)TD (8)
Wherein KFFOFor constant.
For doing so, due to propagation delay △ VCS(θ)=RS△IP(θ) and equation (4) are considered, so that positive offset RFFIFF(θ,TD) it is equal to sensing voltage step-length, this makes:
Equation (9) shows input voltage VinWith total propagation delay TDThe two can be by using with resistance RFFFeedforward Resistor 51 is compensated:
Detailed description of the invention
For a better understanding of the present invention, preferred implementation now is described in reference to the drawings only in a manner of non-limiting example Example, in which:
- Fig. 1 shows the circuit diagram of known switch mode power；
- Fig. 2 to Fig. 4 shows the time diagram of the signal generated in the switch mode power illustrated in Fig. 1；
- Fig. 5 shows the circuit diagram of another switch mode power；
- Fig. 6 shows the same amount of time diagram of the circuit of Fig. 5；
- Fig. 7 shows the simplified electrical circuit diagram of the embodiment of the switch mode power of the disclosure；
- Fig. 7 A shows the generator block used in the circuit diagram of Fig. 7；And
- Fig. 8 shows the same amount of time diagram of the power supply of Fig. 7 and Fig. 7 A.
Specific embodiment
Fig. 7 shows the switch mode power 100 of the general structure of the power supply 50 with Fig. 4.Therefore, switch mode power 100 Shared element is specified by identical appended drawing reference and will be not further described with the circuit diagram of Fig. 4.
Switch mode power 100 includes the current source stage 101 being shown specifically in fig. 7, and current source stage 101 is received by ZCD electricity The control electric current I that road 36 providesZCDRespectively by logic gate 34 and comparator 26 (also called hereinafter duty cycle comparator 26) The set and reset signal S, R (also called hereinafter duty ratio set and reset signal S, R) of generation, and generate the electricity of compensation Flow ICOMP。
With reference to Fig. 7 A, current source stage 101 includes delay estimation block 102 and electric current source block 103.
Delay estimation block 102 includes the first current mirror generator 105, and the current mirror generator 105 is by control electric current IZCDControl It makes and is provided at output 110 and control electric current IZCDProportional the first (especially equal) mirror electric current ICH1；Auxiliary compares net Network 109；Estimate comparator 113；And the latch flip-flops 114 of set/reset type.
Assisting comparing cell 109 includes auxiliary current sense resistor 111, is coupled in the first current mirror generator 105 Output 110 and first ground connection 12 between and have resistance R1；And filter branch 112, it is connected in parallel to auxiliary current Sense resistor 111.
Filter branch 112 includes having resistance R in turnDFilter resistors 115, and have capacitor CDFilter Capacitor 116, they are connected in series together and define intermediate node 118.Filter resistors 115 are connected to the first electricity Between the output and intermediate node 118 for flowing mirror generator 105.Filter capacitor 116 is connected between node 118 and connects with first Between ground 12.Offset voltage source 117 for generating tens millivolts of variations is disposed in the first current mirror generator 105 Between output and the reversed input of estimation comparator 113.Estimate that comparator 113 further comprises being directly coupled to intermediate node 118 non-return input and the reset for being connected to latch flip-flops 114 input the output of R1.Latch flip-flops 114 into one It walks to have to receive and S1 is inputted by the set of the duty ratio of trigger 28 (Fig. 7) reset signal R generated and regulating switch M.It latches Device trigger 114 further has its output Q1 for being connected to electric current source block 103.
Electric current source block 103 includes the second current mirror generator 120, receives control electric current IZCDAnd it exports and control signal IZCDProportional the second (especially equal) mirror electric current ICH2；Control switch 121 is coupled in the second current mirror generator 120 Between output and control node 122；Discharge switch 123 is arranged between control node 122 and the first ground connection 12；Charging capacitor Device 125 has capacitor CTRAnd it is disposed between control node 122 and the first ground connection 12；Switch 126 is transmitted, control is coupled in Between node 122 and transmitting node 127；And holding capacitor device 128, there is capacitor CHAnd it is coupling in transmitting 127 He of node Between first ground connection 12.Charging capacitor 125, transmitting switch 126 and holding capacitor device 128 form tracking and keep type Memory component 130, as explained in more detail below.
Output node 127 is further coupled to the control input of compensating current element 131, and the output of compensating current element 131 mentions Supply the compensation electric current I of the feedforward resistors 51 of Fig. 7COMP.Electric current source block 103 is further received and is generated by the logic gate 34 of Fig. 7 And it is fed to the control input of transmitting switch 126, and the control input of discharge switch 123 is fed to by delay element 132 Set signal S.
The operation of the circuit of Fig. 7, Fig. 7 A is described below.
The reset signal R generated by duty cycle comparator 26 (Fig. 7) is when the sensing voltage in primary sense resistor 19 VcsReach reference value VcsREFWhen, by 114 set of latch flip-flops, latch flip-flops 114 are being equal to total propagation delay TD's It is estimated the reset of comparator 113 after estimated value, will be explained.
In fact, the first current mirror generator 105 is provided to auxiliary comparing cell 109 is equal to control electric current IZCDFirst Mirror electric current ICH1.By the resistance R for selecting resistor 111,1151、RDValue so that R1<<RD, and pass through selection filter electricity The capacitor C of container 116D, so that filter branches 112 form low-pass filtering under steady state conditions, a reactor with nsec constant Device, the electric current I provided by the first current mirror generator 105CH1Actually fully in the first auxiliary current sense resistor It is flowed in 111, so that the voltage on the output node 110 of the first current mirror generator 105 are as follows:
VR1(θ)=R1IZCD(θ)
On the contrary, filter branches 112 be supplied to estimation comparator 113 with the first mirror electric current ICH1Thus with control electric current IZCDThe relevant voltage value of length of delay.
In this way, auxiliary comparing cell 109 is supplied to estimation comparator 103 with signal relevant to instantaneous value and auxiliary current IauxPostpones signal so that work as auxiliary current Iaux(bending section of the curve of Fig. 8) is able to detect instantaneous value when decline.
Specifically, in view of the offset voltage generated by source 117, (the period t in the timing of Fig. 8 when switch M is disconnected0- t1), the reversed input of estimation comparator 113 is in higher potential than non-return input, and estimates the output of comparator 113 R1 is low.Switching frequency f is far below in view of itsFrequency fL, this behavior is in input voltage VinThe entire half period in repeat.
Once duty cycle comparator 26 switches and duty ratio reset signal R becomes height (moment t1), then estimate trigger 114 switchings, and its output signal Q1 is got higher.
In moment t2, when transistor M is disconnected (to be equal to total propagation delay TDDelay, as explained above), auxiliary Electric current IauxDecline such as controls electric current IZCDEqually, as indicated in the curve graph of Fig. 8, therefore the first mirror electric current ICH1Determine In the output 110 of one current mirror generator 105 sharply voltage decline, and it is thus determined that estimation comparator 113 switching, will Estimate that trigger 114 resets, the output Q1 of estimation trigger 114 is lower.
Then, estimate that there is the output Q1 of trigger 114 width to be equal to total propagation delay TDPulse and thus indicate prolong Estimation signal late, the parameter (pulse width) of delay estimation signal and total propagation delay TDIt is related.
The output Q1 of estimation trigger 114 controls the connecting and disconnecting of control switch 121.For accurately, one The output signal Q1 of denier estimation trigger 114 gets higher (moment t1), the sensing electricity in the reversed input of duty cycle comparator 26 Press VcsReach its threshold value (VcsREF) when, control switch 121 is closed and is equal to control electric current IZCDAnd it is raw by the second current mirror Grow up to be a useful person the second mirror electric current I of 120 generationsCH2Charging capacitor 125 is flowed to, (in this step, duty ratio is set to charge to it Position signal S is that low therefore discharge switch 123 and transmitting switch 126 disconnect).Control voltage V on charging capacitor 125CTRTherefore With control electric current IZCDWith auxiliary current IauxProportionally increase.Once the output signal Q1 of estimation trigger 114 is switched to low (moment t2), control switch 121 disconnects and the second current mirror generator 120 stops the charging to charging capacitor 125.Cause This, charging capacitor 125 is electrically charged up to equal to total propagation delay TDEstimation cycle TC, and electric current is equal to control electric current IZCD And with input voltage VinIt is proportional.
For the circuit of Fig. 1, it is assumed that switching frequency fs=1/T (θ) is much higher than input signal VinFrequency fL, then electricity is controlled Flow IZCDAnd the second mirror electric current ICH2The delay T in estimation can be considered asCPeriod is constant, and charging capacitor 125 prolongs estimation Slow TCPeriod is electrically charged, and therefore 125 linear-charging of charging capacitor.
Therefore, the crest voltage V reached by charging capacitor 125CTR_PEAK(θ) is
Discharge switch 123 and transmitting switch 126 remain open, until the pulse of subsequent duty ratio set signal S is connect Receive (moment t3), so that 125 retention value V of charging capacitorCTR_PEAK(θ)。
In moment t3, duty ratio set signal S is switched to height, causes to transmit switch 126 and is closed immediately and by charging capacitor Device 125 is connected to output capacitor 128.It is assumed that output capacitor 128 has the capacitor C than charging capacitor 125TRMuch lower Capacitor CH, it quickly charges to the crest voltage V of charging capacitor 125CTR_PEAK(θ)。
In practice, by combining equation (11) with equation (5), the control voltage V across output capacitor 128CHBy following Equation provides
Itself and input voltage VinBe approximately equal to total propagation delay TDEstimation delay TCProduct it is proportional so that
Therefore compensating current element 131 generates and control signal VCHProportional compensation electric current ICOMP, it is as follows:
Wherein gFFIt is the current-voltage gain of compensating current element 131.
Once duty ratio set signal S again switch to it is low, transmitting switch 126 be again off, by output capacitor 128 from Charging capacitor 125 disconnects.
In electric current source block 103, duty ratio set signal S is provided with slightly delay (moment t4) and be also supplied to Charging capacitor 125 is connected to ground connection in its closure by discharge capacity device 123, discharge capacity device 123, to its repid discharge, And it is then again off.In the short time period that discharge capacity device 123 is closed, charging capacitor 125 is disconnected from output capacitor 128 Open connection, the control voltage V that output capacitor 128 stores before being therefore kept charged toCTRValue.In this way, as Fig. 8 schemes Show, charging capacitor 125 is discharged at each switch cycles and is recharged control voltage VCTRNew value, because This ensures to possible modification input voltage VinOr total propagation delay TDIn condition the adaptation recycled one by one.
The compensation electric current I provided by current source 101COMPTherefore with defeated input voltage VinWith total propagation delay TDProduct at Ratio.
Therefore, switch mode power described herein is due to driver 30 and using the case where replacing power switch M Under do not require appropriate set and independently of input voltage VinAdaptability solution switch M switching (by duty ratio ratio Compared with caused by device 26 delay well below the delay before two, therefore can ignore), so that the compensation of propagation delay become can Energy.
Finally, it should be apparent that can be without departing from the scope of the invention as defined in appended claims the case where Under to it is described herein and illustrate electric current make modification and variation.
Specifically, the solution can also be applied to different types of converter, including be for example depressured and rising Press the current control read without output electric current in the converter of type.

Claims (16)

1. a kind of control circuit (15), for receiving input quantity (Vin) switching regulator current converter switch (M), and it is described Switching regulator current converter includes: with armature winding (Lp) transformer, and generate and the electric current phase in the armature winding Sensing signal (the V of passp) sensor element (19), the control circuit includes:
Comparator stage (25) is configured as comparison signal (Vcs) relevant to the sensing signal and reference signal (VcsREF) it compares, and generates the opening signal (R) for being used for the switch, the switch is relative to the opening signal Propagation delay (TD) switching；
The comparator stage (25) includes comparator element (26) and delay compensating circuit (101),
The delay compensating circuit (101) is configured as estimating the propagation delay and generate and the input quantity (Vin) and it is described Relevant thermal compensation signal (the I of propagation delayCOMP), and
The comparator element (26) is configured as receiving the reference signal, the sensing signal and the thermal compensation signal, And generate the opening signal with lead relevant to the input quantity and the propagation delay.
2. circuit according to claim 1, wherein the comparator stage (25) includes delay estimation block (102) and current source Block (103), the delay estimation block (102), which is configurable to generate, to be had and the propagation delay (TD) relevant parameter delay Estimate signal (Q1), and the electric current source block (103) is configured so that the thermal compensation signal (ICOMP) and the delay Estimate signal parameter and control signal (I relevant to the input quantityZCD) product it is related.
3. circuit according to claim 2, wherein the comparator stage (25) is configured as detection in the transformer (4) Auxiliary winding (Laux) in flow and with the input quantity (Vin) proportional auxiliary current (Iaux), and generate with it is described The proportional control signal (I of auxiliary currentZCD)。
4. circuit according to claim 3, wherein the delay estimation block (102) includes being swashed by the opening signal (R) It is living and detecting the auxiliary current (Iaux) reduction when deactivated switch-mode circuitries.
5. circuit according to claim 4, wherein the switch-mode circuitries (102) include by the auxiliary current (Iaux) Estimation comparator (113) of the instantaneous value compared with length of delay, and be coupled to the output of shown estimation comparator (113) simultaneously And receive the latch logic element (114) of the opening signal (R).
6. the circuit according to any one of claim 2-5, wherein the current source block (103) includes by being prolonged by described Estimate the first switching element (121) of signal (Q1) control late to receive the control signal (IZCD) memory component (125- 128)。
7. circuit according to claim 6, wherein the memory component (125-128) includes capacity cell (125), institute It states capacity cell (125) and is configured to connect to charge generator (120) up to one controlled by the delay estimation signal (Q1) It fixes time, and is discharged with the delay of the connection signal relative to the switch (M).
8. circuit according to claim 7, wherein the switching regulator current converter includes zero current detector (36), institute Zero current detector (36) is stated to be configured as detecting the auxiliary winding (L of the transformer (4)aux) in zero current and generation For the connection signal (S) of the switch (M), and second switch element (123) is configured as the capacity cell (125) it is coupled to reference potential line (12) and receives the connection signal by delay element (132).
9. circuit described in any one of -5,7 and 8 according to claim 1, wherein the switching regulator current converter further includes ginseng Examinee grows up to be a useful person grade (24), described to be configurable to generate and the input quantity (V with reference to generator grade (24)in) relevant reference signal (VcsREF)。
10. circuit described in any one of -5,7 and 8 according to claim 1, wherein the comparator element (26) has first Input and the second input, first input receive the reference signal (VcsREF) and the second input reception sensing Signal (Vp) and with the thermal compensation signal (ICOMP) relevant signal (VFF)。
11. a kind of switch mode power, comprising:
Input terminal receives input quantity (Vin)；
Transformer (4) has armature winding (Lp), the armature winding (Lp) be coupled to the input terminal and be configured as Passed through by primary current；
It switchs (M), with the primary windings connected in series；
Sensor element (19) generates sensing signal (V relevant to the electric current in the armature windingp)；And
Control circuit (15), comprising:
Comparator stage (25) is configured as comparison signal (V relevant to the sensing signalcs) and reference signal (VcsREF) It compares, and generates the opening signal (R) for the switch (M), the switch is with the biography relative to the opening signal Broadcast delay (TD) switching；
Comparator stage (25) includes comparator element (26) and delay compensating circuit (101),
The delay compensating circuit (101) is configured as estimating the propagation delay and generate and the input quantity (Vin) and it is described Propagation delay (TD) relevant thermal compensation signal (ICOMP), and
The comparator element (26) is configured as receiving the reference signal, the sensing signal and the thermal compensation signal, And generate the opening signal with lead relevant to the input quantity and the propagation delay.
12. a kind of for including the control method with the switch of switching regulator power pack of the transformer of armature winding, institute The method of stating includes:
Receive input quantity；
Reference signal and the relevant comparison signal of electric current in the armature winding are compared；
Generate the opening signal for being used for the switch；
Detect the propagation delay (T having relative to the opening signalD) the switch switching；
Estimate the propagation delay and generates thermal compensation signal relevant to the input quantity and the propagation delay；And
By with the input quantity (Vin) and the propagation delay relevant time be expected the opening signal.
13. according to the method for claim 12, including generating there is the delay of parameter relevant to the propagation delay to estimate Signal is counted, and is generated and the input quantity (Vin) relevant control signal, wherein the thermal compensation signal and the delay estimation Product between the parameter of signal and the control signal is related.
14. according to the method for claim 13, including detecting in the auxiliary of the armature winding for being coupled to the transformer Help it is being flowed in winding and with the input quantity (Vin) proportional auxiliary current, and generate related to the auxiliary current The control signal.
15. according to the method for claim 14, receiving the opening signal wherein generating delay estimation signal and being included in First switching edge of delay estimation signal described in Shi Shengcheng, and when detecting the reduction of the auxiliary current described in generation Second switching edge of delay estimation signal.
16. method described in any one of 3-15 according to claim 1, wherein the parameter of the delay estimation signal is arteries and veins Width is rushed, and the thermal compensation signal includes reaching and the pulse width phase using the control signal to memory component charging The certain time of pass.
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