CN106158629B - The production method of MOSFET element - Google Patents
The production method of MOSFET element Download PDFInfo
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- CN106158629B CN106158629B CN201510128889.6A CN201510128889A CN106158629B CN 106158629 B CN106158629 B CN 106158629B CN 201510128889 A CN201510128889 A CN 201510128889A CN 106158629 B CN106158629 B CN 106158629B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 41
- 230000004888 barrier function Effects 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 23
- 229920005591 polysilicon Polymers 0.000 claims description 23
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 122
- 238000000034 method Methods 0.000 description 11
- 238000000407 epitaxy Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 6
- 239000000945 filler Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000004380 ashing Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention provides a kind of production method of MOSFET element characterized by comprising mask layer is formed on the substrate；Using mask layer as exposure mask, substrate is performed etching, is formed simultaneously first groove and second groove；The first filled layer is formed in first groove, and forms barrier bed on the first filled layer；Using barrier bed and mask layer as exposure mask, second groove is performed etching, so that the depth of second groove increases to predetermined depth, forms third groove；The second filled layer is formed in third groove.The production method of MOSFET element according to the present invention, by being formed simultaneously first groove and second groove, then only second groove is performed etching to form third groove, and then form deep trouth and shallow slot, influence of the photoetching deviation of the alignment for MOSFET element when can be avoided to form deep trouth and shallow slot, optimize the manufacture craft of MOSFET element, simple flow reduces cost.
Description
Technical field
The present invention relates to semiconductor technology more particularly to a kind of production methods of MOSFET element.
Background technique
In MOSFET (Metal Oxide Semiconductor Field Effect Transistor, Metal Oxide Semiconductor Field
Effect Transistor, MOSFET) in device, generally reduce power loss by reducing the conducting resistance of device.
And inversely due to breakdown voltage and conducting resistance, so when conducting resistance reduces, it can be to breakdown voltage
It has adverse effect on.In order to solve this problem, superjunction power MOSFET is introduced in the prior art comprising is located at superjunction
Below the active area of type power MOSFET, the p type island region that is alternatively formed and N-type region.Alternate p type island region in superjunction power MOSFET
In the ideal situation with N-type region, it should charge balance state is in, so that p type island region and N-type region are mutual under reverse voltage condition
It exhausts, resistance to sparking is preferable.
But it for traditional groove-shaped superjunction power MOSFET device, generally requires and is formed by Twi-lithography
Both deep trouth and shallow slot, shallow slot are used to form grid, and deep trouth is used to form cylinder, such as p-type column is formed in N-type layer, in this way
Spacing be affected by lithography alignment, if the deviation ratio of lithography alignment is more serious, various adverse effects can be generated, than
Bigger than normal, phenomena such as threshold voltage becomes smaller, and breakdown voltage becomes smaller of leaking electricity between the source and drain of MOSFET element can such as be generated.
Summary of the invention
The present invention provides a kind of production method of MOSFET element, to solve to be formed deep trouth and shallow careless time in the prior art
Carve the defect that alignment generates deviation effects MOSFET element overall performance.
First aspect of the present invention provides a kind of production method of MOSFET element, comprising:
Mask layer is formed on the substrate；
Using the mask layer as exposure mask, the substrate is performed etching, is formed simultaneously the first groove and described second
Groove；
The first filled layer is formed in the first groove, and forms barrier bed on first filled layer；
Using the barrier bed and the mask layer as exposure mask, the second groove is performed etching, so that second ditch
The depth of slot increases to predetermined depth, forms third groove；
The second filled layer is formed in the third groove.
The production method of MOSFET element as described above, optionally, the substrate includes sequentially forming from bottom to top
The substrate of first conduction type, the first layer structure of the first conduction type, the second layer structure and first of the second conduction type
The depth of the third layer structure of conduction type, the first groove and the second groove is greater than the second layer structure and described
The sum of the thickness of third layer structure.
The production method of MOSFET element as described above, optionally, the formation first in the first groove are filled out
Filling layer includes:
The first gate oxide is formed in the first groove；
The first polysilicon layer is formed in the first groove.
The production method of MOSFET element as described above, optionally,
It is described while form the first gate oxide in the first groove, further includes: the shape in the second groove
At the second gate oxide；
It is described while form the first polysilicon layer in the first groove, further includes: the shape in the second groove
At the second polysilicon layer.
The production method of MOSFET element as described above, optionally, described perform etching to the second groove is also wrapped
It includes:
To in the second groove second gate oxide and second polysilicon perform etching, with removal described in
Second gate oxide and second polysilicon.
The production method of MOSFET element as described above, optionally, after the formation third groove, and described
It is formed in third groove before the second filled layer, further includes:
Remove the mask layer.
The production method of MOSFET element as described above, optionally, after the removal mask layer, and in institute
It states before forming the second filled layer in third groove, further includes:
The ion implanting operation that the second conduction type is carried out to the third layer structure, forms the third of the second conduction type
Layer structure.
The production method of MOSFET element as described above, optionally, in the third layer for forming the first conduction type
After structure, further includes:
Remove the barrier bed.
The production method of MOSFET element as described above optionally forms the second filled layer in the third groove
Include:
The 4th with the second conduction type is formed simultaneously in the third groove and above first filled layer
Epitaxial layer；
Removal is higher by the fourth epitaxial layer of the third layer structure of second conduction type.
As shown from the above technical solution, the production method of MOSFET element provided by the invention, by being formed simultaneously first
Groove and second groove then only perform etching to form third groove second groove, and then form deep trouth and shallow slot, energy
Influence of the photoetching deviation of the alignment for MOSFET element when enough avoiding the formation of deep trouth and shallow slot optimizes the production work of MOSFET element
Skill, simple flow reduce cost.
Detailed description of the invention
Fig. 1 is the flow diagram according to the production method of the MOSFET element of one embodiment of the invention；
Fig. 2A to Fig. 2 J is the knot according to each step of the production method of the MOSFET element of another embodiment of the present invention
Structure schematic diagram.
Specific embodiment
Embodiment one
The present embodiment provides a kind of production methods of MOSFET element, for making MOSFET element.As shown in Figure 1, being
According to the flow diagram of the production method of the MOSFET element of the present embodiment.The production method of the MOSFET element of the present embodiment
Include:
Step 100, mask layer is formed on the substrate.
The mask layer of the present embodiment can be oxide layer, and the material of the oxide layer can be silica or silica, when
Other materials can also be so used according to actual needs, can specifically be set according to actual needs, details are not described herein.
The substrate of the present embodiment can include the substrate of the first conduction type sequentially formed from bottom to top with substrate, first lead
The third layer structure of the first layer structure of electric type, the second layer structure of the second conduction type and the first conduction type, first
The depth of groove and second groove is greater than the sum of second layer structure and thickness of third layer structure.Each layer structure of substrate can adopt
It is generated with extensional mode, can also be formed, can specifically be selected according to actual needs, in the present embodiment using ion implanting mode
It repeats no more.
Step 101, using mask layer as exposure mask, substrate is performed etching, is formed simultaneously first groove and second groove.
It is simultaneously formed due to first groove and second groove, so the deep equality of first groove and second groove.
Specifically, substrate can be etched to preset a certain depth, so that the depth of first groove and second groove is the depth.
Step 102, the first filled layer is formed in first groove, and forms barrier bed on the first filled layer.
The effect of barrier bed is for preventing the first filled layer by the destruction of subsequent certain techniques.The barrier bed can be
The oxide layer that photoresist either uses etching mode to be formed.Using photoresist, it is only necessary to which the techniques such as exposure development can be
It is formed on barrier bed, can thus avoid the damage to other film layers as far as possible.
First filled layer of the present embodiment may include the gate oxide that trenched side-wall and bottom are formed and in gate oxidation
Gate material layers inside layer, such as polysilicon.That is, the step may include: to form the first grid in first groove first
Then oxide layer forms the first polysilicon layer in first groove.
Step 103, using barrier bed and mask layer as exposure mask, second groove is performed etching, so that the depth of second groove
Predetermined depth is increased to, third groove is formed.
The depth of third groove is greater than the depth of second groove, i.e., the third groove is deep trouth, and first groove is shallow slot.
Due to the presence of mask layer, when can avoid etching second trenches as far as possible caused by deviation.And due to forming third groove
It does not need to carry out photoetching process in step, only with etching technics, cost is relatively low.
Step 104, the second filled layer is formed in third groove.
Second filled layer is the material to form cylinder, such as can be epitaxial layer.More specifically, e.g. in N-type
The p-type column formed or the N-type column formed in P-type layer in layer.
Then, the step of carrying out subsequent formation other structures in the MOSFET element for foring the second filled layer, with
Final MOSFET element is formed, these steps are the prior art, and details are not described herein.
It is connect according to the production method of the MOSFET element of the present embodiment by being formed simultaneously first groove and second groove
Only second groove is performed etching to form third groove, and then form deep trouth and shallow slot, can be avoided to be formed deep trouth and
Influence of the photoetching deviation of the alignment for MOSFET element when shallow slot, optimizes the manufacture craft of MOSFET element, and simple flow reduces
Cost.
Embodiment two
The present embodiment does further supplementary explanation to the production method of the MOSFET element of above-described embodiment.
While forming the first gate oxide in first groove, further includes: form the second gate oxidation in second groove
Layer；
While forming the first polysilicon layer in first groove, further includes: form the second polysilicon in second groove
Layer.
In this way, being performed etching to second groove further include:
To in second groove the second gate oxide and the second polysilicon perform etching, to remove the second gate oxide and the
Two polysilicon layers.
That is, when being performed etching to second groove, it is necessary first to etching when second groove in the second gate oxide and
Two polysilicon layers remove second gate oxide and the second polysilicon layer, and continue etching downwards, so that the depth of second groove
Degree increases to predetermined depth, forms third groove.
In the present embodiment, when first groove forms the first filler, second groove is formed simultaneously corresponding filler, in turn
The operation for forming barrier bed in second groove is avoided, technique can be simplified, and the filler in second groove also can be
It is removed in subsequent etching process, will not influence the overall performance of MOSFET element.Moreover, because filler in second groove
In the presence of, when forming barrier bed, even if photoetching to inclined, will not be right also due to the protective effect of the filler in second groove
Second groove impacts.
Embodiment three
The present embodiment does further supplementary explanation to the production method of the MOSFET element of above-described embodiment.
In the present embodiment, if being formed with mask layer in a step 101, after step 103, and before step 104,
The production method of the MOSFET element of the present embodiment further include:
Step a: removal mask layer.
The present embodiment can remove the mask layer by the way of ion etching, specifically repeat no more.It is noted that if
There is barrier bed on mask layer, then the mask layer below barrier bed can not remove.
Optionally, if substrate may include the substrate of the first conduction type sequentially formed from bottom to top, the first conductive-type
The third layer structure of the first layer structure of type, the second layer structure of the second conduction type and the first conduction type, then in step a
Later, and before step 104, further includes:
Step b: the ion implanting for carrying out the second conduction type to third layer structure operates, and forms the of the second conduction type
Three-decker.
If also having remaining mask layer, the third layer knot for the first conduction type that mask layer covers below above substrate
The part of structure not will become the first conduction type.
Optionally, after step b, the production method of the MOSFET element of the present embodiment further include:
Remove barrier bed.
The barrier bed then can remove the photoresist by the way of ashing, specifically repeat no more if photoresist.This goes
Can after step 104 except operation, it can also be before step 104.
Optionally, the step 104 of the present embodiment includes:
In third groove and the fourth epitaxial layer with the second conduction type is formed simultaneously above the first filled layer；
Removal is higher by the fourth epitaxial layer of the third layer structure of the second conduction type.
Specifically the can be higher by using chemically mechanical polishing (Chemical Mechanical polishing, CMP) removal
The fourth epitaxial layer of three-decker, remaining fourth epitaxial layer i.e. the second filler in third groove.If forming fourth epitaxial layer
Substrate surface also has barrier bed afterwards, then can be removed the barrier bed together by chemically mechanical polishing mode.
In the present embodiment, using preformed barrier bed as exposure mask, ion implanting is carried out to the film layer on substrate surface layer, with shape
At the film layer of required conduction type, the technique for avoiding carrying out forming barrier bed for injection ion can save processing step.
Example IV
The present embodiment does concrete example explanation to the production method of the MOSFET element of above-described embodiment.Such as Fig. 2A to 2J institute
Show, for according to the structural schematic diagram of each step of the production method of the MOSFET element of the present embodiment.
As shown in Figure 2 A, former mask layer 200 is formed in substrate 201.
As shown in Figure 2 B, photoetching process is carried out to the former mask layer 200, forms mask layer 202 in substrate 201.
The substrate of the present embodiment includes the N-type substrate 2011, N-type epitaxy layer 2012, p-type extension sequentially formed from bottom to top
Layer 2013 and N-type epitaxy layer 2014.That is, the first layer structure of the present embodiment is N-type epitaxy layer 2012, second layer structure is p-type
Epitaxial layer 2013, third layer structure are N-type epitaxy layer 2014.
As shown in Figure 2 C, it is exposure mask with mask layer 202, substrate 201 is performed etching, is formed simultaneously 203 He of first groove
Second groove 204.
The deep equality of first groove 203 and second groove 204, and the bottom of first groove 203 and second groove 204
Bottom is respectively positioned in N-type epitaxy layer 2012.There are two the second grooves 204 of the present embodiment.
As shown in Figure 2 D, the first gate oxide 205 is formed in first groove 203, and is formed in second groove 204
Two gate oxides 206, and the first polysilicon layer 207 is being formed in first groove 203, and is formed in second groove 204
Two polysilicon layers 208.
The mode for forming gate oxide can use thermal oxide mode, specifically repeat no more.More than first in the present embodiment
Crystal silicon layer 207 plays the role of grid.The height of first polysilicon layer 207 and the second polysilicon layer 208 is and N-type epitaxy layer
2014 flush, and can specifically be realized by the way of returning quarter polysilicon layer.
As shown in Figure 2 E, barrier bed 209 is formed above first groove 203.
Specifically photoresist can be formed as barrier bed in the top of first groove 203 by the way of exposure, development
209。
As shown in Figure 2 F, it is exposure mask with barrier bed 209 and mask layer 202, second groove 204 is performed etching, so that the
The depth of two grooves 204 increases to predetermined depth, forms third groove 210.
The second gate oxide more than 206 and second while being performed etching to second groove 204, in second groove 204
Crystal silicon layer 208 is etched away.
As shown in Figure 2 G, mask layer 202 is removed.
It is noted that part mask layer 202 ' is not removed due to the effect of barrier bed 209.
As illustrated in figure 2h, P-type ion implant operation is carried out to N-type epitaxy layer 2014, to form p-type epitaxial layer 2015.
It is noted that the part that N-type epitaxy layer 2014 is covered by mask layer 202 ' is simultaneously due to the effect of mask layer 202 '
Not by injecting p-type ion, N-type epitaxy layer 2014 is remained as.
As shown in figure 2i, barrier bed 209 and mask layer 202 ' are removed.
It can be specifically removed, can also be removed using CMP mode by the way of etching.
As shown in fig. 2j, epitaxy technique is carried out, (is not shown in figure with being formed by formation fourth epitaxial layer on device in Fig. 2 I
Out), and using CMP mode the fourth epitaxial layer higher than p-type epitaxial layer 2015 is removed, to form second in third groove 210
Filled layer 211.
The formation other structures of subsequent progress, such as the step of dielectric layer, metal layer, are the prior art, herein no longer
It repeats.
The production method of the MOSFET element of the present embodiment, the case where deep trouth and shallow slot position can be avoided to deviate as far as possible,
And processing step simplifies, and production cost reduces.
Those of ordinary skill in the art will appreciate that: realize that all or part of the steps of above method embodiment can pass through
The relevant hardware of program instruction is completed, and program above-mentioned can be stored in a computer readable storage medium, the program
When being executed, step including the steps of the foregoing method embodiments is executed；And storage medium above-mentioned includes: ROM, RAM, magnetic disk or light
The various media that can store program code such as disk.
Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
Present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: it still may be used
To modify the technical solutions described in the foregoing embodiments or equivalent replacement of some of the technical features；
And these are modified or replaceed, the range for technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution.
Claims (8)
1. a kind of production method of MOSFET element characterized by comprising
Mask layer is formed on the substrate；
Using the mask layer as exposure mask, the substrate is performed etching, first groove and second groove are formed simultaneously；
The first filled layer is formed in the first groove, and forms barrier bed on first filled layer；
Using the barrier bed and the mask layer as exposure mask, the second groove is performed etching, so that the second groove
Depth increases to predetermined depth, forms third groove；
The second filled layer is formed in the third groove；
Wherein, first filled layer that formed in the first groove includes:
The first gate oxide is formed in the first groove；
The first polysilicon layer is formed in the first groove.
2. the production method of MOSFET element according to claim 1, which is characterized in that the substrate includes from bottom to top
The substrate of the first conduction type sequentially formed, the first layer structure of the first conduction type, the second conduction type second layer knot
The depth of the third layer structure of structure and the first conduction type, the first groove and the second groove is greater than the second layer
The sum of the thickness of structure and the third layer structure.
3. the production method of MOSFET element according to claim 2, which is characterized in that
It is described while form the first gate oxide in the first groove, further includes: is formed in the second groove
Two gate oxides；
It is described while form the first polysilicon layer in the first groove, further includes: is formed in the second groove
Two polysilicon layers.
4. the production method of MOSFET element according to claim 3, which is characterized in that it is described to the second groove into
Row etching further include:
To in the second groove second gate oxide and second polysilicon perform etching, to remove described second
Gate oxide and second polysilicon.
5. the production method of MOSFET element according to claim 2, which is characterized in that the formation third groove it
Afterwards, before and forming the second filled layer in the third groove, further includes:
Remove the mask layer.
6. the production method of MOSFET element according to claim 5, which is characterized in that in the removal mask layer
Later, before and forming the second filled layer in the third groove, further includes:
The ion implanting operation that the second conduction type is carried out to the third layer structure, forms the third layer knot of the second conduction type
Structure.
7. the production method of MOSFET element according to claim 6, which is characterized in that described to the third layer knot
Structure carries out the ion implanting operation of the second conduction type, is formed after the third layer structure of the second conduction type, further includes:
Remove the barrier bed.
8. the production method of MOSFET element according to claim 7, which is characterized in that formed in the third groove
Second filled layer includes:
In the third groove and the fourth epitaxial with the second conduction type is formed simultaneously above first filled layer
Layer；
Removal is higher by the fourth epitaxial layer of the third layer structure of second conduction type.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101859705A (en) * | 2009-01-29 | 2010-10-13 | 万国半导体有限公司 | High density trench mosfet with single mask pre-defined gate and contact trenches |
| CN103187301A (en) * | 2011-12-16 | 2013-07-03 | 茂达电子股份有限公司 | Trench type power transistor component with super interface and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20110117326A (en) * | 2010-04-21 | 2011-10-27 | 매그나칩 반도체 유한회사 | Semiconductor device and method for manufacturing the same |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101859705A (en) * | 2009-01-29 | 2010-10-13 | 万国半导体有限公司 | High density trench mosfet with single mask pre-defined gate and contact trenches |
| CN103187301A (en) * | 2011-12-16 | 2013-07-03 | 茂达电子股份有限公司 | Trench type power transistor component with super interface and manufacturing method thereof |
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