CN106158581A - A kind of method that wafer after wiring is carried out Alloying Treatment - Google Patents
A kind of method that wafer after wiring is carried out Alloying Treatment Download PDFInfo
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- CN106158581A CN106158581A CN201510137146.5A CN201510137146A CN106158581A CN 106158581 A CN106158581 A CN 106158581A CN 201510137146 A CN201510137146 A CN 201510137146A CN 106158581 A CN106158581 A CN 106158581A
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- 238000000034 method Methods 0.000 title claims abstract description 44
- 238000005275 alloying Methods 0.000 title claims abstract description 24
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 99
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 40
- 239000007789 gas Substances 0.000 claims abstract description 27
- 229910001873 dinitrogen Inorganic materials 0.000 claims abstract description 22
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 20
- 239000001257 hydrogen Substances 0.000 claims abstract description 20
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 19
- 238000010792 warming Methods 0.000 claims abstract description 9
- 230000002045 lasting effect Effects 0.000 claims abstract description 7
- 239000012159 carrier gas Substances 0.000 claims abstract description 6
- 150000002431 hydrogen Chemical class 0.000 claims description 4
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims description 3
- 239000000956 alloy Substances 0.000 abstract description 18
- 229910045601 alloy Inorganic materials 0.000 abstract description 17
- 239000003990 capacitor Substances 0.000 abstract description 13
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 10
- 239000001301 oxygen Substances 0.000 abstract description 10
- 229910052760 oxygen Inorganic materials 0.000 abstract description 10
- 230000008439 repair process Effects 0.000 abstract description 8
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 239000004065 semiconductor Substances 0.000 abstract description 7
- 238000005457 optimization Methods 0.000 abstract description 6
- 238000002161 passivation Methods 0.000 abstract description 5
- 230000008859 change Effects 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 238000001816 cooling Methods 0.000 abstract description 2
- 230000008569 process Effects 0.000 description 16
- 230000010355 oscillation Effects 0.000 description 11
- 238000000137 annealing Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 2
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910000714 At alloy Inorganic materials 0.000 description 1
- 229910000846 In alloy Inorganic materials 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000013467 fragmentation Methods 0.000 description 1
- 238000006062 fragmentation reaction Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02356—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention provides a kind of method that wafer after wiring is carried out Alloying Treatment, and the method includes: is placed in a cavity by the wafer after wiring, is passed through the nitrogen for carrier gas continuously, and cavity temperature is warming up to the first preset temperature in cavity；Keep the first preset temperature, in cavity, be passed through a mixed gas containing preset ratio hydrogen lasting the first Preset Time with preset flow；Wherein, preset flow is more than Stream threshold value；After mixed gas is passed through end, in cavity, again it is passed through nitrogen until for pure nitrogen gas, cooling cavities under pure nitrogen gas atmosphere in cavity residing for wafer.The method is by the optimization to the alloy menu in semiconductor fabrication, will alloy time lead to preset ratio hydrogen flow increase, Si (silicon) dangling bonds near passivation interface effectively, it is substantially reduced interface state density, repair the quality of grid oxygen, thus change the C-V curve characteristic of NMOS capacitor, then reach to improve the purpose that frequency lost efficacy, the most just improve product yield simultaneously.
Description
Technical field
The present invention relates to semiconductor chip fabrication process technical field, particularly to one, wafer after wiring is entered
The method of row Alloying Treatment.
Background technology
In semiconductor manufacturing CMOS technology technology, wafer, can be through one alloy after completing wiring
(Alloy) technique, alloying technology is equivalent to the process of an annealing, its object is to make metal recrystallization,
Repair the damage etc. that ion causes.In integrated circuit design, the designer of circuit often designs a vibration
Circuit can produce the identical periodic swinging electric current of size and Orientation thus realize the purpose of circuit work.Specifically
, the cycle T of oscillating circuit=1/f=2 π RC, from formula it can be seen that frequency of oscillation f and oscillating circuit
Resistance R, electric capacity C are relevant, and frequency of oscillation f is inversely proportional to oscillation resistance, and frequency of oscillation f is with oscillating capacitance also
It is inversely proportional to.It is NMOS capacitor, the CMOS technology product of outer meeting resistance (steady state value) for oscillating circuit,
Oscillating capacitance C reduces, then frequency of oscillation f increases；Oscillating capacitance C increases, then frequency of oscillation f reduces.
The oscillating circuit of equivalence is as shown in Figure 1.NMOS capacitor C=(ε S)/(4 π Kd), from formula it can be seen that
Electric capacity C and ε S is directly proportional, and electric capacity C and 4 π Kd is inversely proportional to.For in semiconductor manufacturing NMOS capacitor,
The quality of grid oxygen can affect electric capacity C.Such as, removable ionic charge etc..Wherein, ε is dielectric constant；
S is the area that on electric capacity, bottom crown is corresponding；D is the distance that on electric capacity, bottom crown is corresponding；K is a constant.
In prior art, the hydrogen H being passed through in the alloy process to wafer2Gas flow less, it is impossible to
Well repair grid oxygen quality, affect stability and the size of NMOS capacitor C, then make frequency of oscillation
Inefficacy causes product yield to decline.
Summary of the invention
It is an object of the invention to provide a kind of method that wafer after wiring is carried out Alloying Treatment, repair
The grid oxygen quality of NMOS capacitor, thus change the C-V curve characteristic of NMOS capacitor, then reach to improve
Frequency lost efficacy, and improved product yield.
In order to achieve the above object, the embodiment of the present invention provides one that wafer after wiring is carried out Alloying Treatment
Method, including:
Wafer after wiring is placed in a cavity, in described cavity, is passed through the nitrogen for carrier gas continuously,
And cavity temperature is warming up to the first preset temperature；
Keep the first preset temperature, in described cavity, be passed through one containing preset ratio hydrogen with preset flow
Mixed gas persistently the first Preset Time；Wherein, described preset flow is more than Stream threshold value；
After mixed gas is passed through end, in described cavity, again it is passed through nitrogen until chamber residing for described wafer
Internal for pure nitrogen gas, under described pure nitrogen gas atmosphere, cool down described cavity.
Wherein, in described cavity, it is passed through the nitrogen for carrier gas continuously, and cavity temperature is warming up to first
Preset temperature, specifically includes:
In described cavity, it is passed through the nitrogen that flow is the first preset value, and it is pre-that cavity temperature is warming up to first
If temperature；
The flow of described nitrogen is increased to the second preset value, and continuing to be passed through flow in described cavity is second
The nitrogen of preset value persistently the second Preset Time.
Wherein, described in described cavity, again it is passed through nitrogen until for purity nitrogen in cavity residing for described wafer
Gas, cools down described cavity under described pure nitrogen gas atmosphere, specifically includes:
In described cavity, it is passed through continuously nitrogen that flow is the 3rd preset value lasting the 3rd Preset Time；Its
In, flow is after the nitrogen of the 3rd preset value is passed through end, is pure nitrogen gas atmosphere in described cavity；
Nitrogen flow is reduced to the 4th preset value, continues to be passed through flow in the cavity of described pure nitrogen gas atmosphere
It is nitrogen lasting the 4th Preset Time of the 4th preset value；Described chamber is cooled down in described 4th Preset Time
Body.
Preferably, described Stream threshold value is 6L/min, and described preset flow is 10L/min, described first pre-
If the time is 30min.
Preferably, described mixed gas is nitrogen and hydrogen, and in described mixed gas, the ratio of hydrogen is 4%.
Preferably, described first preset temperature is 425 DEG C.
Preferably, described first preset value is 8L/min, and described second preset value is 10L/min, described second
Preset Time is 5min.
Preferably, described 3rd preset value is 10L/min, and described 3rd Preset Time is 5min, described
Four preset values are 8L/min, and described 4th Preset Time is 40min.
The technique scheme of the present invention at least has the advantages that
The embodiment of the present invention to after wiring, wafer carries out the method for Alloying Treatment in, by quasiconductor system
Make the optimization of alloy menu in technology, the flow of preset ratio hydrogen will be led to increase, then not during alloy
In the case of the structure of the grid oxygen of damage wafer, more efficiently Si (silicon) dangling bonds near passivation interface,
It is substantially reduced interface state density, repairs the quality of grid oxygen, thus change the C-V curve characteristic of NMOS capacitor,
Then reach to improve the purpose that frequency lost efficacy, the most just improve product yield simultaneously；On the other hand after to wiring
Wafer carry out Alloying Treatment be equivalent to annealing process, repaired the damage that ion causes.
Accompanying drawing explanation
Fig. 1 represents the circuit structure diagram of equivalence oscillating circuit；
What Fig. 2 represented the embodiment of the present invention carries out the basic step of method of Alloying Treatment to wafer after wiring
Schematic diagram；
After Fig. 3 represents that in prior art, NMOS capacitor optimizes with the method utilizing the embodiment of the present invention to provide
The comparison diagram of NMOS capacitor；
Fig. 4 represent frequency of oscillation in prior art and utilize the embodiment of the present invention to provide method optimization after shake
Swing the comparison diagram of frequency；
Fig. 5 represent product yield in prior art and utilize the embodiment of the present invention to provide method optimization after product
The comparison diagram of product yield.
Detailed description of the invention
For making the technical problem to be solved in the present invention, technical scheme and advantage clearer, below in conjunction with attached
Figure and specific embodiment are described in detail.
The present invention is directed in CMOS technology technology of the prior art, the NMOS electricity caused in alloy process
The problem that the frequency held lost efficacy, it is provided that a kind of method that wafer after wiring is carried out Alloying Treatment, by right
The optimization of the alloy menu in semiconductor fabrication, will alloy time lead to preset ratio hydrogen flow increase,
Then in the case of not damaging the structure of grid oxygen of wafer, more efficiently near passivation interface, Si (silicon) hangs
Hang key, be substantially reduced interface state density, repair the quality of grid oxygen, thus the C-V changing NMOS capacitor is bent
Line characteristic, then reaches to improve the purpose that frequency lost efficacy, the most just improves product yield simultaneously；On the other hand
Wafer after wiring is carried out Alloying Treatment and is equivalent to the process of annealing, repair the damage that ion causes.
As in figure 2 it is shown, the embodiment of the present invention provides a kind of method that wafer after wiring is carried out Alloying Treatment,
Including:
Step 11, is placed in the wafer after wiring in a cavity, is passed through continuously for carrier gas in described cavity
Nitrogen, and cavity temperature is warming up to the first preset temperature；
Step 12, keeps the first preset temperature, is passed through one containing presetting ratio with preset flow in described cavity
The mixed gas of example hydrogen persistently the first Preset Time；Wherein, described preset flow is more than Stream threshold value；
Step 13, after mixed gas is passed through end, is passed through nitrogen again until described wafer in described cavity
It is pure nitrogen gas in residing cavity, under described pure nitrogen gas atmosphere, cools down described cavity.
In the above embodiment of the present invention, after wafer after wiring is placed in the cavity being full of nitrogen, by cavity
Interior temperature rises to the first preset temperature, then is passed through mixed gas, contains the hydrogen of preset ratio in mixed gas
Gas, is passed through in nitrogen makes cavity the most again and becomes pure nitrogen gas environment, then reduce cavity inner temperature.Need explanation
, during whole alloying technology, the lifting of the annealing temperature in cavity all needs slowly, it is possible to effectively
Avoid bonding after wafer in annealing process, there is fragmentation phenomenon, and whole process the most for once heats up
Once lowering the temperature, in annealing process, temperature controls simple, convenient operation.
In the above embodiment of the present invention, step 11 specifically includes:
Step 111, is passed through the nitrogen that flow is the first preset value in described cavity, and is heated up by cavity temperature
To the first preset temperature；
Step 112, is increased to the second preset value by the flow of described nitrogen, continues to be passed through stream in described cavity
Amount is nitrogen lasting second Preset Time of the second preset value.
In the above embodiment of the present invention, step 13 specifically includes:
Step 131, is passed through nitrogen that flow is the 3rd preset value continuously in described cavity and persistently the 3rd presets
Time；Wherein, flow is after the nitrogen of the 3rd preset value is passed through end, is pure nitrogen gas atmosphere in described cavity；
Step 132, is reduced to the 4th preset value by nitrogen flow, continues in the cavity of described pure nitrogen gas atmosphere
It is passed through nitrogen that flow is the 4th preset value lasting the 4th Preset Time；In described 4th Preset Time cold
The most described cavity.
Concrete, described Stream threshold value is 6L/min, and described preset flow is 10L/min, described first pre-
If the time is 30min.
Concrete, described mixed gas is nitrogen and hydrogen, and in described mixed gas, the ratio of hydrogen is 4%.
Concrete, described first preset temperature is 425 DEG C.
Concrete, described first preset value is 8L/min, and described second preset value is 10L/min, described second
Preset Time is 5min.
Concrete, described 3rd preset value is 10L/min, and described 3rd Preset Time is 5min, described the
Four preset values are 8L/min, and described 4th Preset Time is 40min.
In sum, the detailed process of this alloying technology is as follows:
First, the wafer after wiring is placed in pure nitrogen gas atmosphere (gas flow is 8L) and is warming up to 425 DEG C,
And in the pure nitrogen gas that gas flow is 10L, keep 5min；Be subsequently passed hydrogen that hydrogen content is 4% and
The mixed gas (gas flow is 6L) of nitrogen also keeps 30min, then (gas flow is to be passed through pure nitrogen gas
10L) and keep 5min, then cooling 40min, this conjunction in pure nitrogen gas atmosphere (gas flow is 8L)
Gold process completes.
After alloy menu optimizes, 4% hydrogen (H will be led to during alloy2) gas flow strengthen (from 6L strengthen
To 10L) such that it is able to the quality of grid oxygen GOX is repaired, so that electric capacity C is more stable.
Its operation principle is as follows: in semiconductor manufacturing CMOS technology technology, the surface of grid oxygen (GOX)
There are the dangling bonds of substantial amounts of Si, this is the main source of interfacial state.In alloy (Alloy) process,
Hydrogen is combined formation Si-H covalent bond with dangling bonds, it is possible to remove the dangling bonds at interface, in this process
When improving gas flow, the mean kinetic energy of hydrogen increases, and the penetration capacity of H atom increases, and causes H
The atom coverage rate in interface has increased, and near passivation interface, the ability of Si dangling bonds strengthens.This alloy
(Alloy) by 4% hydrogen gas increased flow capacity in process, in the feelings of the lattice structure not damaging GOX
Under condition, it is possible to more efficiently Si dangling bonds near passivation interface, it is substantially reduced interface state density, repairs GOX
Quality.It addition, during semiconductor manufacturing CMOS, wafer is to keep away with contacting of external environment condition
Exempting from, this can cause crystal column surface can adsorb some impurity (such as O2Deng) and selective oxidation, at alloy (Alloy)
By 4% hydrogen gas increased flow capacity in process, the coverage rate of H atom increases, it is possible to preferably eliminate suction
Attached impurity, the oxide layer that the most preferably reduction wire is formed after wiring, reduces the resistance of wire.
4% hydrogen gas increased flow capacity (is such as added by alloy (Alloy) process from original 6L
Greatly to 10L), it is possible to preferably remove interface dangling bonds, reduce interface state density, make the quality of GOX obtain
To repairing, causing the DIELECTRIC CONSTANT ε of GOX to improve, electric capacity increases, and the resistance of wire reduces simultaneously, and these are two years old
The synergism of aspect causes frequency of oscillation f of CMOS to reduce, and makes the frequency characteristic of product be improved.
As it is shown on figure 3, NMOS capacitor 1 and the method utilizing the embodiment of the present invention to provide are excellent in prior art
The contrast of the NMOS capacitor 2 after change；It is illustrated in figure 4 in prior art frequency of oscillation 3 and utilizes this
The contrast of the frequency of oscillation 4 after the method optimization that bright embodiment provides, as shown in Figure 4, shakes in prior art
Swing frequency 3 and easily lost efficacy (the most not in the range of upper frequency limit and lower-frequency limit are drawn a circle to approve)；It is illustrated in figure 5
Product yield 6 after product yield 5 optimizes with the method utilizing the embodiment of the present invention to provide in prior art
Contrast, the wafer that processed of alloying processing method that the embodiment of the present invention provides as seen from Figure 5 good
Rate significantly increases.
The above is the preferred embodiment of the present invention, it is noted that for the common skill of the art
For art personnel, on the premise of without departing from principle of the present invention, it is also possible to make some improvements and modifications,
These improvements and modifications also should be regarded as protection scope of the present invention.
Claims (8)
1. the method that wafer after wiring is carried out Alloying Treatment, it is characterised in that including:
Wafer after wiring is placed in a cavity, in described cavity, is passed through the nitrogen for carrier gas continuously,
And cavity temperature is warming up to the first preset temperature；
Keep the first preset temperature, in described cavity, be passed through one containing preset ratio hydrogen with preset flow
Mixed gas persistently the first Preset Time；Wherein, described preset flow is more than Stream threshold value；
After mixed gas is passed through end, in described cavity, again it is passed through nitrogen until chamber residing for described wafer
Internal for pure nitrogen gas, under described pure nitrogen gas atmosphere, cool down described cavity.
The method that wafer after wiring is carried out Alloying Treatment the most according to claim 1, its feature exists
In, in described cavity, it is passed through the nitrogen for carrier gas continuously, and cavity temperature is warming up to the first default temperature
Degree, specifically includes:
In described cavity, it is passed through the nitrogen that flow is the first preset value, and it is pre-that cavity temperature is warming up to first
If temperature；
The flow of described nitrogen is increased to the second preset value, and continuing to be passed through flow in described cavity is second
The nitrogen of preset value persistently the second Preset Time.
The method that wafer after wiring is carried out Alloying Treatment the most according to claim 1, its feature exists
In, described in described cavity, again it is passed through nitrogen until for pure nitrogen gas in cavity residing for described wafer,
Cool down described cavity under described pure nitrogen gas atmosphere, specifically include:
In described cavity, it is passed through continuously nitrogen that flow is the 3rd preset value lasting the 3rd Preset Time；Its
In, flow is after the nitrogen of the 3rd preset value is passed through end, is pure nitrogen gas atmosphere in described cavity；
Nitrogen flow is reduced to the 4th preset value, continues to be passed through flow in the cavity of described pure nitrogen gas atmosphere
It is nitrogen lasting the 4th Preset Time of the 4th preset value；Described chamber is cooled down in described 4th Preset Time
Body.
The method that wafer after wiring is carried out Alloying Treatment the most according to claim 1, its feature exists
In, described Stream threshold value is 6L/min, and described preset flow is 10L/min, and described first Preset Time is
30min。
5., according to the method that wafer after wiring is carried out Alloying Treatment described in claim 1 or 4, it is special
Levying and be, described mixed gas is nitrogen and hydrogen, and in described mixed gas, the ratio of hydrogen is 4%.
The method that wafer after wiring is carried out Alloying Treatment the most according to claim 1, its feature exists
In, described first preset temperature is 425 DEG C.
The method that wafer after wiring is carried out Alloying Treatment the most according to claim 2, its feature exists
In, described first preset value is 8L/min, and described second preset value is 10L/min, described second Preset Time
For 5min.
The method that wafer after wiring is carried out Alloying Treatment the most according to claim 3, its feature exists
In, described 3rd preset value is 10L/min, and described 3rd Preset Time is 5min, described 4th preset value
For 8L/min, described 4th Preset Time is 40min.
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| CN201510137146.5A CN106158581B (en) | 2015-03-26 | 2015-03-26 | The method that wafer carries out Alloying Treatment after a kind of pair of wiring |
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| CN201510137146.5A CN106158581B (en) | 2015-03-26 | 2015-03-26 | The method that wafer carries out Alloying Treatment after a kind of pair of wiring |
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| US10943928B2 (en) | 2018-03-26 | 2021-03-09 | Boe Technology Group Co., Ltd. | Display substrate, method for manufacturing the same and display device |
| CN111863611A (en) * | 2020-07-30 | 2020-10-30 | 广州粤芯半导体技术有限公司 | Method for manufacturing semiconductor device |
| CN111863611B (en) * | 2020-07-30 | 2022-02-08 | 广州粤芯半导体技术有限公司 | Method for manufacturing semiconductor device |
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