CN106157920A - Power-off ghost shadow eliminates circuit, array base palte and driving method thereof - Google Patents

Power-off ghost shadow eliminates circuit, array base palte and driving method thereof Download PDF

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Publication number
CN106157920A
CN106157920A CN201610821478.XA CN201610821478A CN106157920A CN 106157920 A CN106157920 A CN 106157920A CN 201610821478 A CN201610821478 A CN 201610821478A CN 106157920 A CN106157920 A CN 106157920A
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CN
China
Prior art keywords
shadow
input
disappears
array base
base palte
Prior art date
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Pending
Application number
CN201610821478.XA
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Chinese (zh)
Inventor
蒲巡
李红敏
董职福
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Hefei BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201610821478.XA priority Critical patent/CN106157920A/en
Publication of CN106157920A publication Critical patent/CN106157920A/en
Pending legal-status Critical Current

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Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3674Details of drivers for scan electrodes
    • G09G3/3677Details of drivers for scan electrodes suitable for active matrices only
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00Control of display operating conditions
    • G09G2320/02Improving the quality of display appearance
    • G09G2320/0257Reduction of after-image effects

Abstract

The present invention provides a kind of power-off ghost shadow to eliminate circuit, array base palte and driving method thereof, belongs to Display Technique field, and it can solve the problem that power-off ghost shadow easily occurs in existing display device.The power-off ghost shadow of the present invention eliminates circuit and includes disappear shadow input block and multiple shadow unit that disappears, wherein, the described shadow unit that disappears has input and outfan, and for being turned on outfan by input when input is Continuity signal, is cut off with outfan by input when input is non-through signal;Disappear the outfan of shadow unit for the grid line connecting on array base palte described in each;The described shadow input block that disappears connects the input of the shadow unit that respectively disappears, and includes control signal end, and it is for providing Continuity signal to the input of the shadow unit that respectively disappears under the control of control signal end.

Description

Power-off ghost shadow eliminates circuit, array base palte and driving method thereof
Technical field
The invention belongs to Display Technique field, be specifically related to a kind of power-off ghost shadow and eliminate circuit, array base palte and driving thereof Method.
Background technology
Being provided with gate driver circuit in the array base palte of GOA (Gate On Array) pattern, gate driver circuit is by many The shift register composition of individual cascade, each shift register and a grid line connect.Under the driving of a few signal, grid Each shift register in the drive circuit of pole can export Continuity signal in turn, it is achieved the driving to grid line.
Shift register in gate driver circuit uses the mode worked step by step, will shut down and (include closing display Device) time, shift registers the most at different levels can only simultaneously close off.Therefore, all there is no signal, each picture time to be shut down on each grid line In the pixel electrode of element, the electric charge of storage cannot discharge, and can cause power off afterimage phenomenon.
Summary of the invention
The present invention solves the problem that power-off ghost shadow easily occurs in existing display device, it is provided that a kind of power-off ghost shadow of avoiding Power-off ghost shadow eliminates circuit, array base palte and driving method thereof.
Solving the technology of the present invention problem and be employed technical scheme comprise that a kind of power-off ghost shadow elimination circuit, it shadow that includes disappearing is defeated Enter unit and multiple shadow unit that disappears, wherein,
The described shadow unit that disappears has input and an outfan, and for when input is Continuity signal by input with defeated Go out end conducting, when input is non-through signal, input is cut off with outfan;Disappear described in each shadow unit outfan use In the grid line connected on array base palte;
The described shadow input block that disappears connects the input of the shadow unit that respectively disappears, and includes control signal end, and it is for controlling Continuity signal is provided to the input of the shadow unit that respectively disappears under the control of signal end.
Preferably, described control signal end is directly connected to respectively to disappear the input of shadow unit.
Preferably, the shadow input block that disappears described in also includes Continuity signal end, control transistor, wherein, described control crystalline substance First pole of body pipe connects Continuity signal end, and the second pole connects the input of the shadow unit that respectively disappears, grid connection control signal end.
Preferably, the shadow unit that disappears described in includes the first transistor and transistor seconds, wherein, described the first transistor First pole and grid connect the shadow input block that disappears, and the second pole connects the first pole and the grid of transistor seconds;Described second crystal Second pole of pipe is used for connecting grid line.
The shadow unit that disappears described in it may further be preferable that also includes electric capacity, and it is single that the first pole of described electric capacity connects the shadow input that disappears Unit, the second pole connects the second pole of the first transistor.
Solve the technology of the present invention problem and be employed technical scheme comprise that a kind of array base palte, comprising:
A plurality of grid line and data wire;
Gate driver circuit, it includes the shift register of multiple cascade, each depositor one grid line of connection;
Above-mentioned power-off ghost shadow eliminates circuit.
Preferably, described array base palte is the array base palte of liquid crystal indicator.
Preferably, one end of each described grid line is simultaneously connected with disappear shadow unit and a shift register.
Preferably, one end of each described grid line connects the shadow unit that disappears, and the other end connects a shift register.
Solve the technology of the present invention problem and be employed technical scheme comprise that the driving method of a kind of array base palte, described array base Plate is above-mentioned array base palte, and its driving method includes:
When described array base palte will be closed, control the signal of described control signal end, make described in disappear shadow input block Continuity signal is provided to the input of the shadow unit that respectively disappears;Meanwhile, discharge signal is provided to each described data wire.
The power-off ghost shadow of the present invention eliminates in circuit, as long as the shadow input block that controls to disappear time to be shut down provides leading in short-term Messenger, Continuity signal can be introduced each grid line, make the transistor turns being connected with grid line in each pixel by the shadow unit that respectively disappears;With Time, as long as data wire provides discharge signal in short-term, in the most each pixel, the electric charge of storage can be discharged into data by transistor On line, thus avoid power-off ghost shadow problem;And when normally showing, what the shadow input block that disappears provided is not Continuity signal, therefore respectively Disappearing what shadow unit was off, each grid line will not be by mutual conduction.
Accompanying drawing explanation
Fig. 1 is the structural schematic block diagram of a kind of power-off ghost shadow elimination circuit of embodiments of the invention;
Fig. 2 is the structural schematic block diagram of the another kind of power-off ghost shadow elimination circuit of embodiments of the invention;
Fig. 3 is the circuit diagram of a kind of power-off ghost shadow elimination circuit of embodiments of the invention;
Fig. 4 is the circuit diagram of the another kind of power-off ghost shadow elimination circuit of embodiments of the invention;
Fig. 5 is the signal timing diagram of the power-off ghost shadow elimination circuit of Fig. 3;
Fig. 6 is the signal timing diagram of the power-off ghost shadow elimination circuit of Fig. 4;
Wherein, reference is: C, electric capacity;M, control transistor;M1, the first transistor;M2, transistor seconds;CON、 Control signal end;VGH, Continuity signal end.
Detailed description of the invention
For making those skilled in the art be more fully understood that technical scheme, below in conjunction with the accompanying drawings and specific embodiment party The present invention is described in further detail by formula.
Embodiment 1:
As shown in Figures 1 to 6, the present embodiment provides a kind of power-off ghost shadow to eliminate circuit, it include disappearing shadow input block and Multiple shadow unit that disappear, wherein,
The shadow unit that disappears has input and outfan, and is used for input and outfan when input is Continuity signal Conducting, cuts off input with outfan when input is non-through signal;The outfan of each shadow unit that disappears is for connecting battle array A grid line on row substrate;
The shadow input block that disappears connects the input of the shadow unit that respectively disappears, and includes control signal end CON, and it is for controlling letter Number end CON control under to the shadow unit that respectively disappears input provide Continuity signal.
As shown in Figure 1 and Figure 2, the power-off ghost shadow of the present embodiment eliminates in circuit, and the shadow input block that disappears is equivalent to by respectively disappearing Shadow unit connects each grid line respectively;And the shadow unit class that disappears is similar to switch, it is that Continuity signal (can make transistor when input is therein The signal of conducting) time the shadow unit that disappears in the conduction state, when input therein be other signal time the shadow unit that disappears be in, locate In off state.
The power-off ghost shadow of the present embodiment eliminates in circuit, as long as the shadow that controls (when array base palte is closed) to disappear time to be shut down is defeated Entering unit and provide in short-term the Continuity signal of (number microsecond), Continuity signal can be introduced each grid line, make each pixel by the shadow unit that respectively disappears In be connected with grid line transistor (switching transistor that finger grid is connected with grid line) conducting;Meanwhile, as long as data wire provides short Time discharge signal (signal of the release of electric charge in pixel can be made, can be low-voltage signal or 0 level signal), in the most each pixel (as In pixel electrode) electric charge that stores can be discharged on data wire by transistor, thus avoid power-off ghost shadow problem;And just When often showing, what the shadow input block that disappears provided is not Continuity signal, therefore respectively disappears what shadow unit was off, and each grid line will not be by mutually Conducting.
By the way of above, as long as setting up simple circuit, the effect eliminating power-off ghost shadow can be played.
Preferably, as a kind of mode of the present embodiment, control signal end CON is directly connected to respectively to disappear the input of shadow unit End.
As it is shown on figure 3, disappear, shadow input block can only include control signal end CON, and the signal of this control signal end CON can lead to Cross the signal source input that control chip etc. is additional, and control signal end CON is directly connected to respectively to disappear the input of shadow unit.So, To shut down can by control chip to control signal end CON input Continuity signal, other time then input non-conduction signal (as without input).The structure of this shadow input block that disappears is the simplest, it is easy to accomplish.
Preferably, as the another way of the present embodiment, the shadow input block that disappears also includes Continuity signal end VGH, control Transistor M, wherein, the first pole controlling transistor M connects Continuity signal end VGH, and the second pole connects the input of the shadow unit that respectively disappears End, grid connection control signal end CON.
As shown in Figure 4, the shadow input block that disappears can also include controlling transistor M and Continuity signal end VGH, Continuity signal end VGH is for persistently providing Continuity signal, and it can be the high level end etc. in array base palte;Control signal end CON is then for right The state controlling transistor M is controlled, thus decides whether to introduce Continuity signal the input of the shadow unit that respectively disappears.It is visible, The signal of this control signal end CON input is only with controlling a transistor, therefore its load is low, and signal intensity need not very big (conducting In array base palte, this just has signal end VGH and intensity is enough, therefore does not has problem above).
Preferably, the shadow unit that disappears includes the first transistor M1 and transistor seconds M2, wherein, the first of the first transistor M1 Pole and grid connect the shadow input block that disappears, and the second pole connects the first pole and the grid of transistor seconds M2;Transistor seconds M2's Second pole is used for connecting grid line.
As shown in Figure 3, Figure 4, the shadow unit that disappears can include two transistors, and when its input is Continuity signal, first is brilliant Continuity signal is introduced the grid of transistor seconds M2 by body pipe M1 conducting, and transistor seconds M2 is also switched on, thus the shadow unit that disappears Input turns on outfan, and Continuity signal is introduced grid line;And in other conditions, the input of the shadow unit that disappears is not conducting Signal, therefore two transistors are turned off, and owing to there are two transistors, therefore do not have the problems such as electric leakage yet, it is ensured that aobvious That shows is normally carried out.
Preferably, the shadow unit that disappears also includes that first pole of electric capacity C, electric capacity C connects and disappears shadow input block, and the second pole connects the Second pole of one transistor M1.
As shown in Figure 3, Figure 4, an electric capacity C also can be had in parallel with above the first transistor M1, so to energy during shutdown The Continuity signal time the shortest (as due to the restriction of control chip) provided, then electric capacity C can disappear at the Continuity signal of external world's input After mistake, maintaining input within a period of time is Continuity signal, to extend the ON time of the shadow unit that disappears, namely extends pixel Discharge time, thus play the shadow effect that preferably disappears.
The present embodiment also provides for a kind of array base palte, comprising:
A plurality of grid line and data wire;
Gate driver circuit, it includes the shift register of multiple cascade, each depositor one grid line of connection;
Above-mentioned power-off ghost shadow eliminates circuit.
The array base palte of the present embodiment includes grid line and data wire, and wherein, each grid line is driven by gate driver circuit, therefore This array base palte is GOA pattern.Meanwhile, array base palte also including, above power-off ghost shadow eliminates circuit, thus, array base palte Every grid line disappear shadow unit the most above-mentioned with a shift register and be connected.
Preferably, array base palte is the array base palte of liquid crystal indicator.
In liquid crystal indicator, pixel relies primarily on the storage (as stored) electricity in pixel electrode by storage electric capacity Lotus shows, if the electric charge in its pixel electrode can not discharge, then power-off ghost shadow problem ratio is more serious, therefore above power-off ghost shadow Eliminate circuit to be preferred in the array base palte of liquid crystal indicator.
Preferably, as a kind of mode of the present embodiment, one end of each grid line is simultaneously connected with the shadow unit and that disappears Individual shift register.
It is to say, as it is shown in figure 1, gate driver circuit and power-off ghost shadow eliminate circuit can be located at the same of array base palte Side, therefore one end of grid line is simultaneously connected with shift register and the shadow unit that disappears.So side of array base palte does not has extra circuit, Also additional space need not be flowed out.
Preferably, as the another way of the present embodiment, one end of each grid line connects the shadow unit that disappears, the other end Connect a shift register.
As in figure 2 it is shown, gate driver circuit and power-off ghost shadow eliminate circuit also can be respectively arranged on array base palte both sides, therefore move Bit register and the shadow unit that disappears are connected to grid line two ends.So, two kinds of circuit are separate, each with enough settings Space, will not collide with each other.
The present embodiment also provides for the driving method of a kind of above-mentioned array base palte, comprising: when array base palte will be closed, Control the signal of this control signal end CON, the shadow input block input offer Continuity signal to the shadow unit that respectively disappears that disappears is provided;With Time, provide discharge signal to each data wire.
It is to say, when shutting down (close such as system or press the button closing display, so that array Substrate enters idle state), then can input, to control signal end CON, the signal that specify by control chip, the shadow that makes to disappear is defeated Enter unit and the transistor turns being connected with grid line in Continuity signal, and then each pixel is provided to the input of the shadow unit that respectively disappears.
Meanwhile, provide discharge signal by data driving chip (Data Driver IC) to each data wire, the lowest Level signal or 0 level signal, make the electric charge of storage in each pixel be discharged on data wire, eliminate power-off ghost shadow.
Wherein, Continuity signal, control signal concrete form relevant to circuit structure, transistor types etc..Below with institute Having transistor is all to be introduced as a example by N-type transistor, and Continuity signal is high level signal in the case.
Concrete, circuit is eliminated for above control signal end CON be directly connected to respectively the to disappear power-off ghost shadow of shadow unit, can be such as Shown in Fig. 5, when normally showing, control signal end CON input low level signal;Signal end CON is controlled then time to be shut down The high level signal (Continuity signal) of input number microsecond.
Concrete, the power-off ghost shadow above control signal end CON being connected to control to transistor M grid eliminates circuit, The most as shown in Figure 6, Continuity signal end VGH persistently provides high level signal (Continuity signal), and control signal end CON is normal aobvious Input low level signal when showing, inputs the high level signal of number microsecond time to be shut down, so that controlling transistor M conducting.
Certainly, described above is all transistors and be the situation of N-type transistor, if all transistors are p-shaped crystalline substance Body pipe, the low and high level of the most all above signal exchanges.
It is understood that the principle that is intended to be merely illustrative of the present of embodiment of above and the exemplary enforcement that uses Mode, but the invention is not limited in this.For those skilled in the art, in the essence without departing from the present invention In the case of god and essence, can make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention.

Claims (10)

1. a power-off ghost shadow eliminates circuit, it is characterised in that include disappear shadow input block and multiple shadow unit that disappears, wherein,
The described shadow unit that disappears has input and outfan, and is used for input and outfan when input is Continuity signal Conducting, cuts off input with outfan when input is non-through signal;Disappear the outfan of shadow unit for even described in each Connect a grid line on array base palte;
The described shadow input block that disappears connects the input of the shadow unit that respectively disappears, and includes control signal end, and it is in control signal Continuity signal is provided to the input of the shadow unit that respectively disappears under the control of end.
Power-off ghost shadow the most according to claim 1 eliminates circuit, it is characterised in that
Described control signal end is directly connected to respectively to disappear the input of shadow unit.
Power-off ghost shadow the most according to claim 1 eliminates circuit, it is characterised in that described in the shadow input block that disappears also include leading Messenger end, control transistor, wherein,
First pole of described control transistor connects Continuity signal end, and the second pole connects the input of the shadow unit that respectively disappears, and grid is even Connect control signal end.
Power-off ghost shadow the most according to claim 1 eliminates circuit, it is characterised in that described in the shadow unit that disappears include first crystal Pipe and transistor seconds, wherein,
First pole of described the first transistor and grid connect the shadow input block that disappears, and the second pole connects the first pole of transistor seconds And grid;
Second pole of described transistor seconds is used for connecting grid line.
Power-off ghost shadow the most according to claim 4 eliminates circuit, it is characterised in that described in the shadow unit that disappears also include electric capacity, First pole of described electric capacity connects the shadow input block that disappears, and the second pole connects the second pole of the first transistor.
6. an array base palte, it is characterised in that including:
A plurality of grid line and data wire;
Gate driver circuit, it includes the shift register of multiple cascade, each depositor one grid line of connection;
In claim 1 to 5, the power-off ghost shadow described in any one eliminates circuit.
Array base palte the most according to claim 6, it is characterised in that
Described array base palte is the array base palte of liquid crystal indicator.
Array base palte the most according to claim 6, it is characterised in that
One end of each described grid line is simultaneously connected with disappear shadow unit and a shift register.
Array base palte the most according to claim 6, it is characterised in that
One end of each described grid line connects the shadow unit that disappears, and the other end connects a shift register.
10. the driving method of an array base palte, it is characterised in that described array base palte is any one in claim 6 to 9 Described array base palte, its driving method includes:
When described array base palte will be closed, control the signal of described control signal end, make described in disappear shadow input block to respectively Disappear shadow unit input provide Continuity signal;Meanwhile, discharge signal is provided to each described data wire.
CN201610821478.XA 2016-09-13 2016-09-13 Power-off ghost shadow eliminates circuit, array base palte and driving method thereof Pending CN106157920A (en)

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Application publication date: 20161123