CN106157905A - buffer, data drive circuit and display device - Google Patents
buffer, data drive circuit and display device Download PDFInfo
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- CN106157905A CN106157905A CN201510206746.2A CN201510206746A CN106157905A CN 106157905 A CN106157905 A CN 106157905A CN 201510206746 A CN201510206746 A CN 201510206746A CN 106157905 A CN106157905 A CN 106157905A
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Abstract
A kind of buffer includes input circuit, observation circuit and output circuit.Input circuit receives input signal, and observation circuit is electrically connected with input circuit, and compares and output switching signal input signal and reference voltage.Output circuit has signal output part, and it is electrically connected with this input circuit and this observation circuit, output circuit selection gist the first high working voltage and first low-work voltage according to the state of switching signal, or according to the second high working voltage and the second low-work voltage, and by input signal as output signal from the output of this signal output part, wherein the current potential of this output signal is between this first high working voltage and this first low-work voltage, or between this second high working voltage and this second low-work voltage.
Description
Technical field
The present invention relates to a kind of buffer, particularly to the buffer of a kind of data drive circuit.
Background technology
The liquid crystal material that display floater Chang Yinqi uses does not matches that with the internal resistance of data drive circuit, it is impossible to provide up
The magnitude of voltage of suitable LCD penetration, causes part gray-scale signal cannot level off to preferable gamma curve, therefore need to be by
Revise gamma voltage and improve picture image.
Fig. 1 is the schematic diagram of the data drive circuit of known technology and buffer thereof, refer to Fig. 1, at present on the market
Some data driving chip, its application specification can include two gamma buffer, and gamma build-out resistor RU1,
RU2, RU3, RU4, RD1, RD2, RD3 and RD4, here, with four data driving chip IC1～IC4
As a example by, in Fig. 1, the input signal of these data driving chip described is indicated briefly as Vin, these data described
Gamma build-out resistor RU1～RU4 and the RD1～RD4 of driving chip IC1, IC2, IC3 and IC4 is 11K
Ohm, is additionally, since four data driving chip IC1～IC4 and shares gamma compensation voltage, therefore its gamma coupling
Resistance RU1～RU4 and RD1～RD4 is parallel connection, and its equivalent resistance is 11K/4 ohm.Just as in figure 2 it is shown,
Which is the data drive circuit of Fig. 1 and the rough schematic view of buffer thereof.Refer to Fig. 2, data drive circuit includes
There is multiple gamma buffer, the respectively first gamma buffer the 11st, the second gamma buffer the 12nd, the 3rd gamma buffering
Device 13 and the 4th gamma buffer 14, gamma build-out resistor RU of data driving chip IC1～IC4 in Fig. 1
And the equivalent resistance of RD, represent with the first impedance R1A and the second impedance R2A in Fig. 2, therefore the first resistance
The resistance value of anti-R1A and the second impedance R2A is 11K/4 ohm.
These gamma buffer described 11st, the 12nd, the operating voltage of 13 and 14 be all 16V and 0V, and gamma buffering
Device the 11st, the 12nd, 13 and 14 input signal Vin1A, Vin2A, Vin3A and Vin4A be respectively 15.8V,
8.2V, 7.8V and 0.23V.Gamma buffer the 11st, the 12nd, 13 and 14 output signal Vout1A, Vout2A,
Vout3A and Vout4A is then respectively 15.8V, 8.2V, 7.8V and 0.23V (namely gamma compensation voltage).
In FIG, the first impedance R1A is between the output of first gamma buffer the 11 to the second gamma buffer 12
Equiva lent impedance, the second impedance R2A is then the output of the 3rd gamma buffer 13 to the 4th gamma buffer 14
Equiva lent impedance between end, and the resistance value of the first impedance R1 and the second impedance R2A is 11K/4.Therefore, flow
Through the first impedance R1A and the second impedance R2A electric current IR1A and IR2A be respectively (15.8V-8.2V)/
(11K/4) and (7.8V-0.23V)/(11K/4), it is about 2.76 milliamperes.Wherein, the first gamma delays
Rush the power being consumed on device 11, be that the cross-pressure (16V-15.8V) on the first gamma buffer 11 is multiplied by electric current IR1A
(2.76mA) it, is (16V-15.8V) * 2.76mA, about 0.552mW；Second gamma buffer 12 institute
The power consuming, is (8.2V-0V) * 2.76mA, about 22.6mW；Consumed on 3rd gamma buffer 13
Power, be (16V-7.8V) * 2.76mA, about 22.632mW；And the 4th gamma buffer 14 is consumed
Power, be (0.23V-0V) * 2.76mA, about 0.552mW.From the foregoing, the second gamma buffer
12 and the 3rd power of being consumed of gamma buffer 13, it is much larger than the first gamma buffer 11 and the 4th gamma buffering
Device 14, therefore can cause the consumption of whole circuit power to be substantially improved.In addition, because known circuits power consumption is relatively big,
And have overheated problem.
Therefore, how to provide a kind of buffer, the power attenuation carrying out being caused during gamma compensation can be reduced, become
For one of important topic.
Content of the invention
Because above-mentioned problem, the purpose of the present invention can effectively reduce work(when carrying out gamma compensation for providing one
The buffer of rate loss and data drive circuit and display device.
For reaching above-mentioned purpose, according to a kind of buffer of the present invention.Buffer include input circuit, observation circuit with
And output circuit.Input circuit receives input signal.Observation circuit system is electrically connected to input circuit, and believes input
Number compare and output switching signal with reference voltage.Output circuit has signal output part, and is electrically connected to defeated
Enter circuit and observation circuit.Output circuit selection gist first high working voltage and first according to the state of switching signal
Low-work voltage, or according to the second high working voltage and the second low-work voltage, and by input signal as output signal
And from signal output part output, wherein the current potential of output signal between the first high working voltage and the first low-work voltage it
Between, or between the second high working voltage and the second low-work voltage.
In one embodiment, output circuit includes circuit for providing voltage, the first operating voltage selection circuit and
Two operating voltage selection circuits.Circuit for providing voltage system is electrically connected to input circuit and signal output part, and voltage provides
Circuit provides the first operation voltage and the second operation voltage, and produces output signal according to input signal.First work
Voltage selecting circuit is electrically connected to circuit for providing voltage and observation circuit, and is electrically connected to signal output part.When opening
When OFF signal is the first state, the first operating voltage selection circuit is according between described first operation voltage and output signal
Voltage difference, and the voltage difference between output signal and the second operation voltage and to make input circuit be electrically connected with first high
Operating voltage and the first low-work voltage, and make output signal between the first high working voltage and the first low-work voltage
Between.Second operating voltage selection circuit is electrically connected to circuit for providing voltage and observation circuit, and is electrically connected to letter
Number output, when switching signal is the second state, the second operating voltage selection circuit is according to output signal and the first behaviour
Make the voltage difference between the voltage difference between voltage, and the second operation voltage and output signal and make input circuit electrical
Connect the second high working voltage and the second low-work voltage, and make output signal between the second high working voltage and second
Between low-work voltage.
In one embodiment, observation circuit includes comparator and phase inverter.Comparator receives input signal and ginseng
Examine voltage, and the two is compared and produces switching signal.Phase inverter is electrically connected to the output of comparator, connects
Receive switching signal, the inversion signal of output switching signal.Wherein, output circuit is according to switching signal and switching signal
The state of inversion signal and selection gist the first high working voltage and the first low-work voltage, or according to the second high workload electricity
Pressure and the second low-work voltage.
In one embodiment, the first low-work voltage is equal to the second high working voltage.
In one embodiment, the voltage difference of the first high working voltage and the first low-work voltage is equal to the second high workload electricity
Pressure and the voltage difference of the second low-work voltage.
In one embodiment, output signal is gamma compensation voltage signal.
For reaching above-mentioned purpose, according to a kind of data drive circuit of the present invention, it is applicable to display device, data-driven
Circuit includes circuit board, the first gamma buffer and the second gamma buffer.First gamma buffer is configured at institute
Stating on circuit board, and having the first signal input part and the first signal output part, the first gamma buffer is from the first signal
Input receives the first input signal, and the first gamma buffer is according to the first high working voltage and the first low-work voltage
And the first input signal is exported from the first signal output part as the first gamma compensation voltage signal, wherein the first gamma
The current potential of compensation voltage signal is between the first high working voltage and the first low-work voltage.Second gamma buffer is joined
Being placed on described circuit board, and having secondary signal input and secondary signal output, the second gamma buffer is from
Binary signal input receives the second input signal, and the second gamma buffer is according to the second high working voltage and the second low work
Make voltage and the second input signal is exported from secondary signal output as the second gamma compensation voltage signal, Qi Zhong
The current potential of two gamma compensation voltage signals is between the second high working voltage and the second low-work voltage.
In one embodiment, data drive circuit also includes multiple data drive unit, and the first gamma buffer and
Second gamma buffer is positioned in identical or different data drive unit.
In one embodiment, the first low-work voltage is equal to described second high working voltage.
In one embodiment, the voltage difference of the first high working voltage and the first low-work voltage is equal to the second high workload electricity
Pressure and the voltage difference of the second low-work voltage.
For reaching above-mentioned purpose, according to a kind of display device of the present invention, include display floater and data drive circuit.
Data drive circuit is electrically connected to display floater.Data circuit includes circuit board, the first gamma buffer and
Two gamma buffer.First gamma buffer is configured on circuit board, and has the first signal input part and the first signal
Output, the first gamma buffer receives the first input signal from the first signal input part, and the first gamma buffer depends on
According to the first high working voltage and the first low-work voltage by the first input signal as the first gamma compensation voltage signal
From the first signal output part output, wherein the current potential of the first gamma compensation voltage signal is between the first high working voltage and the
Between one low-work voltage.Second gamma buffer is configured on circuit board, and has secondary signal input and second
Signal output part, the second gamma buffer receives the second input signal, and the second gamma buffering from secondary signal input
Device according to the second high working voltage and the second low-work voltage by the second input signal as the second gamma compensation voltage
Signal exports from described secondary signal output, and wherein the current potential of the second gamma compensation voltage signal is between the second high workload
Between voltage and the second low-work voltage.
In one embodiment, data drive circuit also includes multiple data drive unit, and described first gamma buffers
Device and described second gamma buffer are positioned in identical or different data drive unit.
In one embodiment, the first low-work voltage is equal to the second high working voltage.
In one embodiment, the voltage difference of the first high working voltage and the first low-work voltage is equal to the second high workload electricity
Pressure and the voltage difference of the second low-work voltage.
In one embodiment, display floater is display panels or organic LED display panel.
In sum, the buffer of the present invention is by selecting different operating voltage range, reduces power attenuation, also makes tool
The data drive circuit having multiple described buffer can avoid part buffer to produce overheated situation because cross-pressure is excessive,
And then reduce the power consumption of the display device using described data drive circuit.
Brief description
Fig. 1 is the schematic diagram of the data drive circuit of known technology and buffer thereof.
Fig. 2 is the rough schematic view of the data drive circuit of Fig. 1 known technology and buffer thereof.
Fig. 3 is the circuit diagram of a kind of buffer of the preferred embodiment of the present invention.
Fig. 4 is the schematic diagram of a kind of data drive circuit of the preferred embodiment of the present invention.
Fig. 5 is the relation curve schematic diagram to input data for the gamma compensation voltage of display floater.
Fig. 6 is the schematic diagram of a kind of display device of the preferred embodiment of the present invention.
Detailed description of the invention
Hereinafter with reference to correlative type, illustrate a kind of buffer according to the preferred embodiment of the present invention, data drive circuit and
Display device, wherein identical assembly will be illustrated with identical reference marks.
Fig. 3 is the circuit diagram of a kind of buffer of the preferred embodiment of the present invention.For convenience of description, in described below
In, in figure, each transistor end points upward is the first end, and end points downward is the second end.Wherein, first
End or the second end can be respectively source terminal or drain end, below will no longer illustrate.In addition, the control lock of each assembly
The end points of pole or other specific uses is then otherwise indicated.
Refer to Fig. 3, buffer 2 includes input circuit the 21st, observation circuit 22 and output circuit 23.Input electricity
Road 21 is electrically connected with observation circuit 22 and output circuit 23, and observation circuit 22 also can be electrically connected with output circuit
23.In the present embodiment, output circuit 21 receives input signal Vin.In addition, input can be believed by observation circuit 22
Number Vin compares with reference voltage Vref, and output switching signal SWS1.Now, output circuit 23
Can according to the state of switching signal SWS1 selection gist the first high working voltage HV1 and the first low-work voltage
LV1, or according to the second high working voltage HV2 and the second low-work voltage LV2, and by input signal Vin as
Output signal Vout and export from output 230.Wherein, the voltage of output signal Vout is between the first high workload
Between voltage HV1 and the first low-work voltage LV1, or between the second high working voltage HV2 and the second low work
Between voltage LV2.
In the present embodiment, buffer 2 can utilize operational amplifier to realize.Therefore, in input circuit 21,
Can include the first N-type transistor MN1, the second N-type transistor MN2, the 3rd N-type transistor MN3,
4th N-type transistor MN4, the 5th N-type transistor MN5, the 6th N-type transistor MN6, the first p-type
Transistor MP1, the second P-type transistor MP2, the 3rd P-type transistor MP3, the 4th P-type transistor MP4,
5th P-type transistor MP5 and the 6th P-type transistor MP6.Above-mentioned N-type transistor and P-type transistor
All may utilize metal-oxide-semiconductor (MOS) (MOS) transistor to realize.Additionally, those skilled in the art are when knowing, above-mentioned
N-type semiconductor and P-type semiconductor can exchange, and have no effect on the spirit of the present invention, and same principle is also permissible
It is applied to following narration, therefore paragraphs below will not be described in great detail.
Continuing referring to Fig. 3, second end of the 3rd P-type transistor MP3 is electrically connected to the first P-type transistor
First end of MP1 and first end of the second P-type transistor MP2.Similarly, the 3rd N-type transistor MN3
The first end be electrically connected to the second end of the first N-type transistor MN1 and the second of the second N-type transistor MN2
End.First end of the 3rd P-type transistor MP3 is electrically connected to positive supply V+, and the 3rd N-type transistor MN3
The second end ground connection, wherein the current potential of positive supply V+ can (but being not limiting as) and the first high working voltage HV1
Current potential identical.Additionally, the gate of the 3rd P-type transistor MP3 is electrically connected with the first working bias voltage Vbias1,
The gate of the 3rd N-type transistor MN3 is then electrically connected with the second working bias voltage Vbias2.In addition, the first p-type
The gate of the gate of transistor MP1 and the first N-type transistor MN1 is electrically connected with, and is jointly electrically connected to
Output 230.Additionally, the gate of the second P-type transistor MP2 also gate with the second N-type transistor MN2
It is electrically connected with.First end of the first N-type transistor MN1 is electrically connected to the second of the 5th P-type transistor MP5
End, the first end of the second N-type transistor MN2 is then electrically connected to second end of the 4th P-type transistor MP4.
Additionally, second end of the first P-type transistor MP1 is electrically connected to the first end of the 5th N-type transistor MN5,
Second end of the second P-type transistor MP2 is then electrically connected to the first end of the 4th N-type transistor MN4.
In the present embodiment, the gate terminal of the second P-type transistor MP2 be the input 210 of input circuit 21 (also
It is operational amplifier wherein input), receive input signal Vin, and the gate of the second N-type transistor MN2
End is electrically connected with the gate terminal of the second P-type transistor MP2.Similarly, the gate of the first P-type transistor MP1
It is also electrically connected to the gate terminal (being also another input of operational amplifier) of the first N-type transistor MN1, and
And it is jointly electrically connected to the output 230 of buffer 2.Above-mentioned the first N-type transistor MN1, the second N-type
Transistor MN2, the 3rd N-type transistor MN3, the first P-type transistor MP1, the second P-type transistor MP2
Collectively constitute differential amplifier circuit with the 3rd P-type transistor MP3.
Continuing referring to Fig. 3, first end of the 4th P-type transistor MP4 and the 5th P-type transistor MP5 is common
It is coupled to above-mentioned positive supply V+, and the gate of the 4th P-type transistor MP4 and the 5th P-type transistor MP5
Gate be jointly electrically connected to and described 6th N-type transistor MN6 and described 6th P-type transistor MP6
First end.Wherein, second end of the 5th P-type transistor MP5 and the 6th N-type transistor MN6 and the 6th P
First end of transistor npn npn MP6 is electrically connected with, and second end of the 4th P-type transistor MP4 is then electrically connected to
Output circuit 23.
Accordingly, the second end of the 4th N-type transistor MN4 and the second end of the 5th N-type transistor MN5 are total to
With ground connection, and the jointly raw connection of the gate terminal of the 4th N-type transistor MN4 and the 5th N-type transistor MN5
The second end to the 6th P-type transistor MP6 and the 6th N-type transistor MN6.Wherein, the 5th N-type crystal
First end of pipe MN5 is electrically connected to the second end of the 6th P-type transistor MP6 and the 6th N-type transistor, and
First end of the 4th N-type transistor MN4 is then electrically connected to output circuit 23.In addition, the 6th P-type transistor
The gate of MP6 and the 6th N-type transistor MN6 is electrically connected with working bias voltage Vbias3 and Vbias4.Its
In, the 4th P-type transistor MP4, the 5th P-type transistor MP5, the 6th P-type transistor MP6, the 4th N
Transistor npn npn MN4, the 5th N-type transistor MN5 and the 6th N-type transistor MN6 system current mirroring circuit.
Observation circuit 22 is electrically connected with described input circuit 21, and includes comparator 221.Comparator 221
Input (such as positive input terminal) be electrically connected with input circuit 210 input 210, to receive input signal
Vin.In addition, another input of comparator 221 (e.g. negative input end) is then electrically connected with reference voltage Vref.
Consequently, it is possible to input signal Vin is compared by comparator 221 with reference voltage Vref, and from its output
230 output switching signal SWS1.In the present embodiment, observation circuit 22 also configures that phase inverter 222, its input
It is electrically connected with the output of comparator 221, receiving switching signal SWS1, and export phase-veversal switch signal
SWS2。
In this embodiment, output circuit 23 includes that the first operating voltage selection circuit the 231st, the second operating voltage selects
Circuit 232 and circuit for providing voltage 233.Circuit for providing voltage 233 includes floating current source the 2331st, the first electric capacity
Assembly C1 and one second capacitance component C2.In addition, the first operating voltage selection circuit 231 includes the 7th p-type
Transistor MP7, the 7th N-type transistor MN7, the first switch SW1, second switch SW2 and the 3rd
Switch SW3.Similarly, the second operating voltage selection circuit 232 include the 8th P-type transistor MP8, the 8th
N-type transistor MN8, the 4th switch SW4, the 5th switch SW5 and the 6th switch SW6.Wherein, first
Switch SW1, second switch SW2 and the 3rd switch SW3 simultaneously start, the 4th switch SW4, the 5th leave
Close SW5 and the 6th switch SW6 also for start simultaneously.In certain embodiments, first switch SW1, second
Switch SW2, the 3rd switch SW3, the 4th switch SW4, the 5th switch SW5 and the 6th switch SW6 can
To utilize MOS transistor to realize.
Described floating current source 2331 has the first end N1, the second end N2, the 3rd end N3 and the 4th end N4.
Second end of the first end N1 of floating current source 2331 and the 4th P-type transistor MP4 is electrically connected with, and floats
First end of the second end N2 of current source 2331 and the 4th N-type transistor MN4 is electrically connected with.Additionally, float
3rd end N3 of current source 2331 and the 4th end N4, connects first end and second of the first capacitance component C1 respectively
Second end of capacitance component C2.In addition, the of second end of the first capacitance component C1 and the second capacitance component C2
One end is electrically connected with, and is jointly electrically connected to signal output part 230.Wherein, floating current source 2331 is in
First end of one capacitance component C1 provides the first operation voltage Vop1, and in the second of the second capacitance component C2
End provides the second operation voltage Vop2.
In the first operating voltage selection circuit 231, first end of the 7th P-type transistor MP7 is electrically connected with first
High working voltage HV1, relatively, second end of the 7th N transistor MN7 is electrically connected with the first low-work voltage
LV1.Additionally, second end of the 7th P-type transistor MP7 is electrically connected with the first of the 7th N-type transistor MN7
End, and it is electrically connected to signal output part 230 through the 3rd switch SW3.In addition, the 7th P-type transistor
The gate of the gate of MP7 and the 7th N-type transistor MN7 is respectively through the first switch SW1 and second switch SW2
It is electrically connected with the described first operation voltage Vop1 and the second operation voltage Vop2.
Relatively, in the second operating voltage selection circuit 232, first end of the 8th P-type transistor MP8 is electrical
Connect the second high working voltage HV2, and second end of the 8th N transistor MN8 is electrically connected with the second low work electricity
Pressure LV2.Additionally, second end of the 8th P-type transistor MP8 is electrically connected with the of the 8th N-type transistor MN8
One end, and it is electrically connected to signal output part 230 through the 6th switch SW6.8th P-type transistor MP8
Gate and the 8th N-type transistor MN8 gate respectively through the 4th switch SW4 and the 5th switch SW5 electricity
Property connect first operation voltage Vop1 with second operate voltage Vop2.In the present embodiment, the second low-work voltage
LV2 can be earthing potential.
In the present embodiment, the current potential of the first low-work voltage LV1 and the current potential of the second high working voltage HV2 are permissible
It is identical, and the voltage difference of the first high working voltage HV1 and the first low-work voltage LV1, can be high with second
Voltage difference between operating voltage HV2 and the second low-work voltage LV2 is identical, but above-mentioned two voltage differences are formed
Voltage range do not overlap mutually.From another perspective, the potential value of the first low-work voltage LV1 is permissible
It is the half of the potential value of positive supply.For example, the first high working voltage HV1 can be 16V, and the first low work
Voltage LV1 (or second high working voltage HV2) can be then 8V.
Continuing referring to Fig. 3, the 3rd P-type transistor MP3 and the 3rd N-type transistor MN3 can be because biasing
The reason of Vbias1 and Vbias2 and be respectively turned on.When input signal Vin is electronegative potential, owing to the first p-type is brilliant
The gate terminal of body pipe MP1 and the second P-type transistor MP2 system can be because the characteristic of imaginary short, therefore input signal
Vin can be copied to the gate terminal of the first transistor MP1, therefore the first P-type transistor MP1 and the second p-type
Transistor MP2 can be switched on (Turn on), and the first N-type transistor MN1 and the second N-type transistor
MN2 then can close (Turn off), and output signal Vout also can be pulled to electronegative potential.Now, positive supply
The voltage of V+ can be applied to the first end of the 4th N-type transistor MN4 and the 5th N-type transistor MN5.Due to
First end of the 5th N-type transistor MN5 is electrically connected with gate terminal, therefore, and the 4th N-type transistor MN4
All can turn on the 5th N-type transistor MN5.In addition, the 6th P-type transistor MP6 and the 6th N-type crystal
The reason that pipe MN6 is applied in bias Vbias3 and Vbias4 due to gate also can turn on, therefore positive supply V+
Voltage also can be applied to the gate terminal of the 4th P-type transistor MP4 and the 5th P-type transistor MP5, and makes the 4th
P-type transistor MP4 and the 5th P-type transistor MP5 closes.Due to the 4th N-type transistor MN4 and the 5th
N-type transistor MN5 can form current-mirror structure, and therefore floating current source 2331 can produce electric current from the 3rd end N3,
And flowing through the second electric capacity C2 and the first electric capacity C1, the 4th end N4 thus resulting in floating current source 2331 is low
Current potential, the 3rd end N3 is then high potential.
On the other hand, owing to input signal Vin is electronegative potential, therefore comparator 221 can export and have the first state
Switching signal SWS1 of (e.g. electronegative potential, but do not limit) so that the 4th switch SW4, the 5th switch
SW5 and the 6th switch SW6 conducting, and the 8th N-type transistor MN8 and the 8th P-type transistor MP8 are also
Can turn on.Now, output signal Vout is electronegative potential, and low between the second high working voltage HV2 and second
Between operating voltage LV2.
Otherwise, if input signal Vin is high potential, the first P-type transistor MP1 and the second P-type crystal
Pipe MP2 can close, and the first N-type transistor MN1 and MN2 then can turn on.And with above institute input signal
On the contrary, the 4th N-type transistor MN4 and the 5th N-type transistor MN5 can be closed, and the 4th P-type transistor
MP4 and the 5th P-type transistor MP5 then can turn on, and also can form the structure of current mirror.Therefore, float
Current source 2331 can produce electric current from the 3rd end N3, and flows through the second electric capacity C1 and the first electric capacity C2 so that
3rd end N3 of floating current source 233 is electronegative potential, and the 4th end N4 system high potential.Further, since input letter
Number Vin is high potential, and therefore comparator 221 can export the switch letter with the second state (e.g. high potential)
Number SWS1 so that the first switch SW1, second switch SW2 and the 3rd switch SW3 can turn on, and the 7th
P-type transistor MP7 and the 7th N-type transistor MN7 also can turn on.Now, output signal Vout is pushed to
High potential, and can be between the first high working voltage HV1 and the first low-work voltage LV1.In the present embodiment
In, output signal Vout is gamma compensation voltage signal.
Referring to Fig. 4 and Fig. 5, Fig. 4 is the schematic diagram of a kind of data drive circuit 3 of the preferred embodiment of the present invention.
Fig. 5 is the relation curve schematic diagram to input data for the gamma compensation voltage of display floater.Data drive circuit 3 includes
Circuit board the 31st, the first gamma buffer the 311st, the second gamma buffer the 312nd, the 3rd gamma buffer 313 and the 4th
Gamma buffer 314, data drive circuit 3 can include multiple data drive unit, such as data drive unit 30.
In the present embodiment, data drive unit 30 includes the second gamma buffer 312 and the 3rd gamma buffer 313.
But, in other embodiment, the second gamma buffer 312 and the 3rd gamma buffer 313 may be located at not
It in same data drive unit, is not restricted in the present invention.Additionally, the first gamma buffer 311 and the 4th gamma delay
Rush device 314 and then belong to other data drive unit.In the present embodiment, the first gamma buffer 311 and the second gamma
It is electrically connected with through passive component (not shown) between the input of buffer 312, the 3rd gamma buffer 313 and the
Also being electrically connected with through passive component (not shown) between the input of four gamma buffer 314, above-mentioned passive component can
For impedance component, capacitance component or Inductive component, or other passive components.In the present embodiment, data-driven
Depending on gamma buffer quantity in unit can be according to actual demand, do not do other and limit.
Equiva lent impedance between the output signal end of the first gamma buffer 311 and the second gamma buffer 312 is the first resistance
Anti-R1A, and the equivalence resistance between the 3rd gamma buffer 313 and the output signal end of the 4th gamma buffer 314
Anti-then be the second impedance R2A.In the present embodiment, the resistance value of the first impedance R1A and the second impedance R2A is
11K/4 (refer to the narration of Fig. 1 and Fig. 2).In addition, the first gamma buffer 311 and the second gamma buffer
312 is to work according to the first high working voltage HV1 and the first low-work voltage LV1, relatively the 3rd gamma buffering
Device 313 and the 4th gamma buffer 314 are then according to the second high working voltage HV2 and the second low-work voltage LV2
Work, wherein the first high working voltage HV1 e.g. 16V, the first low-work voltage LV1 and the second high workload electricity
Pressure HV2 then e.g. 8V, the second low-work voltage LV2 can be ground connection.According to Fig. 4, the first gamma buffering
Input signal Vin1 and the Vin2 of device 311 and the second gamma buffer 312 are respectively 15.8V and 8.2V, and the 3rd
Input signal Vin3 of gamma buffer 313 and the 4th gamma buffer 314 and Vin4 be respectively 7.8V and
0.23V, therefore, output signal Vout1 of the first gamma buffer 311 and the second gamma buffer 312, Vout2
It is respectively 15.8V and 8.2V, output signal Vout3 of the 3rd gamma buffer 313 and the 4th gamma buffer 314,
Vout4 is respectively 7.8V and 0.23V.
In the present embodiment, flow through electric current IR1A and IR2A of the first impedance R1A and the second impedance R2A respectively
For (15.8V-8.2V)/(11K/4) and (7.8V-0.23V)/(11K/4), both are all about 2.76 milliamperes
Training, the power that the first gamma buffer 311 is consumed, is for (16V-15.8V) * 2.76mA, is about
0.552mW, the power that the second gamma buffer 312 is consumed, is for (8.2V-8V) * 2.76mA, is about
0.552mW, the power that the 3rd gamma buffer 313 is consumed, is for (8V-7.8V) * 2.76mA, is about
0.552mW, the power that the 4th gamma buffer 314 is consumed, is for (0.23V-0V) * 2.76mA, is about
0.552mW, the gamma buffer in notebook data drive circuit 3, altogether power consumption 2.208mW.The number of the present invention
According to the power (2.208mW) of drive circuit consumption than the power consumption (46.336mW) of well known data drive circuit,
About reduce 44.128mW.
Fig. 6 is the schematic diagram of a kind of display device 4 of the preferred embodiment of the present invention.Described display device 4 includes aobvious
Show panel the 41st, at least one data drive circuit 42 and at least one scan drive circuit 43.In the present embodiment,
Data drive circuit 42 includes multiple data drive unit, for example the 421st, the 422nd, 423 and 424, and these data
The 421st, driver element the 422nd, 423 and 424 all such as the data drive unit 30 in Fig. 3, includes at least one respectively
Individual gamma buffer.Data drive circuit 42 and data drive unit the 421st, the 422nd, the 423rd, 424 and gamma buffer
Structure and action narration, all with the data drive circuit in above-described embodiment, data drive unit and gal code buffer
Identical, repeat no more in this.In addition, described display floater 41 can be display panels (Liquid Crystal
Display Panel) or organic LED display panel (Organic Light Emitting Diode
Display Panel).In this example it is shown that panel 41 is display panels.Due to display panels
Framework well known, therefore repeat no more.
Wherein, scan drive circuit 43 is electrically connected with described display floater 41, and provides switch described display floater 41
In scanning signal needed for each pixel.In addition, data drive circuit 42 is electrically connected with display floater 41, to provide number
The number of it is believed that, and can be according to the first high working voltage HV1 and the first low-work voltage LV1 or the second high working voltage
The different operating voltage ranges such as HV2 and the second low-work voltage LV2 and produce gamma compensation voltage signal.Such one
Coming, the display device 4 that the present embodiment is provided can reduce power consumption and avoid overheating components, provides gamma to mend
Repay voltage signal to display floater 41, the display characteristic of display floater 41 described in reinforcement.
In sum, the buffer system of the present invention is by selecting different operating voltage range, reduces power attenuation, also makes
The data drive circuit with multiple buffer can avoid part buffer to produce overheated situation because cross-pressure is excessive, enters
And reduce the power consumption of the display device using described data drive circuit.
The foregoing is only illustrative, rather than restricted.Any without departing from spirit and scope of the invention, and right
Its equivalent modifications carrying out or change, be intended to be limited solely by appended claims scope.
Claims (15)
1. a buffer, comprising:
Input circuit, receives input signal；
Observation circuit, is electrically connected with described input circuit, and compares described input signal and reference voltage
Relatively output switching signal；And
Output circuit, has signal output part, and is electrically connected with described input circuit and described observation circuit,
Described output circuit is according to the state of described switching signal and selection gist the first high working voltage and the first low work
Make voltage, or according to the second high working voltage and the second low-work voltage, and by described input signal as defeated
Going out signal and exporting from described signal output part, the current potential of wherein said output signal is between described first senior engineer
Make between voltage and described first low-work voltage, or between described second high working voltage and described second low
Between operating voltage.
2. buffer according to claim 1, wherein said output circuit includes:
Circuit for providing voltage, is electrically connected with described input circuit and described signal output part, and described voltage provides
Circuit provides the first operation voltage and the second operation voltage, and produces described output according to described input signal
Signal；
First operating voltage selection circuit, is electrically connected with described circuit for providing voltage and described observation circuit, and
It is electrically connected with described signal output part, when described switching signal is the first state, described first operating voltage
Selection circuit is according to the voltage difference between described first operation voltage and described output signal, and described output
Signal and described second operates the voltage difference between voltage and makes described input circuit be electrically connected with the described first height
Operating voltage and described first low-work voltage, and make described output signal between described first high workload electricity
Between pressure and described first low-work voltage；And the second operating voltage selection circuit, it is electrically connected with described electricity
Pressure provides circuit and described observation circuit, and is electrically connected with described signal output part, when described switching signal is
During the second state, described second operating voltage selection circuit is according to described output signal and described first operation electricity
Voltage difference between pressure, and described second operation voltage and described output signal between voltage difference and make institute
State input circuit and be electrically connected with described second high working voltage and described second low-work voltage, and make described
Output signal is between described second high working voltage and described second low-work voltage.
3. buffer according to claim 1, wherein, described observation circuit includes:
Comparator, receives described input signal and described reference voltage, and compares the two and produce institute
State switching signal；And
Phase inverter, is electrically connected with the output of described comparator, receives described switching signal, and output switch is believed
Number inversion signal；
Wherein, described output circuit is according to the shape of described switching signal and the inversion signal of described switching signal
State and selection gist the first high working voltage and the first low-work voltage, or according to the second high working voltage and the
Two low-work voltages.
4. buffer according to claim 1, wherein, described first low-work voltage is equal to described the
Two high working voltages.
5. buffer according to claim 1, wherein, described first high working voltage and the first low work
The voltage difference making voltage is equal to the voltage difference of described second high working voltage and the second low-work voltage.
6. buffer according to claim 1, wherein, described output signal is gamma compensation voltage letter
Number.
7. a data drive circuit, it is adaptable to display device, described data drive circuit includes:
Circuit board；
First gamma buffer, is configured on described circuit board, and has the first signal input part and the first letter
Number output, described first gamma buffer receives the first input signal from described first signal input part, and
Described first gamma buffer inputs described first according to the first high working voltage and the first low-work voltage
Signal exports from described first signal output part as the first gamma compensation voltage signal, wherein said first gal
The current potential of agate compensation voltage signal be between described first high working voltage and described first low-work voltage it
Between；And
Second gamma buffer, is configured on described circuit board, and has secondary signal input and one second
Signal output part, described second gamma buffer receives the second input signal from described secondary signal input,
And described second gamma buffer according to the second high working voltage and the second low-work voltage by described second defeated
Enter signal to export from described secondary signal output as the second gamma compensation voltage signal, wherein said second
The current potential of gamma compensation voltage signal between described second high working voltage and described second low-work voltage it
Between.
8. data drive circuit according to claim 7, wherein said data drive circuit also includes many
Individual data drive unit, and described first gamma buffer and described second gamma buffer are positioned at identical or not
In same data drive unit.
9. data drive circuit according to claim 7, wherein, described first low-work voltage is equal to
Described second high working voltage.
10. data drive circuit according to claim 7, wherein, described first high working voltage and
The voltage difference of one low-work voltage is equal to the voltage difference of described second high working voltage and the second low-work voltage.
11. 1 kinds of display devices, comprising:
Display floater；And
Data drive circuit, is electrically connected with described display floater, and described data drive circuit includes:
Circuit board:
First gamma buffer, is configured at described circuit board, and has the first signal input part and
One signal output part, described first gamma buffer receives the first input signal from described first signal input part,
And described first gamma buffer according to the first high working voltage and the first low-work voltage by described first defeated
Enter signal to export from described first signal output part as the first gamma compensation voltage signal, wherein said first
The current potential of gamma compensation voltage signal between described first high working voltage and described first low-work voltage it
Between；And
Second gamma buffer, is configured at described circuit board, and has secondary signal input and
Binary signal output, described second gamma buffer receives the second input signal from described secondary signal input,
And described second gamma buffer according to the second high working voltage and the second low-work voltage by described second defeated
Enter signal to export from described secondary signal output as the second gamma compensation voltage signal, wherein said second
The current potential of gamma compensation voltage signal between described second high working voltage and described second low-work voltage it
Between.
12. display devices according to claim 11, wherein said data drive circuit also includes multiple
Data drive unit, and described first gamma buffer and described second gamma buffer are positioned at identical or different
Data drive unit in.
13. display devices according to claim 11, wherein, described first low-work voltage is equal to institute
State the second high working voltage.
14. display devices according to claim 11, wherein, described first high working voltage and first
The voltage difference of low-work voltage is equal to the voltage difference of described second high working voltage and the second low-work voltage.
15. display devices according to claim 11, wherein, described display floater is LCD
Plate or organic LED display panel.
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| CN201510206746.2A CN106157905B (en) | 2015-04-28 | 2015-04-28 | buffer, data drive circuit and display device |
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| CN201510206746.2A CN106157905B (en) | 2015-04-28 | 2015-04-28 | buffer, data drive circuit and display device |
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Cited By (1)
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| CN110473505A (en) * | 2018-05-09 | 2019-11-19 | 奇景光电股份有限公司 | Output buffer and source electrode driver |
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| US20110148893A1 (en) * | 2009-12-23 | 2011-06-23 | Samsung Electronics Co., Ltd. | Output buffer having high slew rate, method of controlling output buffer, and display driving device including output buffer |
| US20150103066A1 (en) * | 2011-10-07 | 2015-04-16 | Renesas Electronics Corporation | Output circuit, data driver and diplay device |
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| CN1822500A (en) * | 2005-02-18 | 2006-08-23 | 统宝光电股份有限公司 | Analog buffers and related signal driving circuit,electronic device |
| CN101286736A (en) * | 2008-05-21 | 2008-10-15 | 友达光电股份有限公司 | Buffer circuit and display |
| CN101888239A (en) * | 2009-05-13 | 2010-11-17 | 奇景光电股份有限公司 | Output buffer, source electrode driver and electronic system |
| US20110148893A1 (en) * | 2009-12-23 | 2011-06-23 | Samsung Electronics Co., Ltd. | Output buffer having high slew rate, method of controlling output buffer, and display driving device including output buffer |
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| CN106157905B (en) | 2018-09-28 |
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