CN106126453A - A kind of implementation method containing the CPU of interface in addition - Google Patents

A kind of implementation method containing the CPU of interface in addition Download PDF

Info

Publication number
CN106126453A
CN106126453A CN201610418677.6A CN201610418677A CN106126453A CN 106126453 A CN106126453 A CN 106126453A CN 201610418677 A CN201610418677 A CN 201610418677A CN 106126453 A CN106126453 A CN 106126453A
Authority
CN
China
Prior art keywords
cpu
interface
addition
implementation method
performance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610418677.6A
Other languages
Chinese (zh)
Inventor
陈立卫
孙连震
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Inspur Electronic Information Industry Co Ltd
Original Assignee
Inspur Electronic Information Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inspur Electronic Information Industry Co Ltd filed Critical Inspur Electronic Information Industry Co Ltd
Priority to CN201610418677.6A priority Critical patent/CN106126453A/en
Publication of CN106126453A publication Critical patent/CN106126453A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/382Information transfer, e.g. on bus using universal interface adapter
    • G06F13/387Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0024Peripheral component interconnect [PCI]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

The invention discloses a kind of implementation method containing the CPU of interface in addition, the method is to arrange a Peripheral Interface in the side of CPU, and by cable, the partial properties of CPU is drawn out to the outer interface of computer, reaches the purpose of extension CPU performance.Compared to the prior art a kind of implementation method containing the CPU of interface in addition of the present invention, can be drawn out to the outer interface of computer the partial properties of CPU by cable, it is easy to extend the performance of CPU, can be greatly improved utilization rate and the cost performance of CPU.

Description

A kind of implementation method containing the CPU of interface in addition
Technical field
The present invention relates to computer CPU technical field, a kind of implementation method containing the CPU of interface in addition.
Background technology
CPU (Central Processing Unit) on current market is that single CPU is placed on mainboard CPU base On, cpu signal is sent to each adapter (such as internal memory/PCI slot), chip (such as PCH) etc. by CPU base, and the performance of CPU is non- Often rely on motherboard design/type, greatly limit the extension of CPU and computing power.
Disclosed Patents file: entitled " cpu i/f converting system ", this document " proposes cpu i/f conversion System, this system includes: master chip, and for the request operated from chip being sent to modular converter, wherein, request is Write request or read request, in the case of request is write request, be also sent to conversion by being used for write from the first data of chip Module;Modular converter, modular converter is field programmable gate array, is used for carrying out master chip and the time domain between chip turns Change, will be converted to be suitable for the form from chip and by the request and first after conversion from the request of master chip and the first data Data are sent to from chip, and for will be converted to be suitable for the form of master chip from the second data read from chip and incite somebody to action The second data after conversion are sent to master chip;And from chip, in the case of request is write request, write is received The first data arrived, and in the case of request is read request, reads the second data thereon and the second data are sent out Give modular converter ".
Entitled " a kind of CPU analog and method ", this document " a kind of CPU that can verify that peripheral module designs Analog and method, it includes construction and performs a hardware description language simulation environment and a CPU simulation program, and wherein this is hard Part describes vorbal model environment and is activated with corresponding simulator, and still can perform CPU Yu a DUT command process interface mould Type and a CPU simulation program, and still can keep in data for command information by construction one information sequence.When CPU simulation program During with ancillary equipment generation import and export access request with the mutual-action behavior such as accreditation, interruptive command, the present invention may utilize program language Interface and CPU Yu DUT command process interface model, and the information sequence mechanism of job platform of can arranging in pairs or groups and signal signal machine System, is respectively completed the interactive simulation of ancillary equipment and CPU ".
File disclosed above to solve the technical problem that with present invention, and the technological means of employing is different from.
Summary of the invention
The technical assignment of the present invention is to provide a kind of implementation method containing the CPU of interface in addition.
The technical assignment of the present invention realizes in the following manner, and the method is to arrange a peripheral hardware to connect in the side of CPU Mouthful, and by cable, the partial properties of CPU is drawn out to the outer interface of computer, reach the purpose of extension CPU performance.
Described implementation method step is as follows:
1) design each functional unit of CPU;
2) necessary signals is introduced the contact surface of CPU Yu CPU base;
3) side at CPU arranges the Peripheral Interface that a CPU expanded function is drawn;
4), during extension CPU performance, use high speed signal bundle of lines CPU interface in addition by the outer interface of cable Import computer;
5) extension of cpu performance is realized by computer external socket.
Cable between the Peripheral Interface of described CPU and the outer interface of computer meets high speed signal demand.
A kind of implementation method containing the CPU of interface in addition of the present invention compared to the prior art, can be CPU by cable Partial properties be drawn out to the outer interface of computer, it is easy to extend the performance of CPU, the utilization rate of CPU can be greatly improved And cost performance.
Accompanying drawing explanation
Fig. 1 is a kind of schematic flow sheet containing the implementation method of the CPU of interface in addition.
Detailed description of the invention
Embodiment 1:
This implementation method step containing the CPU of interface in addition is as follows:
1) design each functional unit of CPU;
2) 10G network signal is introduced the contact surface of CPU Yu CPU base;
3) side at CPU arranges a Peripheral Interface introducing 10G network signal function;
4), during extension CPU performance, use high speed signal bundle of lines CPU interface in addition by the outer interface of cable Import computer, be somebody's turn to do Cable meets high speed signal demand;
5) extension of cpu performance is realized by computer external socket.
Embodiment 2:
This implementation method step containing the CPU of interface in addition is as follows:
1) design each functional unit of CPU;
2) PCIE is introduced the contact surface of CPU Yu CPU base;
3) side at CPU arranges a Peripheral Interface introducing PCIE function;
4), during extension CPU performance, use high speed signal bundle of lines CPU interface in addition by the outer interface of cable Import computer, be somebody's turn to do Cable meets high speed signal demand;
5) extension of cpu performance is realized by computer external socket.
By said method, the extension of cpu performance can be made not exclusively to rely on motherboard design, it is easy to extend CPU's Performance, is greatly improved cpu busy percentage and cost performance;Improve the versatility of cpu performance extension simultaneously.
By detailed description of the invention above, described those skilled in the art can readily realize the present invention.But should Working as understanding, the present invention is not limited to above-mentioned several detailed description of the invention.On the basis of disclosed embodiment, described technology The technical staff in field can the different technical characteristic of combination in any, thus realize different technical schemes.

Claims (3)

1. the implementation method containing the CPU of interface in addition, it is characterised in that the method is outside the side of CPU arranges If interface, and by cable, the partial properties of CPU is drawn out to the outer interface of computer, reach the purpose of extension CPU performance.
A kind of implementation method containing the CPU of interface in addition the most according to claim 1, it is characterised in that described realization Method step is as follows:
1) design each functional unit of CPU;
2) necessary signals is introduced the contact surface of CPU Yu CPU base;
3) side at CPU arranges the Peripheral Interface that a CPU expanded function is drawn;
4), during extension CPU performance, use high speed signal bundle of lines CPU interface in addition by the outer interface of cable Import computer;
5) extension of cpu performance is realized by computer external socket.
A kind of implementation method containing the CPU of interface in addition the most according to claim 1, it is characterised in that described CPU's Cable between Peripheral Interface and the outer interface of computer meets high speed signal demand.
CN201610418677.6A 2016-06-13 2016-06-13 A kind of implementation method containing the CPU of interface in addition Pending CN106126453A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610418677.6A CN106126453A (en) 2016-06-13 2016-06-13 A kind of implementation method containing the CPU of interface in addition

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610418677.6A CN106126453A (en) 2016-06-13 2016-06-13 A kind of implementation method containing the CPU of interface in addition

Publications (1)

Publication Number Publication Date
CN106126453A true CN106126453A (en) 2016-11-16

Family

ID=57269978

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610418677.6A Pending CN106126453A (en) 2016-06-13 2016-06-13 A kind of implementation method containing the CPU of interface in addition

Country Status (1)

Country Link
CN (1) CN106126453A (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060190656A1 (en) * 1997-10-17 2006-08-24 Acuity Imaging, Llc Flexible processing hardware architecture
CN101197851A (en) * 2008-01-08 2008-06-11 杭州华三通信技术有限公司 Method and system for implementing control of plane centralized type data plane distribution
CN202102433U (en) * 2011-05-16 2012-01-04 曙光信息产业股份有限公司 Device for expanding IO (input and output) bandwidth of dragon core CPU (central processing unit)
CN202771422U (en) * 2012-05-30 2013-03-06 曙光信息产业(北京)有限公司 Interconnection device for Godson 3 CPUs and chipsets
CN103543798A (en) * 2013-11-13 2014-01-29 鄢伟 Combined type computer allowing expanded use
CN104951268A (en) * 2015-06-12 2015-09-30 山东超越数控电子有限公司 Method for implementing extended high-performance graphics card based on CPCI
CN105513311A (en) * 2014-09-26 2016-04-20 青岛鑫益发工贸有限公司 Electric power system data acquisition device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060190656A1 (en) * 1997-10-17 2006-08-24 Acuity Imaging, Llc Flexible processing hardware architecture
CN101197851A (en) * 2008-01-08 2008-06-11 杭州华三通信技术有限公司 Method and system for implementing control of plane centralized type data plane distribution
CN202102433U (en) * 2011-05-16 2012-01-04 曙光信息产业股份有限公司 Device for expanding IO (input and output) bandwidth of dragon core CPU (central processing unit)
CN202771422U (en) * 2012-05-30 2013-03-06 曙光信息产业(北京)有限公司 Interconnection device for Godson 3 CPUs and chipsets
CN103543798A (en) * 2013-11-13 2014-01-29 鄢伟 Combined type computer allowing expanded use
CN105513311A (en) * 2014-09-26 2016-04-20 青岛鑫益发工贸有限公司 Electric power system data acquisition device
CN104951268A (en) * 2015-06-12 2015-09-30 山东超越数控电子有限公司 Method for implementing extended high-performance graphics card based on CPCI

Similar Documents

Publication Publication Date Title
CN201374060Y (en) IIC bus expanded system structure
CN102388357B (en) Method and system for accessing memory device
CN106502930B (en) The method and apparatus of GPIO simulation serial line interface based on windows platform
CN202421950U (en) External expanding unit for PCI (Peripheral Component Interconnect) bus board cards
CN103853642A (en) Injection type simulation system for infrared digital image based on USB3.0 and method thereof
CN107957970A (en) The means of communication and solid-state hard disk controller of a kind of heterogeneous polynuclear
CN104035903B (en) A kind of 2-D data based on Reconfiguration Technologies accesses dynamic self-adapting method
CN106126465B (en) A kind of data transmission method and device
CN104156238A (en) Burning method capable of increasing VR chip FW burning efficiency
CN103853135B (en) The method and apparatus for adjusting the access to slave unit
CN108153624B (en) Test circuit board suitable for NGFF slot
CN103699461A (en) Double-host machine mutual redundancy hot backup method
CN103150281A (en) Integrating method and device and authentication method and device for bus interconnecting module
CN106126453A (en) A kind of implementation method containing the CPU of interface in addition
CN210776403U (en) Server architecture compatible with GPUDirect storage mode
CN117148817A (en) Test system
CN105676726A (en) Serial peripheral interface (SPI)-based multi-MEMS sensor fast data access system and method
CN113496108B (en) CPU model applied to simulation
CN102591817A (en) Multi-bus bridge controller and implementing method thereof
CN210244341U (en) Multiprocessor simulation debugging development platform
CN104077080A (en) Memory access method, memory access control method, SPI flash memory device and controller thereof
CN107870878A (en) Storage system, terminal and computer installation
CN114021715A (en) Deep learning training method based on Tensorflow framework
CN114218138A (en) USB equipment simulation device and test system
CN204189089U (en) A kind of server

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20161116