CN106125604A - A kind of ECG signal processing system - Google Patents

A kind of ECG signal processing system Download PDF

Info

Publication number
CN106125604A
CN106125604A CN201610545370.2A CN201610545370A CN106125604A CN 106125604 A CN106125604 A CN 106125604A CN 201610545370 A CN201610545370 A CN 201610545370A CN 106125604 A CN106125604 A CN 106125604A
Authority
CN
China
Prior art keywords
signal
filter
pass filter
noise
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610545370.2A
Other languages
Chinese (zh)
Inventor
江伟
杨柳青
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
East China Institute of Technology
Original Assignee
East China Institute of Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by East China Institute of Technology filed Critical East China Institute of Technology
Priority to CN201610545370.2A priority Critical patent/CN106125604A/en
Publication of CN106125604A publication Critical patent/CN106125604A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423—Input/output
    • G05B19/0425—Safety, monitoring
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/24—Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
    • A61B5/316—Modalities, i.e. specific diagnostic methods
    • A61B5/318—Heart-related electrical modalities, e.g. electrocardiography [ECG]
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/26—Pc applications
    • G05B2219/2612—Data acquisition interface
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/26—Pc applications
    • G05B2219/2652—Medical scanner

Landscapes

  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Heart & Thoracic Surgery (AREA)
  • Surgery (AREA)
  • Biophysics (AREA)
  • Biomedical Technology (AREA)
  • Cardiology (AREA)
  • Medical Informatics (AREA)
  • Molecular Biology (AREA)
  • Pathology (AREA)
  • Animal Behavior & Ethology (AREA)
  • General Health & Medical Sciences (AREA)
  • Public Health (AREA)
  • Veterinary Medicine (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Measurement And Recording Of Electrical Phenomena And Electrical Characteristics Of The Living Body (AREA)

Abstract

The invention provides a kind of ECG signal processing system, this ECG signal processing system includes: signal amplifies Acquisition Circuit, AD sample circuit, FPGA circuitry, JTAG telecommunication circuit, and power circuit；Wherein, described FPGA circuitry includes: FIR low pass filter, is used for processing myoelectricity interference；Adaptive notch filter, is connected with described FIR low pass filter signal and is used for processing power frequency component interference；Self adaptation high pass filter, is connected with described adaptive notch filter signal and is used for processing baseline drift effect of noise.The invention has the beneficial effects as follows: according to noise behaviors such as myoelectricity interference, Hz noise, baseline drifts present in electrocardiosignal, propose employing FIR low pass filter and inhibit myoelectricity noise jamming, adaptive notch filter is used to eliminate Hz noise, and use self adaptation high pass filter to eliminate baseline drift, it is effectively improved the accuracy of ecg signal acquiring.

Description

A kind of ECG signal processing system
Technical field
The present invention relates to the technical field of ECG detecting, refer more particularly to a kind of ECG signal processing system.
Background technology
Cardiovascular disease has become as a class disease more typically, and the healthy of people in serious harm, from currently From the point of view of medical level, ECG signal sampling has started to be increasingly becoming prevention, diagnoses and treat the important skill of cardiovascular disease Art means.On clinical application, Electrocardiographic mode of operation is the most very convenient, simple, to human body be do not have any traumatic, The advantage there is diagnosis at any time simultaneously, following the tracks of the state of an illness in time.For doctor, want to further appreciate that the heart shape of patient Condition, and the disease occurred on patient's heart is carried out diagnosis and treatment, this detection all be unableing to do without electrocardiosignal and analysis.But, outward Boundary's environment is very big on the impact of electrocardiosignal, and electrocardiosignal shows non-stationary, nonlinear a kind of small-signal, typically comes Saying, its amplitude is substantially mV level, and frequency band range is among 0.07～100Hz this interval.Due to Hz noise, baseline drift The existence of the series of factors such as shifting, myoelectricity interference, often causes serious interference to electrocardiosignal.
Summary of the invention
The invention aims to overcome the deficiencies in the prior art, it is provided that a kind of ECG signal processing system.
The invention provides a kind of ECG signal processing system, this ECG signal processing system includes: signal amplifies The FPGA electricity that the AD sample circuit that Acquisition Circuit is connected with described signal amplification Acquisition Circuit is connected with described AD sample circuit The JTAG telecommunication circuit that road is connected with described FPGA circuitry, and give described signal amplify Acquisition Circuit, AD sample circuit, The power circuit that FPGA circuitry, JTAG telecommunication circuit are powered；Wherein, described FPGA circuitry includes:
FIR low pass filter, is used for processing myoelectricity interference；
Adaptive notch filter, is connected with described FIR low pass filter signal and is used for processing power frequency component interference；
Self adaptation high pass filter, is connected with described adaptive notch filter signal and is used for processing baseline drift noise Impact.
The invention has the beneficial effects as follows: present in foundation electrocardiosignal, myoelectricity interference, Hz noise, baseline drift etc. are made an uproar Sound feature, it is proposed that use FIR low pass filter to inhibit myoelectricity noise jamming, uses adaptive notch filter to eliminate power frequency and does Disturb, and use self adaptation high pass filter to eliminate baseline drift, be effectively improved the accuracy of ecg signal acquiring.
Accompanying drawing explanation
Fig. 1 is the structural representation of the ECG signal processing system that the embodiment of the present invention provides；
Fig. 2 is the structural representation of the FPGA circuitry that the embodiment of the present invention provides；
Fig. 3 is the FIR filter structure illustraton of model that the embodiment of the present invention provides；
Fig. 4 be the embodiment of the present invention provide FIR filter N be odd number h (n) be the linear junction composition of even symmetry；
Fig. 5 be the embodiment of the present invention provide FIR filter N be even number h (n) be the linear junction composition of even symmetry；
Fig. 6 is the parallel DA structural representation that the embodiment of the present invention provides；
Fig. 7 is the serial D A structural representation that the embodiment of the present invention provides；
Fig. 8 is the modified model DA structural representation that the embodiment of the present invention provides；
Fig. 9 is the adaptive notch filter structure chart that the present embodiment of the present invention provides；
Figure 10 is that the adaptive notch filter that the present embodiment of the present invention provides realizes Organization Chart；
Figure 11 is cordic algorithm schematic diagram；
Figure 12 is ORDIC algorithm every one-level iteration-internal realization figure；
Figure 13 is the structure chart of self adaptation high pass filter.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, right The present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, and It is not used in the restriction present invention.
Referring to Fig. 1 and Fig. 2, embodiments provide a kind of ECG signal processing system, this electrocardiosignal is pre- Processing system includes: signal amplifies Acquisition Circuit and amplifies AD sample circuit and the described AD that Acquisition Circuit is connected with described signal The JTAG telecommunication circuit that the FPGA circuitry that sample circuit connects is connected with described FPGA circuitry, and adopt to the amplification of described signal The power circuit that collector, AD sample circuit, FPGA circuitry, JTAG telecommunication circuit are powered；Wherein, described FPGA circuitry includes:
FIR low pass filter, is used for processing myoelectricity interference；
Adaptive notch filter, is connected with described FIR low pass filter signal and is used for processing power frequency component interference；
Self adaptation high pass filter, is connected with described adaptive notch filter signal and is used for processing baseline drift noise Impact.
In the above-described embodiments, according to noise spies such as myoelectricity interference, Hz noise, baseline drifts present in electrocardiosignal Point, it is proposed that use FIR low pass filter to inhibit myoelectricity noise jamming, uses adaptive notch filter to eliminate Hz noise, and Use self adaptation high pass filter to eliminate baseline drift, be effectively improved the accuracy of ecg signal acquiring.
Understand the ECG signal processing system that the present embodiment provides for convenience, below in conjunction with the accompanying drawings and concrete reality Execute example it is described in detail.
As it is shown in figure 1, ECG signal processing system is mainly amplified Acquisition Circuit, AD sample circuit, FPGA electricity by signal Road, JTAG telecommunication circuit and power circuit composition.Wherein, its core circuit designs for FPGA chip circuit, because it controls High-speed AD sampling, the pretreatment of electrocardiosignal, the read-write of FIFO and pass through the communication control between JTAG and upper computer software System.ECG signal processing process based on FPGA, as in figure 2 it is shown, it includes the signal acquisition module controlling AD7606, is used for The algoritic module of ECG signal processing, the data cache module communicated with host computer.Wherein, in ECG signal processing system Key component be: Design Treatment myoelectricity interference FIR low pass filter, Design Treatment power frequency component interference adaptive notch Wave filter, the self adaptation high pass filter of Design Treatment baseline drift noise.
Introduce the present embodiment in turn below and the various piece of ECG signal processing system is provided.
First signal have employed AD8232 electrocardiogram acquisition amplification chip, in this, as electrocardio in amplifying Acquisition Circuit native system The collection nucleus module of signal.This chip can gather the electrocardiosignal of mV level, and signal is amplified to positive and negative about 3.3V, So that A/D chip collection.
The when of selecting electrocardiosignal front-collection amplification chip, need to consider conversion speed, resolution, power consumption with And the performance parameters such as gain bandwidth.Generally, it is desirable to slew rate is not less than 10V/us, high-resolution and the fortune of low-power consumption Put.According to above requirement, native system is selected this operational amplifier of AD8232, carries out the processing and amplifying of electrocardiosignal. Specifically, AD8232 has low cost, low-power consumption and outstanding AC and DC performance；The minimum 78dB of common mode inhibition, Output voltage swing is ± 3V (load as little as 150 Ω)；Low source current: 5.3mA, high pressure Slew Rate: 300V/ μ s.Therefore, it is complete Entirely meet signal and amplify the requirement adjusted.
A/D change-over circuit, AD7606 be the highest sample rate of one be 200kSPS, sampling precision be 16 have symbol Analog-digital converter.A built-in high-performance sample/hold amplifier (SHA) and reference voltage source in its chip.AD7606 uses Multi-level differential pipelined architecture, and built-in output error correction logic, it is possible to ensure in whole operating temperature range without losing code.
AD7606 change-over circuit, when two CONVST (CONVST A, the CONVST B) pin of AD7606 connects, Ke Yitong Shi Jinhang 8 channel sample, or each CONVST starts synchronized sampling to respective channel, and (CONVSTA is used for starting V1 to V4 Synchronized sampling, CONVST B is used for V5 to V8 is started synchronized sampling).When internal reference voltage selects 2.5V, simulation input Voltage range is for reaching ± 10V.After system electrification initializes, the rising edge of CONVST starts AD conversion, and BUSY signal becomes simultaneously Height, represent conversion carry out, when use internal reference clock time, the time of changing into 4us, when BUSY signal becomes low level Time, expression converts, and can start read operation.When BUSY trailing edge, sample/hold amplifier returning tracking pattern, this Time drag down chip selection signalSignal is enabled each readingLow period between can be by the 16 of each passage Change-over knot Fruit reads the most successively from output register, and the shortest between twi-read is spaced apart 6ns.
In order to verify the correctness of A/D controller, the controller IP code of design is downloaded to FPGA (EP4CE6F17C8) In test platform, and the logic analyser utilizing QUARTUS to carry carries out waveforms detection to its clock signal.Work as chip selection signal After ad_cs drags down, 8 readings of ad_cs enable signal and are between low period, and now FPGA is by 16 Change-over knots of 8 passages Fruit reads successively from the output register of A/D chip.
Fpga chip to be made realizes normal signal processing function, just be unable to do without peripheral interface circuit.These peripheral interfaces Circuit includes: crystal oscillating circuit, reset circuit, the jtag circuit etc. downloaded.
Electrocardiosignal is a kind of faint small-signal, and its intensity is typically between 0.05mV-5mV.Gathering electrocardiosignal During be typically subject to the interference of very noisy.Myoelectricity interference is a kind of random white Gaussian noise during electrocardiogram acquisition, Generally there are hardware filtering and two kinds of methods of software filtering can suppress this noise.Software filtering side with digital filtering as representative Rule can regulate again parameter and realize filtering flexibly while completing hardware filtering function.Wherein, finite impulse rings Should (FIR) wave filter be a kind of wave filter for removing electrocardio myoelectricity interference noise conventional in software filtering.With endless Wave filter (IIR) is compared, and it has stability, the feature of strict linear phase.FIR filter is to hold N number of sampled data The process of row weighted average sum, its processing procedure is represented by by formula (1):
What formula (1) described is the mathematical formulae of FIR filter, and wherein N represents the tap number of FIR filter, wherein x K () represents the data of the sampling of kth input, y (n) represents the filtering data of output.Mathematical structure model, as shown in Figure 3；
The computing of whole wave filter mainly forms by taking advantage of and add computing.Designed by the quantity of multiplication module and wave filter Exponent number the most relevant, and the number of exponent number choose be specifically filtered by it environment (sample frequency, the decay of stopband, The selection of algorithm) determined.In the case of exponent number determines, how to optimize multiplying to the resource of FPGA, area, speed Have a very big impact.This chapter will discuss the optimization method of multiple multiplying, and frequency spectrum, filtering finally according to electrocardiosignal are wanted Ask, FPGA resource etc. requires to select suitable optimizing design scheme.
Linear FIR filter has strict linear phase characteristic, and coefficient Striking symmetry, therefore, it can utilize it Symmetry optimize the number of multiplier.When h (n) is even symmetry, and N is odd number, its processing procedure can be represented by formula (2) For:
Can draw its lienar for network structure from formula, as shown in Figure 4, wherein the number of multiplier is (N+1)/2 Individual.
When h (n) is even symmetry, and N is even number, its processing procedure is represented by by formula (3):
Its lienar for network structure can be drawn, as it is shown in figure 5, wherein the number of multiplier is N/2 from above formula.
The design of distributed FIR filter
Distributed optimization method is optimization method based on multiplier architecture.Mathematical operation within FPGA can be called DSP operation module within FPGA realizes taking advantage of and adding computing of FIR filter.This method is simple, and is easily achieved.But It is, in some spectrum distribution identification requires high wave filter, to generally require more filter factor and could meet requirement.That , so will certainly increase the consumption of DSP module in FPGA, because the resource scarcity of DSP module can make FPGA meeting when comprehensive Consume more logical resource to compensate its defect.Taking in a large number of logical resource not only can affect the work of whole system frequently Rate, and stability and the chip power-consumption of system can be had a strong impact on.Generally, the digital filter of high-order can use distribution Formula algorithm optimizes multiplying and realizes resource optimization.
So-called distributed algorithm, its essence is exactly by the institute multiplying accumulating structure arithmetic of the fixed coefficient in FIR filter There is result to leave in a memorizer, use when calculating the method for look-up table to realize whole multiplying.Therefore, adopt The FIR filter designed by this structure has the advantages such as operation efficiency is high, processing speed is fast.
Distributed algorithm principle
What formula (4) described is the transmission form of a FIR filter, and wherein coefficient h (n) is the fixing of FIR filter Constant,
X (n) is data with fixed width of input, uses binary number representation for signless data x (n) For formula (5):
xbN () represents the b position of x (n), x (n) represents n-th sampled value of x, and formula (4) and (5) simultaneous obtain formula later (6):
WhereinOwing to actual signal is all signed number evidence, the most distributed System be the form using complement code to represent binary data, the binary number form of the x (n) represented with B+1 position is formula (7):
The formula that is output as (8) is obtained with formula (6) simultaneous:
The multiplier of whole system can represent f (h (n), x respectively with two look-up tablesB(n)), and f (h (n), x (n)), All of data value is stored with ROM as memorizer in FPGA.
The FPGA of distributed FIR filter realizes
The structures such as the FPGA implementation of distributed FIR filter has parallel, serial, modified model.Want when implementing The way of realization selected is determined with reference to the resource of FPGA, the handling capacity of system requirements, and the complexity realized.
(1) parallel distributed FIR realizes
The distributed FIR filter of parallel organization form has parallel behavior, typically it is used in high-speed computation Occasion.The wave filter of this kind of structure uses multiple look-up tables multiple multiplication of parallel processing simultaneously, stores money in substantial amounts of Source exchanges the raising of speed for.Being illustrated in figure 6 a data width is 3, the parallel distributed structure of a system of N=4. Wherein, DALUT is to utilize FPGA internal abundant sheet interior storage resource to store all f (h (n), xB(n)) the look-up table mould of value Block.
(2) the distributed FIR of serial realizes
Compared to parallel organization, serial structure uses multiplexing to search mode, optimizes DALUT module, has reached to save money The purpose in source, the most this structure is suitable for the system that resource is relatively nervous.But, this structure needs to increase extra being correlated with Control module, could realize the related algorithm of multiple with 2.Serial structure is as shown in Figure 7.
(3) the distributed FIR of modified model realizes
The size of the look-up table of DALUT and coefficient N exponentially times (2N) relation with increase.It is to say, along with the increase of N, The consumption of the resource of FPGA storage inside module will increase the most again.For this situation, use and split follow-on algorithm The consumption of resource will be reduced.Look-up table is mainly divided into multiple little look-up table by this segmentation.Such as, one a length of The FIR filter of NL, can be divided into L group its coefficient, and each group makes an independent look-up table, its mathematic(al) representation Such as formula (9):
For 4N rank system structure as shown in Figure 8, wherein dotted portion be insert the depositor within FPGA Module.Use this structure can improve the data throughout of entirety.
Electrocardiosignal is as a kind of faint small-signal, within its effective spectrum is concentrated mainly on 0.7～100Hz.Myoelectricity Interference is to be mixed in frequency spectrum with the form of white noise, and therefore, design FIR low pass filter can successfully filter out and be mixed in Electrocardiosignal is more than the electromyographic signal of 100Hz.
The FIR filter parameter using the FDAT design in MATLAB is arranged；
The most obvious 103 samples of myoelectricity interference phenomenon are chosen as test number from MIT_BIH ecg signal data storehouse According to, by utilizing MATLAB instrument to extract original electro-cardiologic signals, then, isolate after low-pass filtering noise signal and Output signal.Electrocardiosignal before and after contrast filtering, after low-pass filtering treatment, is more than in the frequency spectrum of electrocardiosignal The myoelectricity noise interferences fast-fading of 100Hz, result shows that myoelectricity noise can be done by this FIR electrocardiosignal low pass filter Disturb and carry out effective inhibitory action.
The FIR filter of the present embodiment design is 182 rank, therefore, at least needs 91 multipliers could meet this kind of design. Fpga chip selected by the present embodiment is the EP4CE6F17C8 high-performance low-power-consumption chip of ALTERA company, though its inside The most a small amount of DSP multiplier module, but the RAM having about 150K stores resource, and therefore, the present embodiment will utilize FPGA Internal abundant memory module realizes follow-on distributed FIR filter.The FIR filter provided due to ALTERA company IP is exactly the follow-on distributed FIR structure used, so, the design directly invokes this FIR filter IP to complete low pass The design of wave filter.
In this module designs, the interface of local data all have employed form based on AVALONE bus, so, favorably The Integrated Development in Qsys system in this module and other module.The data arranging input are 16bit signed number evidence；With Time, the data arranging output are 34bit signed number evidence, and this preferably retains intermediate operations data message.
In order to analyze the Energy distribution situation of output signal after FPGA processes the most exactly, the design uses The method of Modelsim and MATLAB joint test, preserves the data after processing through FPGA with the form of .dat file, And utilize Mathematical treatment instrument powerful for MATLAB that output data are done spectrum analysis.
Electrocardiosignal after FPGA processes is substantially achieved more than the myoelectricity interfering noise signal of 100Hz and filters, and And its simulation result is completely the same with the test result carrying out numerical simulation with MATLAB.Accordingly, it is shown that based on FPGA platform The design of FIR low pass filter be in the main true.
In order to detect the electrocardio filter effect of reality further, the logic analyser within application FPGA is adopted by the design Time domain waveform before and after collection Filtering of ECG Signal, compares with this and checks the effect of the design.
Wherein, the actual electrocardiosignal that logic analyser is gathered shows, the myoelectricity interference signal in block diagram is after the filtering Having obtained effective suppression, this also illustrates that this module designed is fully able to suppress myoelectricity interference signal.
In order to test the Filtering of ECG Signal performance after FPGA processes, this paper is with signal to noise ratio (SNR) and mean square error (MSE) as parameter of measurement(P1For signal power, P2For noise power)And Performance after MATLAB processes compares.Design parameter correction data is shown in Table 2:
Electrocardiosignal parameter comparison after table 2 myoelectricity denoising
Table 2 shows electrocardiosignal performance parameter index after the internal FIR filter of FPGA processes and MATLAB reason The index that opinion is analyzed is basically identical, illustrates that the design is coincidence theory requirement.
Optimization Design based on symmetry coefficient, devises distributed FIR filter, with MIT-BIH electrocardiosignal Sample 103 in data base is primary signal, this filtering carries out numerical simulation and carries out the electrocardio circuit test of reality, and And using to-noise ratio and mean square error as performance evaluation, show, by above experiment, the FIR low pass filter that the present embodiment designs Can successfully filter myoelectricity interference signal, and the conclusion of numerical simulation and experiment test is completely the same, it was demonstrated that this method for designing Correctness and reliability.
The operation principle of wave trap
Preferably notch filter principle frequency response formula is (10):
Preferably wave trap frequency spectrum only can have decay needing the frequency filtered, and does not interferes with the useful letter near frequency Number, but the wave trap of reality is difficult to this point.The external electrocardiogram acquisition chip bought now is all to use simulation trap Method realization filtering, this filtering realizes simple, but useful band signal near meeting severe jamming.Therefore noise should be suppressed Retain the composition of useful signal the most as far as possible so that the spectral characteristic of wave trap is more nearly desired notch device, and this is to set The difficult point of meter.
Wave trap is generally divided into simulation and numeral two kinds, and the implementation of digital trap can pass through FIR or IIR mould Type realizes.Owing to the wave trap of FIR type is as the wave filter of a kind of onrecurrent type, it is former that its limit exists only in coordinate Point, so system is stable, designs such wave trap, as obtained the narrowest bandwidth, it is necessary to use high-order filter Ripple device could meet.On the contrary, iir filter is as a kind of recursive filter device, and its limit is positioned on unit circle rather than initial point. Therefore, the pole distribution of iir filter can reset according to the narrow band bandwidth of wave trap, and adaptive notch filter is exactly The a kind of of IIR mode filter optimizes structure, and it can retain useful component while having narrower bandwidth as far as possible, Therefore, the spectral characteristic of desired notch device it is more nearly.
Adaptive notch filter principle
When the noise mixed in electrocardiosignal is the noise of a kind of single-frequency component, such as the power frequency component of 50Hz, then disappear Except the method for this interference uses wave trap exactly.The present embodiment devises a kind of adaptive notch filter, the structure of this wave trap Figure is as shown in Figure 9.This structure is an adaptive notch filter with two weights coefficients, and original input signal is s (t) and make an uproar Acoustical signalSuperposition, letter
The signal function of the discretization obtained after number sampledWherein Reference-input signal x1It it is the cosine wave after the discretization of a standardSecond road signal is x1Through 90 degree of phase shifts After the signal x that obtains2, the reference signal that both obtainedTwo varied weight coefficients are respectively w1, w2Signal x with input1, x2May be constructed the sine wave type (11) of arbitrary phase, the structure chart of adaptive notch filter obtain Formula (12), (13), (14), (15).By self-adaptative adjustment w1, w2So that the signal phase β of output just with interference signal Phase place is consistent, thus disposes original power frequency interference signals.
w1(k+1)=w1(k)+μe(k)x1(k) (14)
w2(k+1)=w2(k)+μe(k)x2(k) (15)
It is formula that simultaneous formula (12), (13), (14), (15) can obtain the ssystem transfer function of whole system from reaction type (16):
In reference frequency ω0On have the characteristic of wave trap, when formula (16) selects ω 0=50Hz to this adaptive notch filter Carrying out spectrum analysis with MATLAB, frequency has fast fading characteristics near 50Hz, has declining of up to 100dB at 50Hz Subtract.If the FIR wave trap of design, needing 256 exponent numbers, its decay at 50Hz but only has 9dB.As can be seen here, in filter Except 50Hz industrial frequency noise signal aspect, the adaptive notch filter of design compares with conventional FIR wave trap, has obvious advantage.
In adaptive notch filter, the FPGA of signal generating module realizes
Adaptive notch filter based on FPGA platform realizes framework as shown in Figure 10, and this framework specifically includes that input signal, Output signal, signal generating module and adaptive algorithm module.Signal generating module is for producing the cosine and sine signal of needs, certainly Adaptation algorithm block is mainly used to realize formula related algorithm.When μ=0.1, during A=1, if initial value w1=0, w2=0, for adaptive Answer the initial system parameters of algoritic module.
Adaptive notch filter needs a sine and cosine sample for reference signal to meet the regulation of signal.FPGA is used for realize The method of cosine and sine signal has a variety of.Most commonly seen is that the method using look-up table realizes (DDS), and the method is simple, just Realize in FPGA, but the method to obtain high-precision cosine and sine signal and then need to consume the internal too much storage mould of FPGA Block, and the existence of also truncation noise.Due to design distributed FIR filter in filtering electromyographic signal, consumed The internal too much RAM memory module of FPGA, and also have the abundantest logical resource in view of FPGA is internal, therefore, this Embodiment selects CORDIC (CORDIC) algorithm to realize cosine and sine signal.Cordic algorithm is a kind of calculating three The algorithms most in use of angle function.Cordic algorithm has become (MIMO technology, Wave beam forming and self adaptation system in Digital Signal Processing System) important technology.
Cordic algorithm principle
The present embodiment uses the method for polling system to realize cordic algorithm, and what Figure 11 described is a planar coordinate The process rotated, whole process is it can be seen that by vector (Xi, Yi) rotate specific angle, θ, obtain a new vector (Xj, Yj), formula (17) can be used to represent:
Xj=Rcos (θ+β)=Xicos(θ)-Yisinθ
Yj=Rsin (θ+β)=Xisin(θ)+Yicosθ (17)
In formula (17), R is the radius of the circumference of vector, and β is the angle of initialization vector, and θ is the angle of Vector Rotation, uses square The form of battle array represents such as formula (18):
The method using iteration, through iteration repeatedly, it is possible to make the angle summation of rotation converge on the angle needing to rotate Degree.Obtaining (n+1)th vector after n iteration is formula (19):
θ every timenValue beWhereinShow that the angle of total iteration is equal to needing rotation The angle turned.Wherein Sn={-1；+ 1} controls the direction rotated, each anglec of rotation ZnFor formula (20):
Wherein SnAnd ZnRelation be formula (21):
BecauseThe increase of the number of times of iteration, whole product will converge on a constant K, i.e. formula (22):
Not considering the gain of constant, formula (20), (21), (22) simultaneous obtain formula (23):
After the iteration of n timesProduct trend towards a constant K and then simplify and obtain formula (24):
(2) cordic algorithm pattern
The present embodiment uses the rotary mode of cordic algorithm.In rotary mode, what the initial value of Z represented is that system needs An angle to be rotated, when Z level off to 0 time, obtain formula (25):
Xn+1=Xn-SnYn2-n
Yn+1=Yn+SnYn2-n
Zn+1=Zn-Sntan-1(2-n) (25)
Result such as formula (26) in output final after the iterating of n times:
Xn+1=P [X0cos(Z0)-Y0sin(Z0)]
Yn+1=P [Y0cos(Z0)+X0sin(Z0)] (26)
WhereinZn+1If=0 orderY0=0, Z0=α, last after successive ignition It is output as formula (27):
Xn+1=cos α
Yn+1=sin α (27)
Zn+1=0
Can draw from above-mentioned derivation, through successive ignition after a given angle value, just can calculate this angle The value of the trigonometric function of degree.If the change of angle is linear change within 360 degree, then just can obtain a continuous print triangle Function.
(3) cordic algorithm FPGA realizes and test
According to the algorithm of rotary mode, the angle now rotated is 0, almost the value of approximation theory.Whole cordic algorithm The frame diagram that FPGA realizes, the linking relationship between each iteration block diagram, after the iteration of 16 times, altogether export sine and cosine Signal.
Each iteration unit as shown in figure 12, wherein Xn, Yn, ZnIt is after n iteration, be input to the (n+1)th iteration list The input signal of unit.Shift register is used to the signal of temporary input, and wherein shift register is accomplished that 2-nComputing, Xn, YnArithmetic section plus and minus calculation realizes the computing of formula (24).Store in ROM is the anglec of rotation of (n+1)th time, with input ZnDo plus and minus calculation result for judging that sign bit wherein control unit carrys out the output of control signal.
The signal generating module the simulation results of FPGA is it can be seen that the signal generating module of this design can be accurate Output cosine and sine signal, these needs being also fully consistent with designing adaptive notch filter.
Emulation and test result analysis
The present embodiment, in MIT-BIH ecg signal data storehouse, uses 102 samples that Hz noise more highlights as number According to source, the module of design is carried out emulation testing.First, adaptive notch algoritic module carries out MATLAB numerical value imitate Very, then contrast with the output signal after FPGA simulation process, verify that FPGA design result is divided with theoretical with this Whether analysis result has concordance, and wherein, parameter is provided that
Sine and cosine signal frequency 50Hz, μ=0.1, A=1, w1=0, w2=0
Electrocardiosignal before and after emulating MATLAB does frequency-domain analysis, after adaptive notch processes, and electrocardiosignal In 50Hz power frequency interference signals be filtered out, the most in theory, the adaptive notch filter designed by the present embodiment can be effectively Filter the Hz noise noise of 50Hz.
Using adaptive notch filter that electrocardiogram (ECG) data is carried out FPGA simulation process, the test result obtained understands, input letter Number through adaptive notch filter process after, the burr being mingled with in the electrocardiosignal of output has obtained effective suppression so that Electro-cardiologic signal waveforms becomes more smooth.
For analyzing further the frequency distribution characteristic of output signal after FPGA processes, the design use Modelsim and The method of MATLAB joint test, preserves with the form of .dat file processing later data by FPGA, and utilizes Output data are done spectrum analysis by Mathematical treatment instrument powerful for MATLAB.The power frequency interference signals of 50Hz is being carried out at FPGA After reason, this noise is effectively filtered out, and this just illustrates the test result of this circuit and carries out numerical simulation with MATLAB Test result is completely the same.Therefore, this experiment fully show the design of adaptive notch filter based on FPGA platform be correct, can Leaning on, its parameters all can meet the requirement of design.
In order to detect the filter effect of reality, the design uses logic analyser equally, before and after doing the data gathered Contrast, comparing result shows, adaptive notch filter is after tracking to signal after a while, and power frequency component gradually declines Subtract.In other words, this embodies power frequency component and has attenuation characteristic under the effect of adaptive notch filter, the adaptive resistance-trap of this design Ripple device is feasible.
Electrocardiosignal presents attenuation characteristic under the effect of adaptive notch filter.This figure shows, power frequency component is necessarily Being decayed in degree, this just illustrates that this wave trap can suppress the Hz noise in electrocardiosignal.In order to quantitative analysis is adaptive Filtering of ECG Signal performance after answering trap to process, using signal to noise ratio (SNR) and mean square error (MSE) as parameter of measurement(P1For signal power, P2For noise power)To compare with tradition IIR type filtering Relatively, wherein SNR/MSE value the biggest explanation filter effect is the best, and design parameter correction data is shown in Table 3:
Electrocardiosignal parameter comparison after table 3 power frequency denoising
Data in table 3 show through adaptive notch filter filtered electrocardiosignal signal to noise ratio and mean square deviation noiseproof feature Increase than the performance of traditional IIR type filtering, illustrate that the design is better than traditional iir filter.
The design of self adaptation high pass filter
System function such as formula with reference to wave trapTherein ω0The mid frequency of the signal for filtering, works as ω0=0, A=1, the system function of adaptive notch filter can obtain formula for H (z) (28):
What formula (28) described is a high pass filter, and its frequency response is formula (29)
Can be seen that from the distribution of frequency spectrum signal has in 0～0.7Hz section soon by adjusting parameter μ=0.02 Speed fading characteristic, maximum attenuation reaches 100dB.Generally for reaching to obtain quick band-rejected characteristic in narrow frequency range, often The wave filter of rule only increases complexity in system could meet requirement.Use self adaptation high pass filter, simplify system Complexity, can meet again the design requirement of system, and this is the great advantage of self adaptation high pass filter.
Numerical analysis based on MATLAB
Use several groups of data samples of 109 and 203 sample in MIT-BIH data base, the self adaptation high-pass filtering to design Device carries out MATLAB numerical simulation, mainly input and output data is carried out time and frequency domain analysis, and sample 109 is one and comprises The data of faint baseline drift noise, after self adaptation high-pass filtering, the low-frequency interference signal in electrocardiosignal is filtered out, i.e. It is demonstrated experimentally that adaptive notch filter can effectively remove baseline drift phenomenon.
In order to preferably test the performance of self adaptation high pass filter, choose 203 samples with serious baseline drift phenomenon Originally, the baseline drift phenomenon in after self adaptation high pass filter, processes the most closely eliminates.
Electrocardiosignal to 203 samples before and after filtering does the effect of frequency-domain analysis, understands, through adaptive from frequency domain figure After answering high-pass filtering, the low-frequency interference signal in electrocardiosignal is filtered out, it is demonstrated experimentally that adaptive notch filter can be removed effectively Baseline drift phenomenon.
Self adaptation high pass filter based on FPGA designs
FPGA design framework
On method for designing basis based on adaptive notch filter, it is high that the present embodiment devises a kind of modified model self adaptation Bandpass filter, its structure as shown in figure 13:
Compared with in Figure 13 with Fig. 9, it decreases the design of signal generating module in the input module part of system, takes and generation Be input one constant.Therefore inside self adaptation high pass algoritic module, have only to an adjustment factor w1 want with regard to meeting Asking, this enormously simplify the complexity of design compared with the design system of adaptive notch filter, and has saved substantial amounts of resource Consume.
The resource that self adaptation high pass filter is consumed is few more than the logical resource that adaptive notch filter is consumed.And, Than small echo, shape filtering and the method for traditional FIR filtering, use high pass filter at resource consumption and system complexity Aspect is respectively provided with big advantage.
The test of self adaptation high pass filter based on FPGA design
Finding out from the result of Modelsim emulation time domain waveform, input sample signal 203 is high through self adaptation After bandpass filter processes, its baseline drift phenomenon has obtained obvious suppression.
For output data, can draw after carrying out spectrum analysis, through FPGA process after electrocardiosignal in low Frequency interference signal is effectively filtered out.Then show, the test result of this circuit and the test carrying out numerical simulation with MATLAB Result is consistent, and the design of i.e. based on FPGA platform self adaptation high pass filter is correct, feasible.In sum, this sets Meter method can eliminate baseline drift phenomenon, and has that consumption resource is few, the simple feature of system structure.
Equally, in order to detect the electrocardio filter effect of reality further, the design will use the logical analysis within FPGA Instrument, contrasts the time domain waveform before and after the Filtering of ECG Signal of actual acquisition, checks the effect of the design with this.
Compared with ch2 (output signal) and ch1 (input signal) after after filtering, the baseline interference of ch1 is suppressed. Therefore, this explanation the design can suppress baseline noise to disturb well.
For transversal filter performance, the present embodiment with morphologic filtering and wavelet filtering scheme as a comparison, and with letter Make an uproar than (SNR) and mean square error (MSE) as parameter of measurement (P1For signal power, P2For noise merit Rate)Design parameter correction data is shown in Table 4:
Electrocardiosignal parameter comparison after table 4 self adaptation high pass filter denoising
Data in table 4 show, the self adaptation high pass filter of the present embodiment design and traditional small echo and morphology side Method is compared, and achieves higher to-noise ratio and mean square deviation, and the self adaptation high pass filter ratio above-mentioned two that the present embodiment designs is described The method of kind is more preferable.
These are only presently preferred embodiments of the present invention, not in order to limit the present invention, all spirit in the present invention and Any amendment, equivalent and the improvement etc. made within principle, should be included within the scope of the present invention.

Claims (6)

1. an ECG signal processing system, it is characterised in that including: signal amplifies Acquisition Circuit and described signal amplifies The FPGA circuitry that the AD sample circuit that Acquisition Circuit connects is connected with described AD sample circuit is connected with described FPGA circuitry JTAG telecommunication circuit, and power to described signal amplification Acquisition Circuit, AD sample circuit, FPGA circuitry, JTAG telecommunication circuit Power circuit；Wherein, described FPGA circuitry includes:
FIR low pass filter, is used for processing myoelectricity interference；
Adaptive notch filter, is connected with described FIR low pass filter signal and is used for processing power frequency component interference；
Self adaptation high pass filter, is connected and is used for processing the shadow of baseline drift noise with described adaptive notch filter signal Ring.
ECG signal processing system the most according to claim 1, it is characterised in that described signal amplifies Acquisition Circuit and is AD8232 electrocardiogram acquisition amplification chip.
ECG signal processing system the most according to claim 2, it is characterised in that described FIR low pass filter is to N Individual sampled data performs the wave filter of the process of weighted average sum, and its processing procedure is according to following equation:
y ( n ) = x ( n ) * h ( n ) = Σ k = 0 N - 1 x ( k ) h ( n - k ) = Σ k = 0 N - 1 h ( k ) x ( n - k )
Wherein N represents the tap number of FIR filter, the wherein data of the sampling of x (k) expression kth input, and y (n) represents defeated The filtering data gone out.
ECG signal processing system the most according to claim 3, it is characterised in that being even symmetry as h (n), N is strange During number, described FIR low pass filter processing procedure is according to following equation:
y ( n ) = Σ k = 0 N - 1 x ( k ) h ( n - k ) = Σ k = 0 N - 1 h ( k ) x ( n - k )
= Σ k = 0 N - 1 2 - 1 h ( n ) [ x ( n - k ) + x ( n - N + k ) ] + h ( N - 1 2 ) x ( n - N - 1 2 )
When h (n) is even symmetry, and N is even number, described FIR low pass filter processing procedure is according to following equation:
y ( n ) = Σ k = 0 N - 1 x ( k ) h ( n - k ) = Σ k = 0 N - 1 h ( k ) x ( n - k ) = Σ k = 0 N - 1 2 h ( n ) [ x ( n - k ) + x ( n - N + k ) ]
ECG signal processing system the most according to claim 4, it is characterised in that described adaptive notch filter is for having The adaptive notch filter of two weights coefficients, wherein, original input signal is s (t) and noise signalFolded Add, the signal function of the discretization obtained after signal is sampledWherein Reference-input signal x1It it is the cosine wave after the discretization of a standardSecond road signal is x1Through 90 degree of phase shifts After the signal x that obtains2, the reference signal that both obtainedAnd two varied weight coefficients are respectively For w1, w2Signal x with input1, x2May be constructed the sine wave type of arbitrary phase.
ECG signal processing system the most according to claim 5, it is characterised in that described self adaptation high pass filter Frequency should be mutually:
CN201610545370.2A 2016-06-28 2016-06-28 A kind of ECG signal processing system Pending CN106125604A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610545370.2A CN106125604A (en) 2016-06-28 2016-06-28 A kind of ECG signal processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610545370.2A CN106125604A (en) 2016-06-28 2016-06-28 A kind of ECG signal processing system

Publications (1)

Publication Number Publication Date
CN106125604A true CN106125604A (en) 2016-11-16

Family

ID=57283782

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610545370.2A Pending CN106125604A (en) 2016-06-28 2016-06-28 A kind of ECG signal processing system

Country Status (1)

Country Link
CN (1) CN106125604A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107080536A (en) * 2017-05-25 2017-08-22 江苏师范大学 A kind of portable wireless multichannel brain electric signal acquiring system
WO2019047165A1 (en) * 2017-09-08 2019-03-14 曼森伯格（深圳）科技发展有限公司 Control method and system for filtering out working frequency interference signal
CN110584646A (en) * 2019-08-20 2019-12-20 广东工业大学 Adaptive second-order filtering electrocardiosignal denoising preprocessing device and method
CN110933031A (en) * 2019-10-25 2020-03-27 国网吉林省电力有限公司电力科学研究院 Intelligent power grid power distribution terminal unit intrusion detection method based on LSTM
CN110957995A (en) * 2019-10-25 2020-04-03 四川汇源光通信有限公司 Distributed fault monitoring device IIR filtering system and design method thereof
CN111525910A (en) * 2020-04-28 2020-08-11 上海工程技术大学 Filter device for high-speed signal transmission equipment
CN114200260A (en) * 2021-11-26 2022-03-18 山东泰开成套电器有限公司 Audio-based switch cabinet partial discharge detection method

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2530301Y (en) * 2001-03-09 2003-01-08 北京卡迪欧医疗设备有限责任公司 Analyser for electrocardiosignal
CN102028460A (en) * 2011-01-04 2011-04-27 复旦大学 Ventricular fibrillation signal sequence automatic-detection system
US20110319777A1 (en) * 2009-03-09 2011-12-29 Council Of Scientific & Industrial Research Ecg device with impulse and channel switching adc noise filter and error corrector for derived leads
CN104095627A (en) * 2014-05-20 2014-10-15 邱磊 Electrocardiogram digitized signal quality soft-decision method and device
CN204500675U (en) * 2015-02-02 2015-07-29 四川理工学院 A kind of portable cardiac monitor system
CN205083472U (en) * 2015-10-22 2016-03-16 东华理工大学 Electrocardio signal acquisition and processing system

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2530301Y (en) * 2001-03-09 2003-01-08 北京卡迪欧医疗设备有限责任公司 Analyser for electrocardiosignal
US20110319777A1 (en) * 2009-03-09 2011-12-29 Council Of Scientific & Industrial Research Ecg device with impulse and channel switching adc noise filter and error corrector for derived leads
CN102028460A (en) * 2011-01-04 2011-04-27 复旦大学 Ventricular fibrillation signal sequence automatic-detection system
CN104095627A (en) * 2014-05-20 2014-10-15 邱磊 Electrocardiogram digitized signal quality soft-decision method and device
CN204500675U (en) * 2015-02-02 2015-07-29 四川理工学院 A kind of portable cardiac monitor system
CN205083472U (en) * 2015-10-22 2016-03-16 东华理工大学 Electrocardio signal acquisition and processing system

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
宋爱国 等: "《测试信号分析与处理》", 31 January 2009 *
张元 等: "《数字信号处理》", 30 November 1995 *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107080536A (en) * 2017-05-25 2017-08-22 江苏师范大学 A kind of portable wireless multichannel brain electric signal acquiring system
WO2019047165A1 (en) * 2017-09-08 2019-03-14 曼森伯格（深圳）科技发展有限公司 Control method and system for filtering out working frequency interference signal
US11540763B2 (en) 2017-09-08 2023-01-03 Maisonburg (Shenzhen) Technology Development Co., Ltd. Control method and system for filtering power line interferences
CN110584646A (en) * 2019-08-20 2019-12-20 广东工业大学 Adaptive second-order filtering electrocardiosignal denoising preprocessing device and method
CN110933031A (en) * 2019-10-25 2020-03-27 国网吉林省电力有限公司电力科学研究院 Intelligent power grid power distribution terminal unit intrusion detection method based on LSTM
CN110957995A (en) * 2019-10-25 2020-04-03 四川汇源光通信有限公司 Distributed fault monitoring device IIR filtering system and design method thereof
CN111525910A (en) * 2020-04-28 2020-08-11 上海工程技术大学 Filter device for high-speed signal transmission equipment
CN114200260A (en) * 2021-11-26 2022-03-18 山东泰开成套电器有限公司 Audio-based switch cabinet partial discharge detection method

Similar Documents

Publication Publication Date Title
CN106125604A (en) A kind of ECG signal processing system
Sun et al. Fault diagnosis of rolling bearing based on empirical mode decomposition and improved manhattan distance in symmetrized dot pattern image
CN103699513B (en) A kind of stochastic resonance method adjusted based on multiple dimensioned noise
CN107085144A (en) A kind of method of quick measurement Harmonious Waves in Power Systems
CN108272451B (en) QRS wave identification method based on improved wavelet transformation
CN104052494B (en) Signal reconstruction method for frequency domain sparse signals
CN105769173A (en) Electrocardiogram monitoring system with electrocardiosignal denoising function
CN105212922A (en) The method and system that R wave of electrocardiosignal detects automatically are realized towards FPGA
Zou et al. An ultra-low power QRS complex detection algorithm based on down-sampling wavelet transform
CN103190901A (en) R wave detection algorithm based on extremum field mean mode decomposition and improved Hilbert enveloping
CN115901248B (en) Gear box fault feature extraction method
CN109374298B (en) Bearing fault diagnosis method based on cross-correlation singular value
CN106500991B (en) Bearing fault signal characteristic extracting methods based on self-adapting multi-dimension AVG-Hat transformation
CN103345379B (en) A kind of complex multiplier and its implementation
CN103176949B (en) Realize circuit and the method for FFT/IFFT conversion
Meng et al. An adaptive spectrum segmentation-based optimized VMD method and its application in rolling bearing fault diagnosis
Li et al. Multi-fault diagnosis of rotating machinery via iterative multivariate variational mode decomposition
CN201910239U (en) Voice spectrum analyzing system based on field programmable gate array (FPGA)
CN107212881B (en) T-wave electricity alternative detection method
CN110944336B (en) Time spectrum sensing method based on limited new information rate
Hii et al. ECG Noise Reduction with the Use of the Ant Lion Optimizer Algorithm.
Fang-fang et al. Studying on denoising algorithm of heart sound signal based on the generalized mathematical morphology
CN103071236A (en) Method and device for detecting electric shock signal
Janwadkar et al. Strategic design and optimization of Vedic low pass FIR filter for ECG signals
Li et al. The application of FPGA-based discrete wavelet transform system in EEG analysis

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20161116