CN1061194C - Superhighspeed bit-error sampling and testing method and instrument - Google Patents

Abstract

The invention belongs to the technical field of measurement of ultra-high-speed communication systems. The invention proposes an ultra-high-speed sampling test method and an instrument thereof. Including m-sequence generator, eliminating all 0 circuit, 1:N splitter, test branch selector, branch display and low-rate bit error detector. It has the characteristics of low cost, high reliability, flexible use, convenient operation, etc., and is suitable for mass production and popular application.

Description

Ultra-high-speed sampling method for testing code errors and its tester

The invention belongs to the technical field of testing of ultra-high-speed communication systems, and in particular relates to a testing method for bit errors and the design of an instrument.

Due to the development of optical fiber technology, optoelectronic technology and ultra-high-speed circuit technology and the demand for large-capacity information transmission in contemporary society, the future trunk transmission channel will carry out information transmission and exchange at a rate of Gb/s level, and will become a national information network. most important infrastructure. International Telecommunications Standards Organization (ITU) following SDH digital synchronous series STM-1 (155Mb/s), STM-4 (622Mb/s), STM-16 (2.5Gb/s), in 1993 in G. The level of STM-64 (10Gb/s) has been added to the level of 707 synchronous digital series, indicating that the SDH transmission network is rapidly developing towards a higher rate.

In the research, development and production process of ultra-high-speed optical fiber communication systems, the system bit error performance is one of the most important system performance indicators, and the bit error tester is an indispensable key instrument.

At present, many countries have successively developed bit error testers of different grades, and their test methods are to directly use the rate of the tested system to perform bit-by-bit comparison and analysis for bit error detection and statistics. Among them, the bit error tester below 155Mb/s has been widely used. This instrument has a simple structure and low cost. Work to the quintic group (565Mb/s) and STM-4 (622Mb/s) above the rate.

In recent years, 3Gb/s and 10Gb/s direct measurement bit error testers that can work in ultra-high-speed optical fiber communication systems have been developed successively. high cost.

The purpose of the present invention is to overcome the deficiencies of the prior art, to propose an indirect error code test method and to design an ultra-high-speed sampling method error code tester according to the method, which can utilize the existing low-speed error code test The instrument tests the bit error characteristics of ultra-high-speed communication systems. It has the characteristics of low cost, high reliability, flexible use, and convenient operation. It is suitable for mass production and popular application.

A kind of method that is used for the ultra-high-speed sampling test bit error in the ultra-high-speed communication system of the present invention, comprises the following steps:

(1) Use the high-speed sinusoidal signal input by the system to make the m-sequence generator generate high-speed m-sequence and high-speed clock signal. The length of the m-sequence is 2 ⁿ -1, and n is the number of stages of the m-sequence generator;

(2) Use the method of forcing "1" at startup and "1" when changing the code length to eliminate the all-0 blocking of the test system;

(3) said m-sequence is sent to the system under test for transmission, and the transmitted sequence becomes the signal to be tested;

(4) Use 1:N splitter to synchronously split the m-sequence signal to be tested and the high-speed clock signal into N-way low-speed m-sequences whose code rate is 1/N of the original code rate and the sequence pattern is the same as the original Low-speed clock signal with code rate 1/n;

(5) Utilize the test branch selector to select one low-speed signal in the said low-speed m-sequence and send it to the low-speed BERT together with the low-speed clock signal for testing;

(6) The number of the selected low-speed signal branch is displayed through the branch display.

The present invention designs a bit error tester using the above method. As shown in Figure 1. It is mainly composed of m-sequence generator, all-zero elimination circuit, 1:N splitter, test branch selector, branch display and low-speed bit error meter, among which the low-speed bit error meter is an existing instrument.

The present invention utilizes such a property of the m-sequence: the code length is the m-sequence of 2 ⁿ -1, if the sequence obtained by sampling with the interval S=2 ^q (q is an integer) is still the m-sequence of 2 ⁿ -1, only the same as the original sequence There is a certain phase lead, and the rate is reduced to the original 1/S. For example, the m-sequence generator generates an m-sequence of 2.5 GGb/s length 2 ¹⁵ -1, and samples it at an interval of 16 (2 ⁴ =16) in the splitter, and the obtained 16-way parallel sequence is still 2 ¹⁵ -1 m sequence, the rate drops to 155Mb/s.

For optical fiber communication systems or other communication systems, there are two main sources of noise: thermal noise and quantum noise. Thermal noise is normally distributed and can be described by a Gaussian random process. The quantum noise satisfies the Poisson distribution. After passing through the channel of the communication system, the channel can be equivalent to a linear time-invariant filter, and the quantum noise distribution becomes a filtered Poisson process. Theoretical analysis of stochastic process has proved that Gaussian process and filtered Poisson process are both stationary stochastic processes, satisfying the ergodicity of states, and their probability density has nothing to do with time. Therefore, the probability of bit errors caused by noise has nothing to do with time, and the distribution of bit errors satisfies the uniform distribution. In this way, after the sequence is sampled, the bit error rate of each subsequence obtained is the same as that of the original sequence. Measuring the bit error rate of any subsequence is equivalent to measuring the bit error rate of the entire sequence.

The method of the invention solves the problem of bit error testing of ultra-high-speed systems by using a low-speed bit error testing instrument. The method is simple and reliable, has low cost of testing instruments, is convenient and flexible to operate, and is suitable for wide popularization and use.

Brief description of the drawings:

Fig. 1 is a block diagram of the overall structure of the instrument of the present invention.

Fig. 2 is a schematic structural diagram of an m-sequence generator according to an embodiment of the present invention.

FIG. 3 is a schematic structural diagram of a circuit for eliminating all 0s in this embodiment.

FIG. 4 is a schematic structural diagram of a 1:16 splitter in this embodiment.

FIG. 5 is a schematic structural diagram of the test branch selector of this embodiment.

The present invention proposes an embodiment of an ultra-high-speed sampling bit error tester, which uses a 155Mb/s bit error tester to form a tester capable of measuring the bit error performance of a 2.5Gb/s system.

This embodiment includes an m-sequence generator, an all-zero elimination circuit, a 1:16 splitter, a test branch selector, a test branch display and a 155Mb/s bit error detector, as shown in Figure 2-5 below. Describe the structure of each part in detail.

1. m-sequence generator, as shown in Figure 2

The m sequence generator is a 15-stage shift register, a ₁₄ ..., a ₁ , a ₀ are the output signals of 15 D flip-flops and shifted to the right in sequence, a ₁₅ is the feedback signal, which is composed of a The two taps in ₁₄ ~a ₀ are obtained after modulo 2 summing. Different taps can be selected for modulo 2 sum, and different pseudo-random code sequences can be obtained. Under the selection of three specific taps, the longest pseudo-random code sequence can be obtained, which is called m-sequence. The feedback equations corresponding to the three code lengths are as follows:

2 ⁷ -1: ^{a 15} =a ¹¹ Oa ⁸

2 ¹⁰ -1: ^{a 15} =a ⁸ Oa ⁵

2 ¹⁵ -1: ^{a 15} =a ¹ Oa ⁰

The code length selector can give a control signal, select one of the above three combinations, and obtain three high-speed m-sequences with different code lengths.

2. Eliminate all 0 circuits

In the m-sequence generator, if the state of each D flip-flop is 0, the circuit is in the all-0 blocking state, and the m-sequence cannot be generated, that is to say, such a circuit has no self-starting function. In order to eliminate the all-0 blocking, two measures are set in the circuit, the forced setting of "1" when starting up and the forced setting of "1" when changing the code length. Every time it is turned on, it sets the first D flip-flop to 1 state and shifts according to the clock beat. When the "1" signal becomes low level, all 15 D flip-flops are set to 1 state, so m sequence can be generated. When there are other reasons, such as changing the code rate or code length, it is possible to make the m-sequence generator in normal operation enter the all-0 blocking state, so the high-level pulse that changes the code length is also used as a forced "1" Pulse, when the code rate or code length is changed each time, the m-sequence is restarted once, so that there is also a measure to eliminate all 0s in the actual working process after starting up, so as to ensure that the m-sequence generator is always in normal operation.

The structure of the all-zero elimination circuit is shown in Figure 3. A two-input OR gate is connected to the "1" terminal (SET pin) of the m-sequence generator, respectively connected to the power-on forced setting "1" and the code length changing forced Set "1" signal. When starting up, the voltage across _C1 is 0, R is the internal resistance of the ECL10K series chip, -5.2V power supply charges _C1 through R, and the charging constant is τ1=RC1, so the SET terminal can maintain a certain period of time after starting up High level, forcefully set "1" to the shift register, when the voltage across _C1 is less than -1.6V, the SET terminal becomes low level, and the m-sequence generator starts to operate normally. After C ₁ is fully charged, the voltage at both ends is 39/(50+39)×(-5.2)=-2.28V. When shutting down, C ₁ discharges through R ₁ with a time constant of τ ₂ =R ₁ C ₁ . The function of _R1 is to speed up the discharge speed of _C1 and shorten the time between two startups. In Figure 3, Gate _G1 and Gate _G2 form a rising-edge triggered monostable circuit. When the button A on the panel is pressed, a trigger pulse is generated at the input of Gate _G1 , and a trigger pulse is generated at the input of Gate _G2 . A high-level pulse can be obtained at the Q output terminal, and its width is determined by the time constant τ ₃ =R2C2. When the time constant τ ₃ is 1-3 seconds, the repeated triggering caused by the vibration of the key can be effectively eliminated. Button A is the code length selection key, and the high level pulse generated by it is the code length selection pulse, which is also sent to the SET pin of the m-sequence generator. When the code length is changed once, the SET pin is set to "1", the m-sequence restarts once. In this way, the all "0" blocking state that may be generated when the code rate and code length are changed after starting up is eliminated.

3. 1:16 splitter

As shown in Figure 4, it consists of a 1:16 subsection and a timing generator. The timing generator is a frequency divider, which divides the input high-speed clock signal to generate clock signals CK/2, CK/4, CK/8 with frequency division of two, four, eight and sixteen. , CK/16. In the 1:16 split section, first use CK/2 to split the input high-speed m-sequence Din 1:2 to get two signals DATA1/2 and DATA2/2,..., then use CK/4 and CK in turn The /8 signal continues to split the above signals, and finally a low-speed clock with a code rate of 1/16 and parallel 16-way low-speed signals can be obtained.

The entire splitter actually completes the following functions: Assume that the high-speed serial code stream is an m-sequence with a code length of 2 ⁿ -1:

A0, A1, A2, A3, ... A16, A17, ... A32, A33, ...

After sampling, the obtained parallel streams are:

      Q0: A0, A16, A32,...

         Q1: A1, A17, A33, ...

· ·

· ·

· ·

· ·

                                                  

The rates are all 1/16 of the serial code rate, and they are all 2 ⁿ -1 m-sequences, which are the same as the sequence pattern of the serial code stream.

4. Test branch selector and test branch display, as shown in Figure 5

The test branch selector has a 16-to-1 gate of ECL, which accepts 16 parallel signals output by the 1:16 splitter. The four-bit address code of the gate is generated by the branch selection circuit. It is a hexadecimal counter. Every time a high-level pulse is input to the key on the panel, the rising edge will change the state of the counter in order, so that the gate The branch selected by the gate is also changed in sequence. The selected branch number is simultaneously displayed by the test branch display composed of light-emitting diodes on the panel. Due to the layout of the circuit board and the delay caused by the device to the signal, the delay of each branch is different, so the low-speed signal of the selected branch is sampled by a D flip-flop, and then sent to a 155Mb/s error detector such as (Anritsu's ME520B) for testing.

This embodiment can measure the 2.5G/bs system. If the existing BER tester is changed to a 622Mb/s BER tester, this embodiment can measure the 10Gb/s system at a split ratio of 1:16 BER; or use a BER tester capable of testing 155Mb/s and select the splitting ratio as 1:64. This embodiment can also measure the BER of a 10Gb/s system.

The indicators of this example

1. Working rate: 0.01-2.5Gb/s

2. Applicable code type: NRZ

3. m sequence length: 2 ⁷ -1, ^{2 10} -1, ^{2 15} -1

4. Level interface: high-speed code stream is ECL 50Ω

The low-speed code stream is ECL 75Ω

5. Low-speed BER tester: can measure up to 155Mb/s

6. Power supply: AC220V, 50Hz, 0.5A

Claims (4)

1, a kind of method that is used for the ultrahigh speed bit-error sampling and testing of ultrahigh speed communication system is characterized in that this method may further comprise the steps:

(1) utilize the high speed sinusoidal signal of system's input to make the m sequencer produce m sequence and high-speed clock signal at a high speed, the length of m sequence is 2 ⁿ-1, n is the progression of m sequencer;

(2) adopt start to force to put " 1 " and the method for forcing to put " 1 " when changing code length is eliminated complete 0 locking of test macro;

(3) said m sequence is delivered in the system under test (SUT) transmitted, the sequence after transmission becomes measured signal;

(4) utilize 1: the N splitter divides described m sequence measured signal and high-speed clock signal synchronously and is connected into 1/N that N road code check is former code check and the identical low speed m sequence of sequence pattern and be the low-speed clock signal of former code check 1/n;

(5) utilize test branch road selector to choose a kind of low speed signal in the said low speed m sequence and deliver in the low speed Error Detector with low-speed clock signal and to test;

(6) number of said selected low speed signal branch road shows by the branch road display.

2, adopt the code error tester of method according to claim 1, it is characterized in that by the m sequencer that links into an integrated entity, complete 0 circuit that disappears, 1: the N splitter, test branch road selector, branch road display and continuous low speed Error Detector each several part thereof are formed.

3, tester as claimed in claim 2, it is characterized in that 15 grades of shift registers that said m sequencer is made up of 15 d type flip flops, the code length selector that provides three control signals is respectively formed, one two input between monostable circuit that the rising edge that said complete 0 circuit that disappears is made up of G1 door and G2 door triggers and the SET pin that is connected said m sequencer and the G2 door or constitute.

4, as claim 2 or 3 described testers, it is characterized in that said 1: the N splitter is made up of 1: 16 a minute highway section and a timing generator, said test branch road selector selects 1 storbing gate by 16 of an ECL, one 16 system counter and a d type flip flop are formed, said branch road display is made up of a plurality of light-emitting diodes that are installed on the instrument panel, and said low speed Error Detector is the 155Mb/s Error Detector.

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