CN1061194C - Superhighspeed bit-error sampling and testing method and instrument - Google Patents
Superhighspeed bit-error sampling and testing method and instrument Download PDFInfo
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- CN1061194C CN1061194C CN94118837A CN94118837A CN1061194C CN 1061194 C CN1061194 C CN 1061194C CN 94118837 A CN94118837 A CN 94118837A CN 94118837 A CN94118837 A CN 94118837A CN 1061194 C CN1061194 C CN 1061194C
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Abstract
The present invention provides a super speed sampling and testing method and an instrument thereof, which belongs to the field of a measuring technique of a super speed communication system. The instrument comprises a m sequence generator, a removal full 0 circuit, a 1 to N shunt, a selector of a testing branch circuit, a branch circuit indicator and a low speed error code instrument. The testing method and the instrument have the characteristics of low cost, high reliability, flexible use, convenient operation, etc., and are suitable for bulk production and popularizing application.
Description
The invention belongs to the technical field of measurement and test of ultrahigh speed communication system, particularly to the method for testing of error code and the design of instrument.
Because the development of optical fiber technology, photoelectron technology and ultrahigh speed circuit engineering and contemporary society are to big capacity information transmission requirements, following primary transmission channel will carry out message transmission and exchange with the speed of Gb/s magnitude, and will become the topmost infrastructure of national information net.International telecommunication normal structure (ITU) the SDH digital synchronization series STM-1 (155Mb/s) that continues, STM-4 (622Mb/s), STM-16 (2.5Gb/s) afterwards, in the grade of synchronous digital hierarchy G.707, increased this grade of STM-64 (10Gb/s) again, the trend that the SDH transmission network develops to the higher rate direction rapidly has been described in 1993.
In the systematic research of ultra high-speed optical fiber communication, exploitation and production process, system's error performance is one of most important system performance index, the code error tester critical equipment that is absolutely necessary.
Many at present countries develop the code error tester of different class in succession, and its method of testing all is directly to utilize to pursue the sign indicating number comparative analysis on the speed of institute's examining system, carries out Error detection and statistics.Wherein extensive use be the following code error tester of 155Mb/s, this apparatus structure is simple, cost is low, can be operated on the speed of fourth order group (140Mb/s) and STM-1 (155Mb/s), but more than the speed of can't work quinary group (565Mb/s) and STM-4 (622Mb/s).
Develop the code error tester of the direct measurement formula of the 3Gb/s that can be operated in the ultrahigh speed optical fiber telecommunications system and 10Gb/s in recent years in succession, this instrument is chip used all to be must operate on the two-forty, realizes that technical difficulty is big, the cost height.
The objective of the invention is to for overcoming the weak point of prior art, propose a kind of indirect error-code testing method and design a kind of ultrahigh speed sampling method code error tester according to this method, can utilize the bit error performance of existing low speed error code testing instrument test ultrahigh speed communication system, have characteristics such as cost is low, reliability is high, use is flexible, easy to operate, be fit to batch process, popularization and application.
A kind of method that is used for the ultrahigh speed bit-error sampling and testing of ultrahigh speed communication system of the present invention may further comprise the steps:
(1) utilize the high speed sinusoidal signal of system's input to make the m sequencer produce m sequence and high-speed clock signal at a high speed, the length of m sequence is 2
n-1, n is the progression of m sequencer;
(2) adopt start to force to put " 1 " and the method for forcing to put " 1 " when changing code length is eliminated complete 0 locking of test macro;
(3) said m sequence is delivered in the system under test (SUT) transmitted, the sequence after transmission becomes measured signal;
(4) utilize 1: the N splitter divides described m sequence measured signal and high-speed clock signal synchronously and is connected into 1/N that N road code check is former code check and the identical low speed m sequence of sequence pattern and be the low-speed clock signal of former code check 1/n;
(5) utilize test branch road selector to select road low speed signal in the said low speed m sequence and deliver in the low speed Error Detector with low-speed clock signal and to test;
(6) number of said selected low speed signal branch road shows by the branch road display.
The present invention designs a kind of code error tester that adopts said method.As shown in Figure 1.It is mainly by the m sequencer, complete 0 circuit that disappears, and 1: the N splitter, test branch road selector, branch road display and low speed Error Detector several sections are formed, and wherein the low speed Error Detector is existing instrument.
The present invention has utilized such character of m sequence: code length is 2
nIf-1 m sequence is with interval S=2
q(q is an integer) sampling institute calling sequence still is 2
n-1 m sequence just has certain phase place leading with former sequence, and speed is reduced to original 1/S.For example, the m sequencer produces 2 of 2.5GGb/s
15The m sequence of-1 length, in splitter with at interval 16 (2
4=16) sampling, the 16 tunnel parallel sequences that obtain still are 2
15-1 m sequence, speed is reduced to 155Mb/s.
For optical fiber telecommunications system or other communication system, its noise source mainly contains two kinds: thermal noise and quantum noise.Thermal noise satisfies normal distribution, can describe with Gaussian random process.And quantum noise satisfies Poisson distribution, and through after the channel of communication system, channel can come equivalence with a linear time-invariant filter, and quantum noise distributes just becomes the Poisson process of a filtration.The theory analysis of random process proves that the Poisson process of Gaussian process and filtration all is a stationary random process, satisfies ergodic theorem, and its probability density and time are irrelevant.Therefore, the probability that the error code that is caused by noise produces is also irrelevant with the time, the distribution of error code be satisfy equally distributed.Sequence is behind oversampling like this, and the error rate of each subsequence that obtains is all identical with former sequence.Measure the error rate of any one subsequence, just equaled to measure the error rate of whole sequence.
The method of the invention utilizes low speed error code testing instrument to solve the error code testing problem of ultrahigh speed system, and its method realization is simple, reliable, the tester cost is low, flexible to operation, is suitable for extensively promoting the use of.
Brief Description Of Drawings:
Fig. 1 is an instrument overall structure block diagram of the present invention.
Fig. 2 is the m sequencer structural representation of an embodiment of the present invention.
Fig. 3 is complete 0 electrical block diagram that disappears of present embodiment.
Fig. 4 is 1: 16 splitter structural representation of present embodiment.
Fig. 5 is the test branch road selector structure schematic diagram of present embodiment.
The present invention proposes a kind of ultrahigh speed sampling code error tester embodiment, and it utilizes the 155Mb/s Error Detector to form the tester of the error performance of an energy measurement 2.5Gb/s system.
Present embodiment comprises the m sequencer, complete 0 circuit that disappears, and 1: 16 splitter, test branch road selector and test branch road display each several part and a 155Mb/s Error Detector are formed, and are described in detail below in conjunction with Fig. 2-5 pair of each several part structure.
1, m sequencer, as shown in Figure 2
The m sequencer is one 15 grades a shift register, a
14, a
1, a
0Be respectively the output signal of 15 d type flip flops and right shift in order, a
15Be feedback signal, it is by a
14～a
0In two taps carry out mould 2 and after obtain.Select different taps to carry out mould 2 Hes, can obtain different pseudo-random code sequences, under three kinds of specific taps are selected, can obtain the longest pseudo-random code sequence, be called the m sequence.The feedback equation of three kinds of code length correspondences is as follows:
2
7-1∶a
15=a
11Oa
8
2
10-1∶a
15=a
8Oa
5
2
15-1∶a
15=a
1Oa
0
The code length selector can provide control signal, selects a kind ofly in above three kinds of combinations, obtains the high speed m sequence of three kinds of different code lengths.
2, complete 0 circuit that disappears
If the state of each d type flip flop is 0 in the m sequencer, circuit just is in complete 0 blocking, can not produce the m sequence, that is to say that such circuit does not have self-starting function.In order to eliminate complete 0 locking, in circuit, be provided with and force two kinds of measures of set when start is forced set and changed code length.When each start, it is set to 1 state with first d type flip flop, and according to the timeticks displacement, when the set signal became low level, 15 d type flip flops all were set to 1 state, and the m sequence just can produce like this.Other reason is being arranged, as when changing bit rate or code length, might make the m sequencer of normal operation enter complete 0 blocking, therefore will change the high level pulse of code length, also as forcing set pulse, when each change code check or code length, the m sequence is restarted once simultaneously, a measure of complete 0 of disappearing is also arranged in the practical work process after start like this, be in normally in service all the time to guarantee the m sequencer.
Disappear complete 0 circuit structure as shown in Figure 3, at the set terminal (SET pin) of m sequencer, be connected to one two input or door, connecting start respectively and forcing set and change code length to force the set signal.When start, C
1The voltage at two ends is 0, and R is the internal resistance of ECL10K family chip, and-5.2V power supply is given C by R
1Charging, the charging constant is τ 1=RC1, therefore start back SET end can keep the high level of a period of time, forces set to shift register, works as C
1The voltage at two ends is during less than-1.6V, and the SET end becomes low level, and the m sequencer begins normal operation.C
1The charging finish after, the voltage at two ends be 39/ (50+39) * (5.2)=-2.28V.During shutdown, C
1Pass through R
1Discharge, time constant is τ
2=R
1C
1R
1Effect be to accelerate C
1The velocity of discharge, shortening twice start must interlude.In Fig. 3, G
1Door and G
2Door has been formed a monostable circuit that rising edge triggers, when the button A on the panel presses, at G
1The input of door produces a trigger impulse, at G
2The Q output of door just can obtain a high level pulse, and its width is by timeconstant
3=R2C2 determines.Work as timeconstant
3When being 1～3 second, can eliminate the repeated trigger that the shake by button causes effectively.Button A is the code length options button, and the high level pulse that is produced by it is exactly the code length strobe pulse, and it is also delivered to the SET pin of m sequencer, when code length of every change, simultaneously the SET pin is put once " 1 ", and the m sequence just restarts once.Issuable complete " 0 " blocking when so just having eliminated the start back because of change code check and code length.
3,1: 16 splitter
As shown in Figure 4, it is made up of 1: 16 a minute highway section and a timing generator.Timing generator is a frequency divider, and it produces two divided-frequency, four frequency divisions, eight frequency divisions, the clock signal C K/2 of 16 frequency divisions, CK/4, CK/8, CK/16 with the high-speed clock signal frequency division of input.In 1: 16 minute highway section, the high speed m sequence D in that will import with CK/2 does 1: 2 along separate routes earlier, obtain two paths of signals DATA1/2 and DATA2/2, with CK/4 and CK/8 signal above signal is proceeded along separate routes successively then, can be obtained the low-speed clock and the 16 road parallel low speed signals of 1/16 code check at last.
In fact whole splitter finishes following function: suppose that serial code stream at a high speed is that code length is 2
n-1 m sequence:
A0，A1，A2，A3，……A16，A17，……A32，A33，……
After sampling, the parallel code stream that obtains is respectively:
Q0：A0，A16，A32，……
Q1：A1，A17，A33，……
·
·
·
·
Q15：A15，A31，A47，……
Speed is 1/16 of serial code speed, and all is 2
n-1 m sequence is identical with the sequence pattern of serial code stream.
4, test branch road selector and test branch road display, as shown in Figure 5
Test branch road selector has 16 of an ECL to select 1 storbing gate, accepts 16 road parallel signals of splitter output in 1: 16.Four bit address sign indicating numbers of storbing gate select circuit to produce by branch road, it is one 16 system counter, high level pulse of the every input of the button of panel, its rising edge just makes the state of counter change in order once, and the selected branch road of storbing gate also just changes in order like this.The test branch road display that selected branch road number is made up of light-emitting diode on the panel simultaneously shows.Because the delay that relation that circuit board is set type and device produce signal, the time delay of each branch road is different, therefore the low speed signal of selected branch road with after the d type flip flop sampling, is delivered to the 155Mb/s Error Detector as testing in (ME520B of Anritsu) more again.
Present embodiment can be measured the 2.5G/bs system, changes the Error Detector that can test 622Mb/s into if will have Error Detector, just can measure the error code of 10Gb/s system along separate routes than following present embodiment at 1: 16; Or utilize the Error Detector that can test 155Mb/s, and will be along separate routes than electing 1: 64 as, present embodiment also can be measured the error rate of 10Gb/s system.
The index of present embodiment
1. operating rate: 0.01-2.5Gb/s
2. be suitable for sign indicating number type: NRZ
3.m sequence length: 2
7-1,2
10-1,2
15-1
4. electric level interface: high-speeld code-flow is ECL 50 Ω
The low speed code stream is ECL 75 Ω
5. low speed Error Detector: can measure 155Mb/s
6. power supply: AC220V, 50Hz, 0.5A
Claims (4)
1, a kind of method that is used for the ultrahigh speed bit-error sampling and testing of ultrahigh speed communication system is characterized in that this method may further comprise the steps:
(1) utilize the high speed sinusoidal signal of system's input to make the m sequencer produce m sequence and high-speed clock signal at a high speed, the length of m sequence is 2
n-1, n is the progression of m sequencer;
(2) adopt start to force to put " 1 " and the method for forcing to put " 1 " when changing code length is eliminated complete 0 locking of test macro;
(3) said m sequence is delivered in the system under test (SUT) transmitted, the sequence after transmission becomes measured signal;
(4) utilize 1: the N splitter divides described m sequence measured signal and high-speed clock signal synchronously and is connected into 1/N that N road code check is former code check and the identical low speed m sequence of sequence pattern and be the low-speed clock signal of former code check 1/n;
(5) utilize test branch road selector to choose a kind of low speed signal in the said low speed m sequence and deliver in the low speed Error Detector with low-speed clock signal and to test;
(6) number of said selected low speed signal branch road shows by the branch road display.
2, adopt the code error tester of method according to claim 1, it is characterized in that by the m sequencer that links into an integrated entity, complete 0 circuit that disappears, 1: the N splitter, test branch road selector, branch road display and continuous low speed Error Detector each several part thereof are formed.
3, tester as claimed in claim 2, it is characterized in that 15 grades of shift registers that said m sequencer is made up of 15 d type flip flops, the code length selector that provides three control signals is respectively formed, one two input between monostable circuit that the rising edge that said complete 0 circuit that disappears is made up of G1 door and G2 door triggers and the SET pin that is connected said m sequencer and the G2 door or constitute.
4, as claim 2 or 3 described testers, it is characterized in that said 1: the N splitter is made up of 1: 16 a minute highway section and a timing generator, said test branch road selector selects 1 storbing gate by 16 of an ECL, one 16 system counter and a d type flip flop are formed, said branch road display is made up of a plurality of light-emitting diodes that are installed on the instrument panel, and said low speed Error Detector is the 155Mb/s Error Detector.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN94118837A CN1061194C (en) | 1994-12-09 | 1994-12-09 | Superhighspeed bit-error sampling and testing method and instrument |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN94118837A CN1061194C (en) | 1994-12-09 | 1994-12-09 | Superhighspeed bit-error sampling and testing method and instrument |
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| Publication Number | Publication Date |
|---|---|
| CN1115927A CN1115927A (en) | 1996-01-31 |
| CN1061194C true CN1061194C (en) | 2001-01-24 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN94118837A Expired - Fee Related CN1061194C (en) | 1994-12-09 | 1994-12-09 | Superhighspeed bit-error sampling and testing method and instrument |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100372280C (en) * | 2005-11-04 | 2008-02-27 | 清华大学 | Device for testing time characteristic of outburst and error rate in outburst optical fiber transmission system |
| US8630821B2 (en) | 2011-07-25 | 2014-01-14 | Qualcomm Incorporated | High speed data testing without high speed bit clock |
| CN107493202B (en) * | 2017-09-29 | 2024-03-22 | 珠海思开达技术有限公司 | Extensible high-speed error code tester |
| CN110120856B (en) * | 2019-04-29 | 2021-07-23 | 西安微电子技术研究所 | Test vector generation and detection system and method for multi-type test sequences |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0523571A1 (en) * | 1991-07-19 | 1993-01-20 | Anritsu Corporation | Advanced code error detection apparatus and system using maximal-length pseudorandom binary sequence |
| CN2130015Y (en) * | 1992-08-06 | 1993-04-14 | 机械电子工业部石家庄第五十四研究所 | Multifunction error code measurer |
-
1994
- 1994-12-09 CN CN94118837A patent/CN1061194C/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0523571A1 (en) * | 1991-07-19 | 1993-01-20 | Anritsu Corporation | Advanced code error detection apparatus and system using maximal-length pseudorandom binary sequence |
| CN2130015Y (en) * | 1992-08-06 | 1993-04-14 | 机械电子工业部石家庄第五十四研究所 | Multifunction error code measurer |
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|---|---|
| CN1115927A (en) | 1996-01-31 |
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