CN106098710A - A kind of array base palte and preparation method thereof, display device - Google Patents
A kind of array base palte and preparation method thereof, display device Download PDFInfo
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- CN106098710A CN106098710A CN201610763438.4A CN201610763438A CN106098710A CN 106098710 A CN106098710 A CN 106098710A CN 201610763438 A CN201610763438 A CN 201610763438A CN 106098710 A CN106098710 A CN 106098710A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 106
- 239000010409 thin film Substances 0.000 claims abstract description 32
- 239000010408 film Substances 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 12
- 238000000059 patterning Methods 0.000 claims description 9
- 239000004973 liquid crystal related substance Substances 0.000 claims description 6
- 239000007769 metal material Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 26
- 230000004888 barrier function Effects 0.000 abstract 6
- 238000004070 electrodeposition Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 11
- 239000002184 metal Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000002161 passivation Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000007641 inkjet printing Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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Abstract
The embodiment of the present invention provides a kind of array base palte and preparation method thereof, display device, relate to Display Technique field, when electrode is connected with drain electrode by via in array base palte, it is possible to reduce the drop of via area, reduce electrode and the probability that loose contact occurs that drains in this via area.This array base palte includes the thin film transistor (TFT) being arranged on underlay substrate, and be successively set on thin film transistor (TFT) the first insulating barrier, the second insulating barrier, the first electrode, at the drain electrode position of thin film transistor (TFT), first insulating barrier has the first via, second insulating barrier has the second via, this array base palte also includes: the conductive pattern between the first insulating barrier and the second insulating barrier, conductive pattern cover the first via and and drain contact, the first electrode covers the second via and contacts with conductive pattern.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a preparation method of the array substrate and a display device.
Background
With the continuous improvement of display technology, the demand of people for display devices is also increasing, and among various display technologies, optoelectronic products such as Thin Film Transistor displays, which use TFTs (Thin Film transistors) as control elements and integrate large-scale semiconductor integrated circuits and flat panel light source technologies, become a new generation of mainstream display products with the advantages of low power consumption, convenience in carrying, wide application range, high quality, and the like.
Taking a TFT-LCD (Thin Film Transistor Liquid Crystal Display) as an example, as shown in fig. 1, an array substrate in the Display includes a Thin Film Transistor 100, a common electrode 20 and a pixel electrode 30 disposed on a substrate 10, wherein the pixel electrode 30 is far from the Thin Film Transistor 100 relative to the common electrode 20, and the pixel electrode 30 is connected to a drain 101 of the Thin Film Transistor 100 through a via 40.
However, as shown in fig. 1, since the distance between the pixel electrode 30 and the drain 101 in the direction perpendicular to the substrate 10 is large, the height H of the drop height of the via hole 40 is large, the slope of the side surface of the via hole 40 is steep, and since the thin film layer of the pixel electrode 30 is thin, when depositing the thin film layer of the pixel electrode 30, uneven deposition is likely to occur at the side surface and the bottom surface of the via hole 40, which easily causes a problem of poor contact between the pixel electrode 30 and the drain 101, and particularly when the array substrate is applied to a curved or flexible display product, the uneven film layer is likely to break or the like at the via hole 40 during bending, which causes poor display.
Disclosure of Invention
The embodiment of the invention provides an array substrate, a preparation method thereof and a display device.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
an embodiment of the present invention provides an array substrate, including: the thin film transistor structure comprises a thin film transistor arranged on a substrate, and a first insulating layer, a second insulating layer and a first electrode which are arranged on the thin film transistor in sequence, wherein the first insulating layer is provided with a first through hole, and the second insulating layer is provided with a second through hole; the array substrate further includes: a conductive pattern between the first and second insulating layers, the conductive pattern covering the first via and contacting the drain, the first electrode covering the second via and contacting the conductive pattern.
Further, the array substrate further comprises a second electrode located between the second insulating layer and the first insulating layer, and in the sub-pixel region, the first electrode and the second electrode are oppositely arranged along the vertical direction of the substrate.
Furthermore, the array substrate further comprises a touch control electrode wire positioned between the second insulating layer and the first insulating layer, and the touch control electrode wire is in contact with the surface of the second electrode.
Furthermore, the touch electrode line is located on the surface of the second electrode on the side away from the substrate base plate.
Further, the thickness of the touch electrode line is greater than that of the second electrode.
Further, the touch electrode line is made of a metal material.
Further, the conductive pattern and the second electrode are made of the same material in the same layer; or the conductive pattern and the touch electrode line are made of the same material on the same layer; or the conductive pattern comprises a first conductive electronic pattern and a second conductive electronic pattern which are arranged in a stacked mode, the first conductive electronic pattern and the second electrode are made of the same material on the same layer, and the second conductive electronic pattern and the touch electrode line are made of the same material on the same layer.
In another aspect, a display device is provided, which includes the array substrate as claimed in any one of the above claims.
Further, in the case that the array substrate includes a first electrode and a second electrode: the display device is a liquid crystal display device, the first electrode is a pixel electrode, and the second electrode is a common electrode; or, the display device is an organic light emitting display device, the first electrode is an anode, and the second electrode is a cathode; or, the first electrode is a cathode and the second electrode is an anode.
In another aspect, an embodiment of the present invention further provides a method for manufacturing an array substrate, including: forming a thin film transistor on a substrate; forming a first insulating layer on the substrate on which the thin film transistor is formed, the first insulating layer having a first via hole at a position corresponding to a drain of the thin film transistor; forming a first conductive film on the substrate base plate with the first insulating layer, and patterning the first conductive film to form a first conductive layer, wherein the first conductive layer comprises a conductive pattern covering the first via hole; forming a second insulating layer on the substrate on which the first conductive layer is formed, the second insulating layer having a second via hole at a position corresponding to the conductive pattern; and forming a first electrode on the substrate with the second insulating layer, wherein the first electrode covers the second via hole and is in contact with the conductive pattern.
The embodiment of the invention provides an array substrate, a preparation method thereof and a display device, wherein the array substrate comprises a thin film transistor arranged on a substrate, and a first insulating layer, a second insulating layer and a first electrode which are sequentially arranged on the thin film transistor; the array substrate further comprises a conductive pattern located between the first insulating layer and the second insulating layer, the conductive pattern covers the first through hole and is in contact with the drain electrode, and the first electrode covers the second through hole and is in contact with the conductive pattern.
Since the first via hole in the first insulating layer and the second via hole in the second insulating layer are both located at the position of the drain electrode of the thin film transistor, when the first electrode covers the second via hole, the first electrode is in contact with the conductive pattern covering the first via hole, connected to the drain electrode through the conductive pattern, thus, compared to the prior art in which the first electrode needs to be connected to the drain electrode across the entire step height of the first via and the second via in the direction perpendicular to the substrate, in the present invention, the first electrode is connected to the drain electrode through the conductive pattern, since the conductive pattern covering the first via hole has a certain thickness, so that the step height spanned by the first electrode in the via hole area is reduced, and then reduced the probability that phenomenon such as fracture appears in the via hole region at first electrode, reduced the probability that contact failure appears when first electrode is connected with the drain electrode.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an array substrate provided in the prior art;
fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 8 is a flowchart illustrating a method for manufacturing an array substrate according to an embodiment of the invention;
fig. 9a is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 9b is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 9c is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 9d is a schematic structural diagram of an array substrate according to an embodiment of the invention.
Reference numerals:
01-an array substrate; 10-a substrate base plate; 20-a common electrode; 30-pixel electrodes; 40-via holes; 41-a first via; 42-a second via; 50-touch electrodes; 100-thin film transistors; 101-a drain; 110-a first insulating layer; 120-a second insulating layer; 201-a first electrode; 202-a second electrode; 300-a conductive pattern; 301-a first conductive electronic pattern; 302-second conductive electronic pattern.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides an array substrate, as shown in fig. 2, the array substrate 01 includes: in the case where the first insulating layer 110 has the first via hole 41 and the second insulating layer 120 has the second via hole 42 at the position of the drain 101 of the thin film transistor 100, since the first via hole 41 and the second via hole 42 correspond to each other in position, the total height of the first via hole 41 and the second via hole 42 is H1, which is the sum of the height of the first via hole 41 and the height of the second via hole 42.
On this basis, as shown in fig. 2, the array substrate 01 further includes: and a conductive pattern 300 between the first insulating layer 110 and the second insulating layer 120, wherein the conductive pattern 300 covers the first via hole 41 and contacts the drain electrode 101, and since the conductive pattern 300 covering the first via hole 41 has a certain thickness, a step height H2 of the via hole region is a total step height H1 of the first via hole 41 and the second via hole 42 minus the thickness of the conductive pattern 300, in which case the first electrode 201 covers the second via hole 42 and contacts the conductive pattern 300.
Therefore, compared with the prior art that the first electrode crosses the whole drop height of the first via hole and the second via hole in the direction vertical to the substrate and is connected with the drain electrode, in the invention, the first electrode covers the second via hole and is in contact with the conductive pattern, and the drop height H2 of the via hole area is smaller than the total drop height H1, so that the probability of phenomena of breakage and the like of the first electrode in the via hole area is reduced, and the probability of poor contact when the first electrode is electrically connected with the drain electrode is reduced.
Here, in the array substrate 01, another light shielding layer, a signal line, an electrode, and the like are generally disposed between two insulating layers, namely, the second insulating layer 110 and the first insulating layer 120, which are sequentially disposed.
Specifically, for example, as shown in fig. 3, a second electrode 202 is disposed between the second insulating layer 120 and the first insulating layer 110, and in the subpixel region, the first electrode 201 and the second electrode 202 are disposed opposite to each other in the vertical direction of the substrate base plate 10.
The application of the array substrate 01 including the first electrode 201 and the second electrode 202 disposed oppositely in a display device is further described below.
For example, as shown in fig. 3, the array substrate 01 may be an ADS (Advanced-Super Dimensional Switching) type array substrate in an LCD (Liquid Crystal Display), wherein the first electrode 201 is a pixel electrode and includes a plurality of strip-shaped sub-electrodes, and the second electrode 202 is a common electrode. The first insulating layer 110 and the second insulating layer 120 are both passivation layers.
For another example, as shown in fig. 4, the array substrate 01 may also be an array substrate in an OLED (Organic Light emitting display), in which the first electrode 201 is an anode and the second electrode 202 is a cathode, or the first electrode 201 is a cathode and the second electrode 202 is an anode. The first insulating layer 110 is a passivation layer, and the second insulating layer 120 is a pixel defining layer.
The following embodiments are all examples in which the array substrate 01 is an ADS type array substrate, and the invention is further described.
In order to make the array substrate 01 have the functions of the array substrate itself and also have the touch function, as shown in fig. 5, the array substrate 01 further includes a touch electrode line 50 located between the second insulating layer 120 and the first insulating layer 110, and the touch electrode line 50 is in contact with the surface of the second electrode 202 (i.e., the common electrode 20).
It should be noted that the touch electrode line 50 includes a portion disposed on the surface of the common electrode 20 and contacting with the surface of the common electrode, and also includes a trace portion disposed on the peripheral area of the array substrate, and the input and output of the touch signal are performed through the trace of the portion. In this case, the second electrode 202 serves as a common electrode in the display stage and serves as a touch electrode in the touch stage, so that when the array substrate is applied to a display device, a touch display function can be realized in the process of alternately performing the display stage (e.g., 0.01s) and the touch stage (e.g., 0.005 s).
In addition, the touch electrode line 50 is generally made of a metal material, and because the resistance of the metal is small, the portion of the touch electrode line 50 contacting the surface of the common electrode 20 is equivalent to a small resistance connected in parallel on the common electrode 20, so that the resistance of the common electrode 20 can be reduced, and the load of the entire array substrate is reduced.
It should be further noted that the touch electrode line 50 is in contact with the surface of the second electrode 202, and may be the touch electrode line 50 is in contact with the upper surface of the second electrode 202, that is, as shown in fig. 5, the touch electrode line 50 is located on a side of the second electrode 202 away from the substrate 10; of course, the touch electrode line 50 may also be in contact with the lower surface of the second electrode 202, that is, the touch electrode line 50 is located on the side of the second electrode 202 close to the substrate base plate 10.
On this basis, when the touch electrode line 50 is in contact with the upper surface of the second electrode 202, the touch electrode line 50 is in direct contact with the second electrode 202, and the surface of the touch electrode line 50 is smaller than that of the second electrode 201, so that the touch electrode line 50 and the second electrode 202 can be formed by one-time patterning through a half-exposure mask process. When the touch electrode line 50 contacts the lower surface of the second electrode 202, the touch electrode line 50 and the second electrode 202 must be formed by two patterning processes.
In addition, since the touch electrode line 50 is mostly made of metal, the second electrode 202 serving as the common electrode is mostly made of transparent conductive material, and the thickness of the touch electrode line 50 made of metal is greater than that of the common electrode 20 made of transparent conductive material, so that if the touch electrode line 50 is located on the lower surface of the common electrode 20, the touch electrode line 50 is easily located at the edge position of the touch electrode line 50, so that the transparent conductive film forming the common electrode 20 is easily broken; the above disadvantage does not occur when the control electrode line 50 is located on the upper surface of the common electrode 20.
In summary, in the present invention, preferably, the thickness of the touch electrode line 50 is greater than the thickness of the second electrode 202; the touch electrode line 50 is located on a surface of the first electrode 201 on a side away from the substrate base plate 10.
The specific arrangement of the conductive pattern 300 will be further described below.
For example, as shown in fig. 5, the conductive pattern 300 and the second electrode 202 are disposed in the same layer and the same material, so that the height of the via hole is reduced, and the conductive pattern 300 and the second electrode 202 can be formed by a single patterning process, thereby achieving the purposes of simplifying the process and reducing the manufacturing cost.
For another example, as shown in fig. 6, the conductive pattern 300 and the touch electrode line 50 are made of the same material in the same layer, and the conductive pattern 300 and the touch electrode line 50 can be formed by a one-step patterning process while the height of the via hole area is reduced, so as to achieve the purposes of simplifying the process and reducing the manufacturing cost.
On this basis, when the touch electrode line 50 and the conductive pattern 300 are made of metal, on one hand, compared with the case that the conductive pattern 300 and the second electrode 202 (the common electrode 20) are made of transparent conductive materials, the conductive pattern 300 made of metal has better conductivity, so that the conduction effect between the pixel electrode 30 and the drain electrode 101 is better; on the other hand, the thickness of the metal film is generally larger, so that the drop height of the via hole area is reduced; on the other hand, the metal film has good flexibility, so that the array substrate is more suitable for being applied to a flexible display device, and normal conduction between the conductive pattern 300 and the drain 101 can be effectively ensured when the via hole region is bent or bent.
For another example, as shown in fig. 7, the conductive pattern 300 includes a first conductive sub-pattern 301 and a second conductive sub-pattern 302 that are stacked, the first conductive sub-pattern 301 and the second electrode 201 are made of the same material in the same layer, and the second conductive sub-pattern 302 and the touch electrode line 50 are made of the same material in the same layer. In this way, the first conductive electronic pattern 301 and the second electrode 201 are formed through a one-time composition process, and the second conductive electronic pattern 302 and the touch electrode line 50 are formed through a one-time composition process, so that the process can be simplified, the manufacturing cost can be reduced, and meanwhile, the first conductive electronic pattern 301 and the second conductive electronic pattern 302 can be simultaneously covered on the via hole area, and the drop height of the via hole area can be further effectively reduced.
It should be noted that, in the present invention, the patterning process may refer to a process including a photolithography process, or a photolithography process and an etching step, and may also include other processes for forming a predetermined pattern, such as printing, ink-jetting, etc.; the photolithography process refers to a process of forming a pattern by using a photoresist, a mask plate, an exposure machine, and the like, including processes of film formation, exposure, development, and the like. The corresponding patterning process may be selected according to the structure formed in the present invention.
In another aspect, the present invention further provides a display device, which includes any one of the array substrates described above, and has the same structure and beneficial effects as the array substrate provided in the foregoing embodiment. Since the foregoing embodiments have described the structure and the beneficial effects of the array substrate in detail, the details are not repeated herein.
Here, in the case where the array substrate 01 includes the first electrode 201 and the second electrode 202:
the display device may be a liquid crystal display device formed by the ADS type array substrate 01 and the opposite box substrate shown in fig. 3, and a liquid crystal layer between the ADS type array substrate 01 and the opposite box substrate, wherein the first electrode 201 is a pixel electrode and includes a plurality of strip-shaped sub-electrodes, the second electrode 202 is a common electrode, and both the first insulating layer 110 and the second insulating layer 120 are passivation layers.
The display device may also be an organic light emitting display device formed by the array substrate shown in fig. 4, wherein the first electrode 201 is an anode and the second electrode 202 is a cathode, or the first electrode 201 is a cathode and the second electrode 202 is an anode. The first insulating layer 110 is a passivation layer, and the second insulating layer 120 is a pixel defining layer. Of course, a light emitting function layer is provided between the first electrode 201 and the second electrode 202.
In the case where the display device is an organic light-emitting display device, when the first electrode 201 is a reflective electrode and the second electrode 202 is a transmissive electrode, the display device is a bottom emission type; when the first electrode 201 is a transmissive electrode and the second electrode 202 is a reflective electrode, the display device is a top-emission type, which is not limited in the present invention.
It should be further noted that, for the array substrate constituting the OLED, compared with the ADS type array substrate constituting the LCD, the arrangement forms of the touch electrode lines 50 and the conductive patterns 300 and the related principle processes of the two array substrates are similar, and are not further described herein.
An embodiment of the present invention further provides a method for manufacturing an array substrate, as shown in fig. 8, the method includes:
in step S101, as shown in fig. 9a, a thin film transistor 100 is formed on a substrate 10, wherein the thin film transistor 100 includes a gate electrode, a source electrode, and a drain electrode 101.
In step S102, as shown in fig. 9b, a first insulating layer 110 is formed on the substrate 10 on which the thin film transistor 100 is formed, the first insulating layer 110 having the first via hole 41 at a position corresponding to the drain 101 of the thin film transistor 100.
Step S103, as shown in fig. 9c, a first conductive film is formed on the substrate 10 on which the first insulating layer 110 is formed, and the first conductive film is patterned to form a first conductive layer including the conductive pattern 300 covering the first via hole 41.
Fig. 9c illustrates only that the first conductive layer is formed by patterning the first conductive film, and only the conductive pattern 300 is included in the first conductive layer, in practical applications, the first conductive layer may further include a second electrode 202, for example, the common electrode 20 in fig. 3, or the cathode or the anode in fig. 4.
Step S104, as shown in fig. 9d, a second insulating layer 120 is formed on the substrate formed with the first conductive layer (including the conductive pattern 300), and the second insulating layer 120 has a second via hole 42 at a position corresponding to the conductive pattern 300.
In step S105, as shown in fig. 2, a first electrode 201 is formed on the substrate 10 on which the second insulating layer 120 is formed, and the first electrode 201 covers the second via hole 42 and contacts the conductive pattern 300.
When the first conductive layer formed in step S103 further includes the second electrode 202 disposed opposite to the first electrode 201 along the vertical direction of the substrate 10, the ADS-type array substrate shown in fig. 2 is only used as the first conductive layer, and the first electrode 201 is a pixel electrode; of course, the array substrate in the OLED shown in fig. 4 may also be used, where the first electrode 201 is an anode when the second electrode 202 is a cathode, or the first electrode 201 is a cathode when the second electrode 202 is an anode.
Of course, after step S105, a planarization layer or a protection layer may be further formed, and the forming method thereof is the same as that in the prior art, and is not repeated here.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. An array substrate, comprising: the thin film transistor structure comprises a thin film transistor arranged on a substrate, and a first insulating layer, a second insulating layer and a first electrode which are arranged on the thin film transistor in sequence, wherein the first insulating layer is provided with a first through hole, and the second insulating layer is provided with a second through hole;
the array substrate further includes: a conductive pattern between the first and second insulating layers, the conductive pattern covering the first via and contacting the drain, the first electrode covering the second via and contacting the conductive pattern.
2. The array substrate of claim 1, further comprising a second electrode between the second insulating layer and the first insulating layer, wherein the first electrode and the second electrode are disposed opposite to each other in a vertical direction of the substrate in a sub-pixel region.
3. The array substrate of claim 2, further comprising a touch electrode line between the second insulating layer and the first insulating layer, wherein the touch electrode line is in contact with a surface of the second electrode.
4. The array substrate of claim 3, wherein the touch electrode line is located on a surface of the second electrode facing away from the substrate.
5. The array substrate of claim 3 or 4, wherein the touch electrode line has a thickness greater than a thickness of the second electrode.
6. The array substrate of claim 3 or 4, wherein the touch electrode lines are made of a metal material.
7. The array substrate of claim 3 or 4,
the conductive pattern and the second electrode are made of the same material at the same layer;
or the conductive pattern and the touch electrode line are made of the same material on the same layer;
or the conductive pattern comprises a first conductive electronic pattern and a second conductive electronic pattern which are arranged in a stacked mode, the first conductive electronic pattern and the second electrode are made of the same material on the same layer, and the second conductive electronic pattern and the touch electrode line are made of the same material on the same layer.
8. A display device comprising the array substrate according to any one of claims 1 to 7.
9. The display device according to claim 8, wherein in a case where the array substrate includes a first electrode and a second electrode:
the display device is a liquid crystal display device, the first electrode is a pixel electrode, and the second electrode is a common electrode;
or,
the display device is an organic light-emitting display device, the first electrode is an anode, and the second electrode is a cathode; or, the first electrode is a cathode and the second electrode is an anode.
10. A preparation method of an array substrate is characterized by comprising the following steps:
forming a thin film transistor on a substrate;
forming a first insulating layer on the substrate on which the thin film transistor is formed, the first insulating layer having a first via hole at a position corresponding to a drain of the thin film transistor;
forming a first conductive film on the substrate base plate with the first insulating layer, and patterning the first conductive film to form a first conductive layer, wherein the first conductive layer comprises a conductive pattern covering the first via hole;
forming a second insulating layer on the substrate on which the first conductive layer is formed, the second insulating layer having a second via hole at a position corresponding to the conductive pattern;
and forming a first electrode on the substrate with the second insulating layer, wherein the first electrode covers the second via hole and is in contact with the conductive pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610763438.4A CN106098710A (en) | 2016-08-29 | 2016-08-29 | A kind of array base palte and preparation method thereof, display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610763438.4A CN106098710A (en) | 2016-08-29 | 2016-08-29 | A kind of array base palte and preparation method thereof, display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106654048A (en) * | 2016-12-27 | 2017-05-10 | 武汉华星光电技术有限公司 | Top light-emitting OLED display unit, manufacturing method thereof and display panel |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102411237A (en) * | 2010-09-20 | 2012-04-11 | 乐金显示有限公司 | Liquid crystal display device and method for manufacturing the same |
| US20130257794A1 (en) * | 2012-03-29 | 2013-10-03 | Lg Display Co., Ltd. | Liquid crystal display device and method of manufacturing the same |
| CN104516614A (en) * | 2013-09-26 | 2015-04-15 | 业鑫科技顾问股份有限公司 | Touch device |
-
2016
- 2016-08-29 CN CN201610763438.4A patent/CN106098710A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102411237A (en) * | 2010-09-20 | 2012-04-11 | 乐金显示有限公司 | Liquid crystal display device and method for manufacturing the same |
| US20130257794A1 (en) * | 2012-03-29 | 2013-10-03 | Lg Display Co., Ltd. | Liquid crystal display device and method of manufacturing the same |
| CN104516614A (en) * | 2013-09-26 | 2015-04-15 | 业鑫科技顾问股份有限公司 | Touch device |
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