CN106098698B - Array substrate and preparation method thereof, display device - Google Patents
Array substrate and preparation method thereof, display device Download PDFInfo
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- CN106098698B CN106098698B CN201610453098.5A CN201610453098A CN106098698B CN 106098698 B CN106098698 B CN 106098698B CN 201610453098 A CN201610453098 A CN 201610453098A CN 106098698 B CN106098698 B CN 106098698B
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- 239000000758 substrate Substances 0.000 title claims abstract description 56
- 238000002360 preparation method Methods 0.000 title abstract 2
- 238000000034 method Methods 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 15
- 239000010409 thin film Substances 0.000 claims description 15
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 19
- 238000000059 patterning Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 230000000903 blocking effect Effects 0.000 description 2
- 208000036252 interstitial lung disease 1 Diseases 0.000 description 2
- 208000036971 interstitial lung disease 2 Diseases 0.000 description 2
- 208000029523 Interstitial Lung disease Diseases 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Theoretical Computer Science (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The present invention provides a kind of array substrates and preparation method thereof, display device, wherein gate driving circuit scattering device is in the region between adjacent rows sub-pixel unit.In this manner it is possible to not make gate driving circuit in the side edge of array substrate, so that corresponding region can also be used as display area, the width of the frame region of array substrate can be thus further decreased.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a manufacturing method of the array substrate and a display device.
Background
In order to achieve a narrow frame of a display device, a design of a Gate Driver On Array (GOA) is proposed in the prior art. Referring to fig. 1, in the prior art, a Gate driving circuit (including a plurality of GOA units) is generally fabricated at two side edges of an array substrate through a patterning process, a driving signal line CLK for driving the Gate driving circuit is disposed at the side edge in addition to the GOA units, and is located at two sides of a display region (a plurality of sub-pixel arrays are formed in the display region, where the sub-pixel is represented by P, and a plurality of Data lines Data and a plurality of Gate lines Gate, where the nth Gate line is represented by Gate).
The main structure of the gate driving circuit is generally made of opaque materials such as metal, so in the prior art, the side edge is not generally used as a display area to emit light. The gate driving circuit occupies a certain space, so that the corresponding display device still has the problem of wide frame.
Disclosure of Invention
One object of the present invention is to reduce the bezel width of a display device.
In a first aspect, the present invention provides an array substrate, including: the pixel driving circuit comprises a substrate, a sub-pixel unit array, a grid line, a data line, a grid driving circuit and a driving signal line, wherein the sub-pixel unit array is formed on the substrate; wherein,
the gate driving circuits are dispersedly arranged in the plurality of first non-opening regions, and the dispersedly arranged parts are electrically connected with each other through connecting lines extending along the direction of the data lines;
the first non-opening area is an area between two adjacent rows of sub-pixel units.
Furthermore, the gate driving circuit comprises a plurality of groups of shift register units, the plurality of groups of shift register units are dispersedly arranged in a plurality of first non-opening areas, and each group of shift register units is only arranged in the same first non-opening area; each group of shift register units is used for outputting at least one scanning pulse in one frame.
Furthermore, each group of shift register units is connected with N grid lines nearest to the group of shift register units through connecting lines; wherein, N is the number of the scanning pulses output by a group of shift register units in one frame.
Furthermore, the gate line connected to the sub-pixel unit in the row on the first side in the two sub-pixel units in the two rows on both sides of the first non-opening area where the gate driving circuit is located in the first non-opening area on the first side of the sub-pixel unit in the row, and the gate line connected to the sub-pixel unit in the row on the second side is located in the first non-opening area on the second side of the sub-pixel unit in the row.
Furthermore, two grid lines are arranged in one of every two adjacent first non-opening areas, and each grid line is connected with a row of sub-pixel units close to the grid line; a group of shift register units are arranged in the other first non-opening area; each group of shift register units is used for outputting two scanning pulses in one frame.
Further, the gate driving circuit and the sub-pixel unit array comprise a plurality of thin film transistors; the grid electrodes of the thin film transistors are positioned on one side of the active layer, which is far away from the substrate; the array substrate further comprises a light shielding pattern which is arranged on one side of the active layer, which is far away from the grid electrode, and is used for shielding a channel region of the thin film transistor;
the driving signal line and the light-shielding pattern are formed in the same layer.
Further, the light shielding pattern is electrically connected to the driving signal line.
Further, the shading graph is suitable for being reused as a touch electrode graph.
In a second aspect, the present invention provides a method for manufacturing an array substrate, including: the pixel driving circuit comprises a sub-pixel unit array, a grid line, a data line, a grid driving circuit and a driving signal line, wherein the sub-pixel unit array is formed on a substrate; wherein,
the gate driving circuits are dispersedly arranged in the plurality of first non-opening regions, and the dispersedly arranged parts are electrically connected with each other through connecting lines extending along the direction of the data lines;
the first non-opening area is an area between two adjacent rows of sub-pixel units.
In a third aspect, the present invention provides a display device comprising the array substrate of any one of the above.
In the array substrate provided by the invention, the gate driving circuits are dispersedly arranged in the area between two adjacent rows of sub-pixel units. Therefore, a gate driving circuit is not required to be manufactured at the side edge of the array substrate, so that the corresponding area can also be used as a display area, and the width of the frame area of the array substrate can be further reduced.
Drawings
The characteristic information and advantages of the invention will be more clearly understood by reference to the accompanying drawings, which are schematic and should not be understood as imposing any limitation on the invention, in which:
fig. 1 is a schematic structural diagram of an array substrate in the prior art;
fig. 2 is a schematic structural diagram of a partial structure of an array substrate according to an embodiment of the present invention;
fig. 3a and fig. 3b are schematic structural diagrams of a part of the structure of an array substrate according to an embodiment of the invention;
fig. 4 is a schematic view of a manufacturing process of an array substrate according to the present invention.
Detailed Description
In order that the above objects, features and advantages of the present invention can be more clearly understood, a more particular description of the invention will be rendered by reference to the appended drawings. It should be noted that the embodiments and features of the embodiments of the present application may be combined with each other without conflict.
The invention provides an array substrate, which comprises a substrate, a sub-pixel unit array, a grid line, a data line, a grid driving circuit and a driving signal line, wherein the sub-pixel unit array is formed on the substrate; wherein,
the gate driving circuits are dispersedly arranged in the plurality of first non-opening regions, and the dispersedly arranged parts are electrically connected with each other through connecting lines extending along the direction of the data lines;
the first non-opening area is an area between two adjacent rows of sub-pixel units. .
In the array substrate provided by the invention, the gate driving circuits are dispersedly arranged in the area between two adjacent rows of sub-pixel units. Therefore, a gate driving circuit is not required to be manufactured at the side edge of the array substrate, so that the corresponding area can also be used as a display area, and the width of the frame area of the array substrate can be further reduced. In addition, since the partial region is a region disposed between two adjacent rows of the sub-pixel units, the partial region generally corresponds to the position of the black matrix, and therefore, the aperture ratio of the sub-pixel unit is not greatly affected.
Some embodiments of the array substrate are described in detail below with reference to the accompanying drawings. Referring to fig. 2, there is shown a schematic structural view of a part of the structure in one embodiment of the array member; the gate driving circuit GOA includes a plurality of shift register units (shown as GOA units in the figure) arranged in a dispersed manner, and the GOA units are connected into an integrated gate driving circuit GOA through connecting lines (the connecting lines are not shown in the figure); each GOA cell is disposed in a region between two adjacent rows of sub-pixel cells P (hereinafter, referred to as a first non-opening region for convenience of description) for outputting a scan pulse. Therefore, GOAs do not need to be arranged on two sides of the display area A, the frame area can be designed to be smaller or not arranged at all, and the edge narrowing can be realized.
In specific implementation, on the premise that the gate driving circuits GOA are dispersedly arranged in the region between two adjacent rows of the sub-pixel units P, the protection scope of the present invention is not affected no matter how the gate driving circuits GOA are split. In the embodiment shown in fig. 2, the GOA is divided into a plurality of GOA units and distributed, which is only an alternative implementation. Because one GOA unit is a relatively complete basic functional unit capable of outputting one or more scanning pulses, the design and manufacturing difficulty of the array substrate can be lower due to the arrangement, and the control is convenient subsequently.
As can be seen from the above description, in the implementation, on the premise that the gate driving circuits GOA are dispersedly disposed in the region between two adjacent rows of the sub-pixel units P, the protection scope of the present invention is not affected much no matter where the connection lines and the driving signal lines (such as clock signal lines, herein denoted as CLK) for driving the gate driving circuits are disposed. Fig. 2 shows an arrangement of the connection lines and the driving signal lines CLK, which are disposed in a region between two adjacent columns of the sub-pixel units P (for convenience of description, the region between two adjacent columns of the sub-pixel units P is defined as a second non-opening region). In this way, since neither the connection line nor the drive signal line CLK is provided in the frame region, the width of the frame region can be further reduced. Of course, in a specific application, both the connection lines and the driving signal lines CLK may be disposed in the frame region, or only the connection lines or the driving signal lines CLK may be disposed in the frame region.
Typically, one gate line is disposed in each of the first non-opening regions. However, in the process of implementing the present invention, the inventors found that, when a part of the GOA circuit is disposed in the first non-opening region, if the gate line is also disposed in the first non-opening region where the GOA circuit is located, it is relatively difficult to arrange the gate line reasonably, and the manufacturing difficulty is large. On this basis, the embodiment of the present invention further provides another alternative design, referring to fig. 2, for a GOA unit, the gate line connected to the upper row of sub-pixel units P is located in the first non-opening region above the row of sub-pixel units P, and the gate line connected to the lower row of sub-pixel units P is located in the first non-opening region below the row of sub-pixel units P. Therefore, the grid line and the GOA unit are respectively arranged in different first non-opening areas, and the problems can be well overcome. Of course, in the specific implementation, as an alternative, the gate line may be further disposed in the first non-opening region of the partial structure where the GOA circuit is disposed, and such a technical solution may also achieve the basic object of the present invention, and should also fall into the protection scope of the present invention.
Under the condition that the gate lines and the GOA units are respectively arranged in different first non-opening areas according to the above manner, each GOA unit can be further used for outputting two scanning pulses, and two gate lines are arranged in each two adjacent first non-opening areas, and each gate line is connected with a row of sub-pixel units P close to the gate line; a group of shift register units are arranged in the other first non-opening area; each group of shift register units is used for outputting two scanning pulses. Therefore, the scanning requirements of the sub-pixel units P of all the rows can be met, and compared with the situation that one GOA unit is arranged to output a plurality of scanning pulses, the area of each GOA unit is smaller, the width of the first non-opening area can be reduced, and the display brightness at the corresponding position is prevented from being obviously darker.
In practical implementation, the gate driving circuit generally includes a plurality of thin film transistors, and similarly, the sub-pixel unit array generally includes a plurality of thin film transistors. In a specific manufacturing process, each thin film transistor included in the gate driving circuit and the plurality of thin film transistors included in the sub-pixel unit array can be formed through the same process, so that the manufacturing difficulty can be reduced. In addition, the structures of the thin film transistors may be different in implementation. For the case when the Gate of the thin film transistor is located on the side of the active layer away from the substrate, the embodiment of the present invention further provides an alternative arrangement, referring to fig. 3a (fig. 3a is a schematic structural diagram of the thin film transistor located in the GOA unit) and fig. 3b (fig. 3b is a schematic structural diagram of the thin film transistor in the sub-pixel array), a light shielding pattern LS is disposed on the side of the active layer PL away from the Gate; the light-shielding pattern LS is formed on the same layer as the driving signal line CLK to shield a channel region of the thin film transistor. The advantage of this arrangement is that the active layer can be prevented from being affected by light from the side (lower side in the figure) far away from the gate, and in addition, the manufacturing difficulty and layout difficulty are reduced due to the same layer formation with the driving signal line CLK.
Further, the light shielding patterns LS may be electrically connected to the driving signal lines CLK, so that the resistance of the signals transmitted on the driving signal lines CLK can be reduced; and/or, further, the shading pattern can be reused as a touch electrode pattern. Therefore, the independent manufacture of corresponding touch electrode patterns can be avoided, and the thickness and the manufacture difficulty of the display device are reduced.
In a specific implementation, the electrical connection may refer to that the light shielding pattern LS (the light shielding pattern is a conductive pattern) is directly connected to the driving signal line CLK, or may refer to that the light shielding pattern LS is indirectly connected to the driving signal line CLK through another conductive structure. The light shielding patterns can be reused as touch electrode patterns, that is, the light shielding patterns LS can be designed so that the light shielding patterns LS can be used as the touch electrode patterns, for example, the light shielding patterns can be made into a plurality of block-shaped electrodes distributed in an array, and each electrode can be used as the touch electrode pattern to realize a touch detection function.
In a specific implementation, any one of the light-shielding patterns may be made of Ti/Al or the like.
In a specific implementation, in addition to the above-described structure, the array substrate in the ADS mode may further include other structures such as a base GL, a plurality of interlayer dielectric layers ILD1, ILD2 and ILD3, an active layer PL, a source/drain electrode pattern SD, and a common electrode (not shown in the figure), which are not described herein one by one. In addition, in a specific implementation, the connection lines and the driving signal line CLK may be connected to each portion of the gate driving circuit GOA through vias. The connecting lines and the driving signal lines CLK and GOA can be designed in various ways by those skilled in the art according to the disclosure, and the invention will not be described in detail herein.
It should be understood that, in the specific implementation, various optional setting manners described herein may be combined arbitrarily, and the implementation of the present invention is not affected by the corresponding technical solutions.
Another aspect of the present invention also provides a method for manufacturing an array substrate, which can be used to manufacture the array substrate described above, and the method can include:
the pixel driving circuit comprises a sub-pixel unit array, a grid line, a data line, a grid driving circuit and a driving signal line, wherein the sub-pixel unit array is formed on a substrate; wherein,
the gate driving circuits are dispersedly arranged in the plurality of first non-opening regions, and the dispersedly arranged parts are electrically connected with each other through connecting lines extending along the direction of the data lines;
the first non-opening area is an area between two adjacent rows of sub-pixel units.
It will be appreciated that, in particular, those skilled in the art may conceive of different embodiments of the above-mentioned fabrication method to fabricate any of the above-mentioned array substrates. A process of fabricating the array substrate shown in fig. 2 and 3 will be described as an example. Referring to fig. 4, the method includes:
step S1, forming a mask pattern LS and a driving signal line CLK on a substrate GL by a patterning process; the shielding pattern LS is positioned to cover a portion of a channel region in an active layer that is subsequently formed on a substrate.
Step S2, forming a first interlayer dielectric ILD1 above the blocking pattern LS; the interlayer dielectric layer ILD herein mainly plays a role of insulation, and separates the blocking pattern LS from the active layer PL.
Step S3, fabricating an active layer PL through a patterning process;
in step S4, a second interlayer dielectric ILD2 is fabricated.
In step S5, a Gate layer Gate is formed by a patterning process.
In step S6, a third interlayer dielectric ILD3 is fabricated.
In step S7, the source drain electrode layer SD is manufactured by a patterning process.
To this end, the structure shown in fig. 3a and 3b can be obtained.
In step S8, a resin layer is produced.
In step S9, a pixel electrode is fabricated through a patterning process.
Step S10, a passivation layer is fabricated.
In step S11, a common electrode layer is formed by a patterning process.
The structures formed in steps S8-S11 are not shown in fig. 3a and 3 b.
How the above steps are carried out is described in detail with reference to the prior art, and the present invention is not described in detail herein.
In a third aspect, the present invention further provides a display device, including the array substrate described in any one of the above.
In a specific implementation, the display device herein may be: any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. An array substrate, comprising: the pixel driving circuit comprises a substrate, a sub-pixel unit array, a grid line, a data line, a GOA gate driving circuit and a driving signal line, wherein the sub-pixel unit array is formed on the substrate, the grid line is used for providing scanning pulses for the sub-pixel unit array, the data line is used for providing data voltages for the sub-pixel unit array, the GOA gate driving circuit is used for providing the scanning pulses for the grid line, and the driving signal line is used for driving the GOA gate driving circuit; wherein,
the GOA gate driving circuits are dispersedly arranged in the plurality of first non-opening areas, and the dispersedly arranged parts are electrically connected with each other through connecting lines extending along the direction of the data lines;
the first non-opening area is an area between two adjacent rows of sub-pixel units;
the gate lines connected with the sub-pixel units in the row on the first side in the two rows of sub-pixel units on the two sides of the first non-opening area where the GOA gate driving circuit is located are located in the first non-opening area on the first side of the row of sub-pixel units, and the gate lines connected with the sub-pixel units in the row on the second side are located in the first non-opening area on the second side of the row of sub-pixel units.
2. The array substrate of claim 1, wherein each driving signal line and/or connecting line is disposed in the second non-opening region; the second non-opening area is an area between two adjacent columns of sub-pixel units.
3. The array substrate of claim 1, wherein the gate driving circuit comprises a plurality of groups of shift register units, the groups of shift register units are dispersedly disposed in a plurality of first non-opening areas, and each group of shift register units is disposed in only one same first non-opening area; each group of shift register units is used for outputting at least one scanning pulse in one frame.
4. The array substrate of claim 3, wherein each group of shift register units is connected to the N gate lines nearest to the group of shift register units through the connecting lines; wherein, N is the number of the scanning pulses output by a group of shift register units in one frame.
5. The array substrate of claim 1,
in every two adjacent first non-opening areas, two grid lines are arranged in one first non-opening area, and each grid line is connected with a row of sub-pixel units close to the grid line; a group of shift register units are arranged in the other first non-opening area; each group of shift register units is used for outputting two scanning pulses in one frame.
6. The array substrate of claim 1, wherein the gate driving circuit and the array of sub-pixel units comprise a plurality of thin film transistors; the grid electrodes of the thin film transistors are positioned on one side of the active layer, which is far away from the substrate; the array substrate further comprises a light shielding pattern which is arranged on one side of the active layer, which is far away from the grid electrode, and is used for shielding a channel region of the thin film transistor;
the driving signal line and the light-shielding pattern are formed in the same layer.
7. The array substrate of claim 6, wherein the light-shielding pattern is electrically connected to the driving signal line.
8. The array substrate of claim 6, wherein the light-shielding pattern is suitable for multiplexing as a touch electrode.
9. A method for manufacturing an array substrate comprises the following steps: the pixel driving circuit comprises a sub-pixel unit array, a grid line, a data line, a GOA grid driving circuit and a driving signal line, wherein the sub-pixel unit array is formed on a substrate, the grid line is used for providing scanning pulses for the sub-pixel unit array, the data line is used for providing data voltages for the sub-pixel unit array, the GOA grid driving circuit is used for providing the scanning pulses for the grid line, and the driving signal line is used for driving the GOA grid driving circuit; wherein,
the GOA gate driving circuits are dispersedly arranged in the plurality of first non-opening areas, and the dispersedly arranged parts are electrically connected with each other through connecting lines extending along the direction of the data lines;
the first non-opening area is an area between two adjacent rows of sub-pixel units;
the gate lines connected with the sub-pixel units in the row on the first side in the two rows of sub-pixel units on the two sides of the first non-opening area where the GOA gate driving circuit is located are located in the first non-opening area on the first side of the row of sub-pixel units, and the gate lines connected with the sub-pixel units in the row on the second side are located in the first non-opening area on the second side of the row of sub-pixel units.
10. A display device comprising the array substrate according to any one of claims 1 to 8.
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| CN107993613B (en) * | 2018-01-30 | 2020-07-03 | 武汉华星光电半导体显示技术有限公司 | AMOLED display panel |
| US10796643B2 (en) | 2018-01-30 | 2020-10-06 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | AMOLED display panel with transmitting goa circuit disposed below effective display region |
| CN110288959A (en) * | 2019-06-27 | 2019-09-27 | 北海惠科光电技术有限公司 | The driving circuit and its driving method of a kind of display panel, display panel |
| CN110599898A (en) * | 2019-08-20 | 2019-12-20 | 深圳市华星光电技术有限公司 | Grid driving array type display panel |
| CN111261094A (en) * | 2020-03-31 | 2020-06-09 | 深圳市华星光电半导体显示技术有限公司 | Grid driving array type display panel |
| CN111429829A (en) * | 2020-04-13 | 2020-07-17 | 深圳市华星光电半导体显示技术有限公司 | Display panel |
| CN111429828A (en) | 2020-04-13 | 2020-07-17 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
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| US4368467A (en) * | 1980-02-29 | 1983-01-11 | Fujitsu Limited | Display device |
| CN101978406A (en) * | 2008-04-14 | 2011-02-16 | 日东电工株式会社 | Optical display device manufacturing system and method for manufacturing optical display device |
| CN104599657A (en) * | 2015-03-04 | 2015-05-06 | 京东方科技集团股份有限公司 | Drive circuit and drive method for double-gate pixel structure, display panel and display device |
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