CN106098674B - The resistance test structure and method of the tungsten sinking layer of RFLDMOS - Google Patents
The resistance test structure and method of the tungsten sinking layer of RFLDMOS Download PDFInfo
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- CN106098674B CN106098674B CN201610671709.3A CN201610671709A CN106098674B CN 106098674 B CN106098674 B CN 106098674B CN 201610671709 A CN201610671709 A CN 201610671709A CN 106098674 B CN106098674 B CN 106098674B
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Abstract
The invention discloses a kind of resistance test structure of the tungsten sinking layer of RFLDMOS, test structure one and two, test structure one includes two tungsten sinking layers being arranged side by side and is all connected to test pads by first layer metal layer.Test structure two includes two tungsten sinking layers being arranged side by side, but only there are one being connected to test pads by first layer metal layer, the first layer metal layer of two tungsten sinking layers it is separated so as to be not connected to.Test structure one and two all respectively includes two and connects into Kelvin's test structure.4th tungsten sinking layer makes the tungsten sinking layer in test structure two be dense arrangement, improves the accuracy of the resistance test of test structure two.The invention also discloses a kind of method for testing resistance of the tungsten sinking layer of RFLDMOS.The present invention can provide the accuracy of the resistance test of tungsten sinking layer, improve WAT successfully tested rates.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing field, more particularly to a kind of radio frequency horizontal proliferation field effect transistor
Manage the resistance test structure of the tungsten sinking layer of (RFLDMOS)；The invention further relates to a kind of resistance surveys of the tungsten sinking layer of RFLDMOS
Method for testing.
Background technology
As shown in Figure 1, it is the structure diagram of existing RFLDMOS；For the powerful existing RFLDMOS packets of base station etc.
It includes：
The substrate of heavy doping such as silicon substrate 1, is formed with the epitaxial layer 2 being lightly doped on the substrate 1.
Channel region 3 and drift region 4, the channel region 3 and the drift region are formed in 2 surface region of epitaxial layer
4 laterally contact or do not contact, and channel region 3 described in Fig. 1 and the drift region 4 do not contact laterally.
Gate dielectric layer such as gate oxide and polysilicon gate 8 are sequentially formed on the surface of the channel region 3, by the polycrystalline
The surface of the channel region 3 of 8 surface of Si-gate covering is used to form raceway groove.
Source region 5 be formed in the surface of the channel region 3 and with the first side autoregistration of the polysilicon gate 8,6 shape of drain region
Spacing is mutually separated in drift region 4 described in Cheng Yu and with the second side of the polysilicon gate 8.
Raceway groove draw-out area 7 is formed in 3 surface of channel region.
The Faraday shield dielectric layer and farad being sequentially overlapped are formed in the side of the polysilicon gate 8 and top surface
Shielding metal leve 9；The Faraday shield dielectric layer and the Faraday shield metal layer 9 also extend into the polysilicon gate
The surface in 8 outsides.
Metal silicide 10 is all formed on the surface of the source region 5, the drain region 6 and the polysilicon gate 8.
The source region 5 is connected to the source electrode formed by front metal layer 102 by contact hole 12, and the drain region 6 is by connecing
Contact hole 12 is connected to the drain electrode formed by front metal layer 102；The polysilicon gate 8 is connected to by contact hole 12 by positive gold
Belong to the grid that layer 102 is formed.Contact hole 12 passes through interlayer film 11.Front metal layer 102 in Fig. 1 is first layer metal layer, one
As a complete device need multilayer front metal layer that could draw corresponding electrode, pass through layer between each layer front metal layer
Between film 11 be isolated and pass through contact hole 12 and be connected.
The tungsten sinking layer (Wsink) 101 of the RFLDMOS is passed through across raceway groove draw-out area 7, channel region 3 and is lightly doped
Epitaxial layer 2 is simultaneously connected with the substrate 1 of heavy doping；The top of the tungsten sinking layer 101 of the RFLDMOS is connected to the source electrode.
By taking N-type RFLDMOS as an example, substrate 1 is p-type heavy doping, and epitaxial layer 2 is lightly doped for N-type, and source region 5 and drain region 6 are all
N-type heavy doping, channel region 3 are lightly doped for p-type, and drift region 4 is lightly doped for N-type, and raceway groove draw-out area 7 is p-type heavy doping.
As seen from Figure 1, there are one longer drift regions 4 to obtain required breakdown voltage, Faraday shield for drain terminal
Ring is made of the Faraday shield dielectric layer and Faraday shield metal layer 9 for adding superposition in drain terminal.Channel region 3 is by autoregistration polycrystalline
The p-type ion implanting at the source edge of Si-gate 8 simultaneously passes through long-time high temperature and promotes to be formed.Tungsten sinking layer 101 passes through ultra-deep groove
It etches and inserts void-free tungsten metal and formed, is connected on the substrate 1 of p-type heavy doping, it is ensured that the source region 5 of device and channel region 3
There is good back metal to draw, the source region 5 realized relative to the diffusion technique in traditional structure and the connection of channel region 3, tungsten
Sinking layer 101 can substantially reduce the resistance and internal thermal resistance of device.
As shown in Fig. 2, it is the domain of the tungsten sinking layer of existing RFLDMOS；The tungsten sinking layer 101 of RFLDMOS can be into array
Arrangement architecture, as seen from Figure 1, tungsten sinking layer 101 are all strip structure, and 101 all length sides of tungsten sinking layer are put down in every a line
Row, width edge alignment.The length sides alignment of tungsten sinking layer 101 in each row.Due to each tungsten sinking layer 101 have it is neighbouring
Tungsten sinking layer 101, there is no isolated tungsten sinking layer 101, therefore the tungsten sinking layer 101 of existing RFLDMOS is all close packed structure.
It needs to test the resistance of tungsten sinking layer 101 in the prior art, test cannot be by existing RFLDMOS's
Tungsten sinking layer 101 directly test and is obtained, but needs to design test structure, and test structure is tested to obtain.It is existing
The Wsink resistance test structures for having RFLDMOS include two structures, respectively test structure one and test structure two.
As shown in figure 3, be the tungsten sinking layer of existing RFLDMOS resistance test structure in test structure one domain；
Test structure one includes two tungsten sinking layers, in order to be marked respectively with 101a and 101b with showing to distinguish.Tungsten sinking layer 101a and
101b is arranged side by side, and is all connected to first layer metal layer 102 at the top of tungsten sinking layer 101a and 101b, passes through first layer metal layer
102 are eventually connected in test pads (Pad) 103, and electrode is added in test pads 103 during test.In domain shown in Fig. 3
Show epitaxial layer 2 and raceway groove draw-out area 7.
As shown in figure 4, be the tungsten sinking layer of existing RFLDMOS resistance test structure in test structure two domain；
Test structure one only includes a tungsten sinking layer, in order to mark the tungsten sinking layer with 101e respectively to show to distinguish.Tungsten sinking layer
101e is isolated structures.First layer metal layer 102 is all connected at the top of tungsten sinking layer 101e, passes through first layer metal layer 102
It is eventually connected in test pads 103, electrode is added in test pads 103 during test.It is also shown in domain shown in Fig. 4 outer
Prolong layer 2 and raceway groove draw-out area 7.
It is found that two test structures one form Kelvin (Kelvin) test structure, two tests shown in Fig. 3 and Fig. 4
Structure two also forms Kelvin's test structure.The Kai Er of the composition of test structure one can be respectively obtained by Kelvin's test method
The resistance of literary test structure be Rs_Wsink+Rs_parasitic, test structure two form Kelvin's test structure resistance
For 2Rs_Wsink+Rs_parasitic；Wherein Rs_Wsink represents the parallel connection electricity of two tungsten sinking layers 101a and 101b in Fig. 3
The resistance of twice namely one tungsten sinking layer of resistance, 2Rs_Wsink represent twice of the resistance of tungsten sinking layer 101a in Fig. 4, if
All, therefore the parallel resistance of two tungsten sinking layers 101a and 101b are the size of timing tungsten sinking layer 101a and 101b and 101e
The half of the resistance of tungsten sinking layer 101a.Rs_parasitic represents the dead resistance of substrate, one group of test structure shown in Fig. 3
Into Kelvin's test structure in, the dead resistance of substrate is included in the width range being located between two tungsten sinking layer 101b
The sum of the dead resistance of the substrate of twice of width range is spaced between the dead resistance of substrate and tungsten sinking layer 101a and 101b.
In Fig. 4, Rs_parasitic represents the dead resistance of the substrate in the width range being located between two tungsten sinking layer 101e,
During design by pair with dead resistance relative to width match the Rs_parasitic in Fig. 3 and Fig. 4 can be made equal, this
The Kelvin that the resistance of sample into the Kelvin's test structure for being about to the composition of test structure two subtracts the composition of test structure one tests knot
The resistance of structure is with regard to that can obtain the resistance i.e. Rs_Wsink of the tungsten sinking layer of existing RFLDMOS.
Chip permits Acceptance Tests (Wafer Accept Test, WAT) to find, is tied using existing Fig. 3 and test shown in Fig. 4
When structure carries out the resistance test of tungsten sinking layer, the resistance of test structure two often will appear larger deviation as that can reach 100 individually
More than Europe, finally so that WAT test crash.
Invention content
The technical problems to be solved by the invention are to provide a kind of resistance test structure of the tungsten sinking layer of RFLDMOS, energy
The accuracy of the resistance test of tungsten sinking layer is provided, improves WAT successfully tested rates.For this purpose, the present invention also provides a kind of RFLDMOS
Tungsten sinking layer method for testing resistance.
In order to solve the above technical problems, the resistance test structure of the tungsten sinking layer of RFLDMOS provided by the invention includes：
Test structure one, the test structure one include the first tungsten sinking layer and the second tungsten sinking layer, and first tungsten sinks
Layer is identical with the size of the second tungsten sinking layer and all in bar shaped, and the first tungsten sinking layer and the second tungsten sinking layer are in
Length sides are parallel, the structure that is arranged side by side of width edge alignment；The top of the first tungsten sinking layer and the second tungsten sinking layer
All it is in contact with first layer metal layer, the first layer metal layer at the top of the first tungsten sinking layer and the second tungsten sinking layer
It is connected together and to the first test pads.
Test structure two, the test structure two include third tungsten sinking layer and the 4th tungsten sinking layer, and the third tungsten sinks
Layer is all identical with the size of the first tungsten sinking layer with the size of the 4th tungsten sinking layer；The third tungsten sinking layer and institute
The 4th tungsten sinking layer is stated in length sides are parallel, the structure that is arranged side by side of width edge alignment；The third tungsten sinking layer and described
The top of four tungsten sinking layers is all in contact with first layer metal layer, and the first layer metal layer at the top of the third tungsten sinking layer connects
It is connected to the second test pads；The top of the 4th tungsten sinking layer and the contact of first layer metal layer, the 4th tungsten sinking layer
The first layer metal layer at the top of the first layer metal layer at top and the third tungsten sinking layer it is separated so as to be not connected to.
Two test structures one form first Kelvin's test structure, two tests on the substrate of heavy doping
The second tungsten sinking interlayer of structure one is separated with the substrate of the first width and the length of two the second tungsten sinking layers
Side is parallel and width edge is aligned, the first tungsten sinking layer and the second sinking layer in the same test structure one it
Between between be separated with the substrate of the second width.
Two test structures two form first Kelvin's test structure, two tests on the substrate of heavy doping
The 4th tungsten sinking interlayer of structure two is every the interval less than the third tungsten sinking layer, the institute of two test structures two
The length sides that the substrate of third width and two third tungsten sinking layers are separated between stating between third tungsten sinking layer are parallel
And width edge is aligned, the third width is equal to 2 times of second width plus first width.
The resistance of the first Kelvin test structure for the first tungsten sinking layer and the second tungsten sinking layer and
Join 2 times of resistance plus the dead resistance of first width and the substrates of second width and.
The resistance of the second Kelvin test structure is for twice of resistance of the third tungsten sinking layer plus described the
The dead resistance of the substrate of three width, the resistance of the tungsten sinking layer of RFLDMOS are the resistance of the second Kelvin test structure
With the resistance difference of the first Kelvin test structure.
The 4th tungsten sinking layer makes the tungsten sinking layer in the test structure two be dense arrangement, improves described first and opens
The accuracy of your literary test structure.
A further improvement is that the tungsten sinking layer of the RFLDMOS is passed through across raceway groove draw-out area, channel region and is lightly doped
Epitaxial layer and connected with the substrate of heavy doping, the first tungsten sinking layer, the second tungsten sinking layer, the third tungsten sinking
The doped region that layer and the 4th tungsten sinking layer are passed through and the doped region phase that the tungsten sinking layer of the RFLDMOS is passed through
Together.
A further improvement is that the tungsten sinking layer of the RFLDMOS is dense arrangement.
A further improvement is that RFLDMOS includes：
It is formed with the epitaxial layer being lightly doped over the substrate.
Channel region and drift region are formed in the epi-layer surface region, the channel region and the drift region are lateral
Contact or not.
Gate dielectric layer and polysilicon gate are sequentially formed on the surface of the channel region, is covered by the polycrystalline silicon gate surface
The surface of the channel region be used to form raceway groove.
Source region be formed in the surface of the channel region and with the first side autoregistration of the polysilicon gate, drain region is formed in
Spacing is mutually separated in the drift region and with the second side of the polysilicon gate.
Raceway groove draw-out area is formed in the channel region surface.
The Faraday shield dielectric layer and farad being sequentially overlapped are formed in the side of the polysilicon gate and top surface
Shielding metal leve；The Faraday shield dielectric layer and the Faraday shield metal layer are also extended into outside the polysilicon gate
The surface of side.
The source region is connected to the source electrode formed by front metal layer by contact hole, and the drain region is connected by contact hole
To the drain electrode formed by front metal layer；The polysilicon gate is connected to the grid formed by front metal layer by contact hole.
The tungsten sinking layer of the RFLDMOS is across across raceway groove draw-out area, channel region and the epitaxial layer being lightly doped and and again
The substrate connection of doping；The source electrode is connected at the top of the tungsten sinking layer of the RFLDMOS.
In order to solve the above technical problems, the method for testing resistance of the tungsten sinking layer of RFLDMOS provided by the invention is included such as
Lower step：
Step 1: design test structure one and test structure two.
Test structure one, the test structure one include the first tungsten sinking layer and the second tungsten sinking layer, and first tungsten sinks
Layer is identical with the size of the second tungsten sinking layer and all in bar shaped, and the first tungsten sinking layer and the second tungsten sinking layer are in
Length sides are parallel, the structure that is arranged side by side of width edge alignment；The top of the first tungsten sinking layer and the second tungsten sinking layer
All it is in contact with first layer metal layer, the first layer metal layer at the top of the first tungsten sinking layer and the second tungsten sinking layer
It is connected together and to the first test pads.
Test structure two, the test structure two include third tungsten sinking layer and the 4th tungsten sinking layer, and the third tungsten sinks
Layer is all identical with the size of the first tungsten sinking layer with the size of the 4th tungsten sinking layer；The third tungsten sinking layer and institute
The 4th tungsten sinking layer is stated in length sides are parallel, the structure that is arranged side by side of width edge alignment；The third tungsten sinking layer and described
The top of four tungsten sinking layers is all in contact with first layer metal layer, and the first layer metal layer at the top of the third tungsten sinking layer connects
It is connected to the second test pads；The top of the 4th tungsten sinking layer and the contact of first layer metal layer, the 4th tungsten sinking layer
The first layer metal layer at the top of the first layer metal layer at top and the third tungsten sinking layer it is separated so as to be not connected to.
Two test structures one form first Kelvin's test structure, two tests on the substrate of heavy doping
The second tungsten sinking interlayer of structure one is separated with the substrate of the first width and the length of two the second tungsten sinking layers
Side is parallel and width edge is aligned, the first tungsten sinking layer and the second sinking layer in the same test structure one it
Between between be separated with the substrate of the second width.
Two test structures two form first Kelvin's test structure, two tests on the substrate of heavy doping
The 4th tungsten sinking interlayer of structure two is every the interval less than the third tungsten sinking layer, the institute of two test structures two
The length sides that the substrate of third width and two third tungsten sinking layers are separated between stating between third tungsten sinking layer are parallel
And width edge is aligned, the third width is equal to 2 times of second width plus first width.
Step 2: the resistance of the first Kelvin test structure is tested using Kelvin resistance test method,
The resistance of the first Kelvin test structure is the 2 of the parallel resistance of the first tungsten sinking layer and the second tungsten sinking layer
Times plus first width and second width substrate dead resistance and.
Step 3: the resistance of the second Kelvin test structure is tested using Kelvin resistance test method,
The resistance of the second Kelvin test structure is twice of the resistance of the third tungsten sinking layer plus the third width
The dead resistance of substrate；The 4th tungsten sinking layer makes the tungsten sinking layer in the test structure two be dense arrangement, improves institute
State the accuracy of first Kelvin's test structure.
Step 4: the resistance of the second Kelvin test structure is subtracted to the resistance of the first Kelvin test structure
Obtain the resistance of the tungsten sinking layer of RFLDMOS.
A further improvement is that the tungsten sinking layer of the RFLDMOS is passed through across raceway groove draw-out area, channel region and is lightly doped
Epitaxial layer and connected with the substrate of heavy doping, the first tungsten sinking layer, the second tungsten sinking layer, the third tungsten sinking
The doped region that layer and the 4th tungsten sinking layer are passed through and the doped region phase that the tungsten sinking layer of the RFLDMOS is passed through
Together.
A further improvement is that the tungsten sinking layer of the RFLDMOS is dense arrangement.
A further improvement is that RFLDMOS includes：
It is formed with the epitaxial layer being lightly doped over the substrate.
Channel region and drift region are formed in the epi-layer surface region, the channel region and the drift region are lateral
Contact or not.
Gate dielectric layer and polysilicon gate are sequentially formed on the surface of the channel region, is covered by the polycrystalline silicon gate surface
The surface of the channel region be used to form raceway groove.
Source region be formed in the surface of the channel region and with the first side autoregistration of the polysilicon gate, drain region is formed in
Spacing is mutually separated in the drift region and with the second side of the polysilicon gate.
Raceway groove draw-out area is formed in the channel region surface.
The Faraday shield dielectric layer and farad being sequentially overlapped are formed in the side of the polysilicon gate and top surface
Shielding metal leve；The Faraday shield dielectric layer and the Faraday shield metal layer are also extended into outside the polysilicon gate
The surface of side.
The source region is connected to the source electrode formed by front metal layer by contact hole, and the drain region is connected by contact hole
To the drain electrode formed by front metal layer；The polysilicon gate is connected to the grid formed by front metal layer by contact hole.
The tungsten sinking layer of the RFLDMOS is across across raceway groove draw-out area, channel region and the epitaxial layer being lightly doped and and again
The substrate connection of doping；The source electrode is connected at the top of the tungsten sinking layer of the RFLDMOS.
Relative to the prior art, the present invention improves test structure two, and test structure two is sunk in original tungsten
A tungsten sinking layer, respectively third tungsten sinking layer and the 4th tungsten sinking layer are increased on the basis of layer, under the 4th tungsten layer by layer
Although top is also connected with first layer metal layer, the first layer metal layer and third tungsten at the top of the 4th tungsten sinking layer sink
Layer top first layer metal layer it is separated so as to be not connected to, in this way, to test structure two carry out resistance test when only
The resistance to third tungsten sinking layer can be tested, the resistance of the 4th tungsten sinking layer will not include into the resistance of entire test structure two
Come, the 4th tungsten sinking layer will not bring the resistance test of test structure two adverse effect, the resistance test of test structure two according to
It is so that single tungsten sinking layer is tested.
On the contrary, the present invention, which passes through, sets the 4th tungsten sinking layer so that third tungsten sinking layer is no longer isolated, but by third and
Four tungsten sinking layers form dense arrangement together, in the dense arrangement and RFLDMOS device areas in this and test structure one
The dense arrangement of tungsten sinking layer is similar, so as to make test when eliminating in existing test structure two using isolated tungsten sinking layer
There is the situation of relatively large deviation in the test structure of the resistance of structure two, so as to improve the accurate of the resistance test of test structure two
Property, it can finally improve WAT successfully tested rates.
Description of the drawings
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments：
Fig. 1 is the structure diagram of existing RFLDMOS；
Fig. 2 is the domain of the tungsten sinking layer of existing RFLDMOS；
Fig. 3 is the domain of the test structure one in the resistance test structure of the tungsten sinking layer of existing RFLDMOS；
Fig. 4 is the domain of the test structure two in the resistance test structure of the tungsten sinking layer of existing RFLDMOS；
Fig. 5 is the domain of the test structure two in the resistance test structure of the tungsten sinking layer of RFLDMOS of the embodiment of the present invention.
Specific embodiment
The resistance test structure of the tungsten sinking layer of RFLDMOS of the embodiment of the present invention is still for RFLDMOS shown in FIG. 1
The resistance of tungsten sinking layer tested.As shown in Figure 1, RFLDMOS includes：
The substrate of heavy doping such as silicon substrate 1, is formed with the epitaxial layer 2 being lightly doped on the substrate 1.
Channel region 3 and drift region 4, the channel region 3 and the drift region are formed in 2 surface region of epitaxial layer
4 laterally contact or do not contact, and channel region 3 described in Fig. 1 and the drift region 4 do not contact laterally.
Gate dielectric layer such as gate oxide and polysilicon gate 8 are sequentially formed on the surface of the channel region 3, by the polycrystalline
The surface of the channel region 3 of 8 surface of Si-gate covering is used to form raceway groove.
Source region 5 be formed in the surface of the channel region 3 and with the first side autoregistration of the polysilicon gate 8,6 shape of drain region
Spacing is mutually separated in drift region 4 described in Cheng Yu and with the second side of the polysilicon gate 8.
Raceway groove draw-out area 7 is formed in 3 surface of channel region.
The Faraday shield dielectric layer and farad being sequentially overlapped are formed in the side of the polysilicon gate 8 and top surface
Shielding metal leve 9；The Faraday shield dielectric layer and the Faraday shield metal layer 9 also extend into the polysilicon gate
The surface in 8 outsides.
Metal silicide 10 is all formed on the surface of the source region 5, the drain region 6 and the polysilicon gate 8.
The source region 5 is connected to the source electrode formed by front metal layer 102 by contact hole 12, and the drain region 6 is by connecing
Contact hole 12 is connected to the drain electrode formed by front metal layer 102；The polysilicon gate 8 is connected to by contact hole 12 by positive gold
Belong to the grid that layer 102 is formed.Contact hole 12 passes through interlayer film 11.Front metal layer 102 in Fig. 1 is first layer metal layer, one
As a complete device need multilayer front metal layer that could draw corresponding electrode, pass through layer between each layer front metal layer
Between film 11 be isolated and pass through contact hole 12 and be connected.
The tungsten sinking layer (Wsink) 101 of the RFLDMOS is passed through across raceway groove draw-out area 7, channel region 3 and is lightly doped
Epitaxial layer 2 is simultaneously connected with the substrate 1 of heavy doping；The top of the tungsten sinking layer 101 of the RFLDMOS is connected to the source electrode.
By taking N-type RFLDMOS as an example, substrate 1 is p-type heavy doping, and epitaxial layer 2 is lightly doped for N-type, and source region 5 and drain region 6 are all
N-type heavy doping, channel region 3 are lightly doped for p-type, and drift region 4 is lightly doped for N-type, and raceway groove draw-out area 7 is p-type heavy doping.
As seen from Figure 1, there are one longer drift regions 4 to obtain required breakdown voltage, Faraday shield for drain terminal
Ring is made of the Faraday shield dielectric layer and Faraday shield metal layer 9 for adding superposition in drain terminal.Channel region 3 is by autoregistration polycrystalline
The p-type ion implanting at the source edge of Si-gate 8 simultaneously passes through long-time high temperature and promotes to be formed.Tungsten sinking layer 101 passes through ultra-deep groove
It etches and inserts void-free tungsten metal and formed, is connected on the substrate 1 of p-type heavy doping, it is ensured that the source region 5 of device and channel region 3
There is good back metal to draw, the source region 5 realized relative to the diffusion technique in traditional structure and the connection of channel region 3, tungsten
Sinking layer 101 can substantially reduce the resistance and internal thermal resistance of device.
As shown in Fig. 2, it is the domain of the tungsten sinking layer of RFLDMOS；The tungsten sinking layer 101 of RFLDMOS can be arranged into an array
Structure, as seen from Figure 1, tungsten sinking layer 101 are all strip structure, and all length sides of tungsten sinking layer 101 are parallel, wide in every a line
Spend side alignment.The length sides alignment of tungsten sinking layer 101 in each row.Since each tungsten sinking layer 101 has neighbouring tungsten
Sinking layer 101, there is no isolated tungsten sinking layer 101, therefore the tungsten sinking layer 101 of existing RFLDMOS is all close packed structure.
The resistance test structure of the tungsten sinking layer of RFLDMOS of the embodiment of the present invention includes：Test structure one and test structure
Two.
The test structure one of the embodiment of the present invention and the prior art it is identical, as shown in figure 3, test structure one, the test
Structure one includes the first tungsten sinking layer 101a and the second tungsten sinking layer 101b, the first tungsten sinking layer 101a and second tungsten
The size of sinking layer 101b is identical and all in bar shaped, and the first tungsten sinking layer 101a and the second tungsten sinking layer 101b are in length
Degree side is parallel, the structure that is arranged side by side of width edge alignment；The first tungsten sinking layer 101a and the second tungsten sinking layer 101b
Top be all in contact with first layer metal layer 102, the first tungsten sinking layer 101a and the second tungsten sinking layer 101b's
The first layer metal layer 102 at top is connected together and to the first test pads 103.
As shown in figure 5, test structure two, which includes third tungsten sinking layer 101c and the 4th tungsten sinking layer
The size of 101d, the third tungsten sinking layer 101c and the 4th tungsten sinking layer 101d all with the first tungsten sinking layer 101a
Size it is identical；The third tungsten sinking layer 101c and the 4th tungsten sinking layer 101d are in length sides are parallel, width edge alignment
The structure that is arranged side by side；The top of the third tungsten sinking layer 101c and the 4th tungsten sinking layer 101d are all and first layer metal
Layer 102 is in contact, and the first layer metal layer 102 at the top of the third tungsten sinking layer 101c is connected to the second test pads 103；
The top of the 4th tungsten sinking layer 101d and first layer metal layer 102 contact, the top of the 4th tungsten sinking layer 101d
The first layer metal layer 102 at the top of first layer metal layer 102 and the third tungsten sinking layer 101c it is separated so as to not connecting
It connects.Note：The first layer metal layer 102 in test structure one and two is collectively labeled as 102 in Fig. 3 and Fig. 5, the first test pads and
Second test pads are collectively labeled as 103.
Two test structures one form first Kelvin's test structure, two surveys on the substrate 1 of heavy doping
The substrate 1 and two the second tungsten sinking layers of the first width are separated between the second tungsten sinking layer 101b of examination structure one
The length sides of 101b are parallel and width edge is aligned, the first tungsten sinking layer 101a and institute in the same test structure one
The substrate 1 of the second width is separated between stating between the second sinking layer；
Two test structures two form first Kelvin's test structure, two surveys on the substrate 1 of heavy doping
The 4th tungsten sinking layer 101d intervals for trying structure two are less than the interval of the third tungsten sinking layer 101c, two tests
The substrate 1 of third width is separated between the third tungsten sinking layer 101c of structure two and two third tungsten sink
The length sides of layer 101c are parallel and width edge is aligned, and the third width is equal to 2 times of second width plus described first
Width.
The resistance of the first Kelvin test structure is the first tungsten sinking layer 101a and the second tungsten sinking layer
2 times of the parallel resistance of 101b are plus the dead resistance and i.e. Rs_ of first width and the substrate 1 of second width
Wsink+Rs_parasitic, formula with it is of the prior art be as, Rs_parasitic at this is the 2 of the second width
Again plus the dead resistance of the substrate 1 of the first width.
The resistance of the second Kelvin test structure adds institute for twice of the resistance of the third tungsten sinking layer 101c
State the dead resistance i.e. 2Rs_Wsink+Rs_parasitic of the substrate 1 of third width, formula with it is of the prior art be as；
Rs_parasitic at this is that the dead resistance of the substrate 1 of third width and 2 times of the second width add the first width
The substrate 1 dead resistance it is identical.
Resistance and first Kelvin of the resistance of the tungsten sinking layer of RFLDMOS for the second Kelvin test structure
Resistance difference, that is, Rs_Wsink of test structure.
It is unfavorable that 4th tungsten sinking layer 101d described in the embodiment of the present invention will not generate the resistance of the test structure two
It influences, if formula is still for 2Rs_Wsink+Rs_parasitic, when test only lets it pass the electricity of the third tungsten sinking layer 101c
It hinders namely in testing, the 4th tungsten sinking layer 101d is equivalent to a false tungsten sinking layer (dummy Wsink).It is and described
It is dense arrangement that can make the tungsten sinking layer in the test structure two after 4th tungsten sinking layer 101d increases, improves the test knot
The accuracy of the resistance test of structure two.
The tungsten sinking layer of the RFLDMOS pass through across raceway groove draw-out area 7, channel region 3 and the epitaxial layer 2 that is lightly doped and and
The substrate 1 of heavy doping connects, the first tungsten sinking layer 101a, the second tungsten sinking layer 101b, the third tungsten sinking layer
The doped region that 101c and the 4th tungsten sinking layer 101d are passed through and the doping that the tungsten sinking layer of the RFLDMOS is passed through
Region is identical.
The method for testing resistance of the tungsten sinking layer of RFLDMOS of the embodiment of the present invention includes the following steps：
Step 1: design test structure one and test structure two.
Test structure one, the test structure one include the first tungsten sinking layer 101a and the second tungsten sinking layer 101b, and described the
One tungsten sinking layer 101a is identical with the size of the second tungsten sinking layer 101b and in bar shaped, the first tungsten sinking layer 101a
With the second tungsten sinking layer 101b in length sides are parallel, the structure that is arranged side by side of width edge alignment；The first tungsten sinking layer
The top of 101a and the second tungsten sinking layer 101b are all in contact with first layer metal layer 102, the first tungsten sinking layer
The first layer metal layer 102 at the top of 101a and the second tungsten sinking layer 101b is connected together and to the first test lining
Pad 103.
Test structure two, the test structure two include third tungsten sinking layer 101c and the 4th tungsten sinking layer 101d, and described the
The size of three tungsten sinking layer 101c and the 4th tungsten sinking layer 101d is all identical with the size of the first tungsten sinking layer 101a；
The third tungsten sinking layer 101c and the 4th tungsten sinking layer 101d are in length sides are parallel, the knot that is arranged side by side of width edge alignment
Structure；The top of the third tungsten sinking layer 101c and the 4th tungsten sinking layer 101d are all in contact with first layer metal layer 102,
The first layer metal layer 102 at the top of the third tungsten sinking layer 101c is connected to the second test pads 103；Under 4th tungsten
The top of heavy layer 101d and first layer metal layer 102 contact, the first layer metal layer at the top of the 4th tungsten sinking layer 101d
The first layer metal layer 102 at the top of the 102 and third tungsten sinking layer 101c it is separated so as to be not connected to.
Two test structures one form first Kelvin's test structure, two surveys on the substrate 1 of heavy doping
The substrate 1 and two the second tungsten sinking layers of the first width are separated between the second tungsten sinking layer 101b of examination structure one
The length sides of 101b are parallel and width edge is aligned, the first tungsten sinking layer 101a and institute in the same test structure one
The substrate 1 of the second width is separated between stating between the second sinking layer.
Two test structures two form first Kelvin's test structure, two surveys on the substrate 1 of heavy doping
The 4th tungsten sinking layer 101d intervals for trying structure two are less than the interval of the third tungsten sinking layer 101c, two tests
The substrate 1 of third width is separated between the third tungsten sinking layer 101c of structure two and two third tungsten sink
The length sides of layer 101c are parallel and width edge is aligned, and the third width is equal to 2 times of second width plus described first
Width.
Step 2: the resistance of the first Kelvin test structure is tested using Kelvin resistance test method,
The resistance of the first Kelvin test structure for the first tungsten sinking layer 101a and the second tungsten sinking layer 101b's and
Join 2 times of resistance plus the dead resistance of first width and the substrates 1 of second width and.
Step 3: the resistance of the second Kelvin test structure is tested using Kelvin resistance test method,
The resistance of the second Kelvin test structure is twice of the resistance of the third tungsten sinking layer 101c wide plus the third
The dead resistance of the substrate 1 of degree；The 4th tungsten sinking layer 101d makes the tungsten sinking layer in the test structure two be intensive row
Row improve the accuracy of the first Kelvin test structure.
Step 4: the resistance of the second Kelvin test structure is subtracted to the resistance of the first Kelvin test structure
Obtain the resistance of the tungsten sinking layer of RFLDMOS.
The present invention has been described in detail through specific embodiments, but these not form the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these also should
It is considered as protection scope of the present invention.
Claims (6)
1. a kind of resistance test structure of the tungsten sinking layer of RFLDMOS, which is characterized in that including：
Test structure one, the test structure one include the first tungsten sinking layer and the second tungsten sinking layer, the first tungsten sinking layer and
The size of the second tungsten sinking layer is identical and all in bar shaped, and the first tungsten sinking layer and the second tungsten sinking layer are in length
Side is parallel, the structure that is arranged side by side of width edge alignment；The top of the first tungsten sinking layer and the second tungsten sinking layer all and
First layer metal layer is in contact, and the first tungsten sinking layer is connected with the first layer metal layer at the top of the second tungsten sinking layer
Together and it is connected to the first test pads；
Test structure two, the test structure two include third tungsten sinking layer and the 4th tungsten sinking layer, the third tungsten sinking layer and
The size of the 4th tungsten sinking layer is all identical with the size of the first tungsten sinking layer；The third tungsten sinking layer and described
Four tungsten sinking layers are in length sides are parallel, the structure that is arranged side by side of width edge alignment；The third tungsten sinking layer and the 4th tungsten
The top of sinking layer is all in contact with first layer metal layer, and the first layer metal layer at the top of the third tungsten sinking layer is connected to
Second test pads；The top of the 4th tungsten sinking layer and the contact of first layer metal layer, the top of the 4th tungsten sinking layer
First layer metal layer and the third tungsten sinking layer top first layer metal layer it is separated so as to be not connected to；
Two test structures one form first Kelvin's test structure, two test structures on the substrate of heavy doping
The length sides of the substrate and two the second tungsten sinking layers that one the second tungsten sinking interlayer is separated with the first width are put down
It goes and width edge is aligned, between the first tungsten sinking layer and the second tungsten sinking layer in the same test structure one
Between be separated with the substrate of the second width；
Two test structures two form second Kelvin's test structure, two test structures on the substrate of heavy doping
Two the 4th tungsten sinking interlayer is every the interval less than the third tungsten sinking layer, and described the of two test structures two
The length sides that the substrate of third width and two third tungsten sinking layers are separated between three tungsten sinking layers are parallel and wide
Side alignment is spent, the third width is equal to 2 times of second width plus first width；
The resistance of the first Kelvin test structure is the first tungsten sinking layer and the parallel connection electricity of the second tungsten sinking layer
2 times of resistance plus the substrate of first width and second width dead resistance and；
The resistance of the second Kelvin test structure is the twice wide plus the third of the resistance of the third tungsten sinking layer
The dead resistance of the substrate of degree, the resistance and institute of the resistance of the tungsten sinking layer of RFLDMOS for the second Kelvin test structure
State the resistance difference of first Kelvin's test structure.
2. the resistance test structure of the tungsten sinking layer of RFLDMOS as described in claim 1, it is characterised in that：The RFLDMOS
Tungsten sinking layer pass through and connect across raceway groove draw-out area, channel region and the epitaxial layer being lightly doped and with the substrate of heavy doping, it is described
The doping that first tungsten sinking layer, the second tungsten sinking layer, the third tungsten sinking layer and the 4th tungsten sinking layer are passed through
The doped region that the tungsten sinking layer of region and the RFLDMOS are passed through is identical.
3. the resistance test structure of the tungsten sinking layer of RFLDMOS as described in claim 1, which is characterized in that RFLDMOS packets
It includes：
It is formed with the epitaxial layer being lightly doped over the substrate；
Channel region and drift region are formed in the epi-layer surface region, the channel region and the drift region laterally contact
Or it does not contact；
Gate dielectric layer and polysilicon gate are sequentially formed on the surface of the channel region, the institute covered by the polycrystalline silicon gate surface
The surface for stating channel region is used to form raceway groove；
Source region be formed in the surface of the channel region and with the first side autoregistration of the polysilicon gate, drain region is formed in described
Spacing is mutually separated in drift region and with the second side of the polysilicon gate；
Raceway groove draw-out area is formed in the channel region surface；
The Faraday shield dielectric layer and faraday screen being sequentially overlapped are formed in the side of the polysilicon gate and top surface
Cover metal layer；The Faraday shield dielectric layer and the Faraday shield metal layer are also extended on the outside of the polysilicon gate
Surface；
The source region is connected to the source electrode formed by front metal layer by contact hole, the drain region by contact hole be connected to by
The drain electrode that front metal layer is formed；The polysilicon gate is connected to the grid formed by front metal layer by contact hole；
The tungsten sinking layer of the RFLDMOS is passed through across raceway groove draw-out area, channel region and the epitaxial layer being lightly doped and and heavy doping
Substrate connection；The source electrode is connected at the top of the tungsten sinking layer of the RFLDMOS.
4. the method for testing resistance of the tungsten sinking layer of a kind of RFLDMOS, which is characterized in that include the following steps：
Step 1: design test structure one and test structure two；
Test structure one, the test structure one include the first tungsten sinking layer and the second tungsten sinking layer, the first tungsten sinking layer and
The size of the second tungsten sinking layer is identical and all in bar shaped, and the first tungsten sinking layer and the second tungsten sinking layer are in length
Side is parallel, the structure that is arranged side by side of width edge alignment；The top of the first tungsten sinking layer and the second tungsten sinking layer all and
First layer metal layer is in contact, and the first tungsten sinking layer is connected with the first layer metal layer at the top of the second tungsten sinking layer
Together and it is connected to the first test pads；
Test structure two, the test structure two include third tungsten sinking layer and the 4th tungsten sinking layer, the third tungsten sinking layer and
The size of the 4th tungsten sinking layer is all identical with the size of the first tungsten sinking layer；The third tungsten sinking layer and described
Four tungsten sinking layers are in length sides are parallel, the structure that is arranged side by side of width edge alignment；The third tungsten sinking layer and the 4th tungsten
The top of sinking layer is all in contact with first layer metal layer, and the first layer metal layer at the top of the third tungsten sinking layer is connected to
Second test pads；The top of the 4th tungsten sinking layer and the contact of first layer metal layer, the top of the 4th tungsten sinking layer
First layer metal layer and the third tungsten sinking layer top first layer metal layer it is separated so as to be not connected to；
Two test structures one form first Kelvin's test structure, two test structures on the substrate of heavy doping
The length sides of the substrate and two the second tungsten sinking layers that one the second tungsten sinking interlayer is separated with the first width are put down
It goes and width edge is aligned, between the first tungsten sinking layer and the second tungsten sinking layer in the same test structure one
Between be separated with the substrate of the second width；
Two test structures two form second Kelvin's test structure, two test structures on the substrate of heavy doping
Two the 4th tungsten sinking interlayer is every the interval less than the third tungsten sinking layer, and described the of two test structures two
The length sides that the substrate of third width and two third tungsten sinking layers are separated between three tungsten sinking layers are parallel and wide
Side alignment is spent, the third width is equal to 2 times of second width plus first width；
Step 2: the resistance of the first Kelvin test structure is tested using Kelvin resistance test method, it is described
The resistance of first Kelvin's test structure for the parallel resistance of the first tungsten sinking layer and the second tungsten sinking layer 2 extraordinarily
The dead resistance of the substrate of upper first width and second width and；
Step 3: the resistance of the second Kelvin test structure is tested using Kelvin resistance test method, it is described
Twice substrate that adds the third width of the resistance of second Kelvin's test structure for the resistance of the third tungsten sinking layer
Dead resistance；Step 4: the resistance of the second Kelvin test structure is subtracted into the first Kelvin test structure
Resistance obtains the resistance of the tungsten sinking layer of RFLDMOS.
5. the method for testing resistance of the tungsten sinking layer of RFLDMOS as claimed in claim 4, it is characterised in that：The RFLDMOS
Tungsten sinking layer pass through and connect across raceway groove draw-out area, channel region and the epitaxial layer being lightly doped and with the substrate of heavy doping, it is described
The doping that first tungsten sinking layer, the second tungsten sinking layer, the third tungsten sinking layer and the 4th tungsten sinking layer are passed through
The doped region that the tungsten sinking layer of region and the RFLDMOS are passed through is identical.
6. the method for testing resistance of the tungsten sinking layer of RFLDMOS as claimed in claim 4, which is characterized in that RFLDMOS packets
It includes：
It is formed with the epitaxial layer being lightly doped over the substrate；
Channel region and drift region are formed in the epi-layer surface region, the channel region and the drift region laterally contact
Or it does not contact；
Gate dielectric layer and polysilicon gate are sequentially formed on the surface of the channel region, the institute covered by the polycrystalline silicon gate surface
The surface for stating channel region is used to form raceway groove；
Source region be formed in the surface of the channel region and with the first side autoregistration of the polysilicon gate, drain region is formed in described
Spacing is mutually separated in drift region and with the second side of the polysilicon gate；
Raceway groove draw-out area is formed in the channel region surface；
The Faraday shield dielectric layer and faraday screen being sequentially overlapped are formed in the side of the polysilicon gate and top surface
Cover metal layer；The Faraday shield dielectric layer and the Faraday shield metal layer are also extended on the outside of the polysilicon gate
Surface；
The source region is connected to the source electrode formed by front metal layer by contact hole, the drain region by contact hole be connected to by
The drain electrode that front metal layer is formed；The polysilicon gate is connected to the grid formed by front metal layer by contact hole；
The tungsten sinking layer of the RFLDMOS is passed through across raceway groove draw-out area, channel region and the epitaxial layer being lightly doped and and heavy doping
Substrate connection；The source electrode is connected at the top of the tungsten sinking layer of the RFLDMOS.
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| CN102364682A (en) * | 2011-10-28 | 2012-02-29 | 上海宏力半导体制造有限公司 | Perpendicular double-diffusion MOS (Metal Oxide Semiconductor) test structure as well as forming and testing methods |
| CN103367330A (en) * | 2013-07-31 | 2013-10-23 | 上海宏力半导体制造有限公司 | Testing structure of power semiconductor device and manufacture method of testing structure |
| CN104465614A (en) * | 2013-09-18 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | Test structure and corresponding test method |
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| CN102364682A (en) * | 2011-10-28 | 2012-02-29 | 上海宏力半导体制造有限公司 | Perpendicular double-diffusion MOS (Metal Oxide Semiconductor) test structure as well as forming and testing methods |
| CN103367330A (en) * | 2013-07-31 | 2013-10-23 | 上海宏力半导体制造有限公司 | Testing structure of power semiconductor device and manufacture method of testing structure |
| CN104465614A (en) * | 2013-09-18 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | Test structure and corresponding test method |
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