CN106098630A - A kind of fan-out-type wafer-level packaging method and packaging part - Google Patents
A kind of fan-out-type wafer-level packaging method and packaging part Download PDFInfo
- Publication number
- CN106098630A CN106098630A CN201610648702.XA CN201610648702A CN106098630A CN 106098630 A CN106098630 A CN 106098630A CN 201610648702 A CN201610648702 A CN 201610648702A CN 106098630 A CN106098630 A CN 106098630A
- Authority
- CN
- China
- Prior art keywords
- bare chip
- fan
- level packaging
- type wafer
- wiring layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Abstract
The present invention provides a kind of fan-out-type wafer-level packaging method and packaging part, and this method for packing provides a carrier；Groove is offered in described carrier front；The bare chip with contact pad is provided, described bare chip face down is put in described groove；The molding compound covering described bare chip is formed at the bare chip back side；Grind the back side of described carrier, make the front of described bare chip expose；Form wiring layer again, make described in again wiring layer electrically connect with the contact pad of described bare chip；Metal coupling is installed, makes described metal coupling be electrically connected with the contact pad of described bare chip by described wiring layer again.The present invention utilizes the screens effect of groove to fix bare chip, it is to avoid or decrease the displacement of bare chip in encapsulation process, and make packaging part can have narrower device bonding pad gap and higher input and output number；And product yield and yield can be improved, reduce again live width and the line-spacing of wiring layer, reduce package dimension, reduce cost.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation, particularly relate to a kind of fan-out-type wafer-level packaging method and encapsulation
Part.
Background technology
Owing to the terminal units such as smart mobile phone are increasingly faster to the development of compactization, it is specifically designed in miniaturization, thin
The importance of the Wafer level packaging of membranization and cost degradation improves constantly.Fan-out-type wafer-level packaging (FOWLP:Fan-
Out WLP) technology is best suitable for the movement/wireless market of high request at present, and other paid close attention to high-performance and undersized city
, it may have the strongest captivation.Use this technology, can also seal even if the more chip of number of terminals does not reduce spacing
Dress, even if chip shrinks without change package dimension.Therefore, FOWLP can realize the standardization of package dimension, the most permissible
Realize multiple chip, can be the hybrid package of different cultivars chip so that it is in terms of functional realiey, attracted more concern.
In Embedded wafer-level packaging manufacturing process, during wafer sealing moulding, the displacement of bare chip (Die) is one
Relatively common problem.The shift value scope of bare chip is generally in 20～100 μm, and this can cause the dislocation of lithography alignment, resistance
Rc degradation, inner connecting structure lost efficacy, and limited the bonding pads separation of device.
Therefore, how to provide a kind of fan-out-type Wafer level packaging, to reduce the displacement of bare chip in encapsulation process,
Become the important technological problems that those skilled in the art are urgently to be resolved hurrily.
Summary of the invention
Prior art in view of the above, it is an object of the invention to provide a kind of fan-out-type wafer-level packaging method and envelope
Piece installing, bare chip displacement problem during for solving FOWLP encapsulated moulding in prior art.
For achieving the above object and other relevant purposes, the present invention provides a kind of fan-out-type wafer-level packaging method, including
Following steps:
One carrier is provided；
Groove is offered in described carrier front；
The bare chip with contact pad is provided, described bare chip face down is put in described groove；
The molding compound covering described bare chip is formed at the bare chip back side；
Grind the back side of described carrier, make the front of described bare chip expose；
Form wiring layer again, make described in again wiring layer electrically connect with the contact pad of described bare chip；
Metal coupling is installed, makes described metal coupling be electrically connected by the contact pad of described wiring layer again with described bare chip
Connect.
Alternatively, one or more in silicon, silicon oxide, metal, glass or pottery of the material of described carrier.
Alternatively, described carrier is plate.
Alternatively, the method offering groove is laser drill, machine drilling or deep reaction ion etching.
Alternatively, the width of described groove is consistent with the width of described bare chip or length, makes described bare chip just block
Hold and fix in the trench.
Alternatively, the degree of depth of described groove is more than the thickness of described bare chip.
Alternatively, described gash depth is 50～200 μm.
Alternatively, when described bare chip face down being put in described groove, described bare chip is completely embedded into described ditch
In groove.
Alternatively, when described bare chip face down being put in described groove, it is formed with guarantor in described bare chip front
Sheath；Grind the back side of described carrier, expose the described protective layer covering described bare chip front, then remove described protective layer
Expose the front of described bare chip.
Still optionally further, described protective layer is pasty state or glue, or is solid film, or for ultraviolet release adhesive tape or
Heat release adhesive tape.
Still optionally further, the method forming described protective layer is spin coating, printing, chemical gaseous phase deposition or lamination.
Still optionally further, the thickness of described protective layer is 5～10 μm.
Still optionally further, the method removing described protective layer is laser ablation, stripping, dry or wet etch, chemistry
Agent dissolving, ultraviolet release or heat release.
Alternatively, described molding compound is filled in the trench.
Alternatively, the material forming described molding compound is epoxylite, liquid type thermosetting epoxy resin or moulds
Material mold compound.
Alternatively, the method forming described molding compound is compression forming, transfer modling, fluid-tight molding, vacuum lamination
Or spin coating.
Alternatively, the method grinding the described carrier back side includes the one in mechanical lapping, chemical polishing, etching or many
Kind.
Alternatively, described wiring layer again includes metal connecting line and is located at the dielectric layer around described metal connecting line, described
Metal connecting line is electrically connected with the contact pad of described bare chip by through hole, and electrically connects with described metal coupling.
Still optionally further, when forming wiring layer, described dielectric layer covers the front of described bare chip and fills up described again
Groove.
Still optionally further, the material of described dielectric layer is SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2, polyimides
(Polyimide, PI), polybenzoxazole (Polybenzoxazole, PBO), benzocyclobutene (Benzocyclobutene,
BCB) one or more in.
Still optionally further, forming the method for described dielectric layer is that physical vapour deposition (PVD), chemical gaseous phase deposit, print, revolve
It is coated with, sprays, sinters or thermal oxide.
Still optionally further, the material of described metal connecting line include the one in Cu, Al, Ag, Au, Sn, Ni, Ti, Ta or
Multiple.
Still optionally further, the method forming described metal connecting line includes the one in electrolysis plating, chemical plating, silk screen printing
Or it is multiple.
Alternatively, described wiring layer again covers described bare chip and extends at described carrier backside surface.
Alternatively, forming Underbump metallization layer on described wiring layer again, described Underbump metallization layer passes through described cloth again
Line layer electrically connects with the contact pad of described bare chip, and described metal coupling is arranged on described Underbump metallization layer.
Alternatively, described metal coupling is solder ball, copper ball or gun-metal ball；The forming method of described metal coupling is
Electroplate or plant ball.
For achieving the above object and other relevant purposes, the present invention also provides for a kind of fan-out-type wafer-level packaging part, including:
Bare chip, described bare chip has contact pad；
Carrier, described carrier is provided with groove, and described bare chip clamping is in the trench；
Molding compound, covers the back side of described bare chip and fills in the trench；
Wiring layer again, is positioned on the front of described bare chip, electrically connects with the contact pad of described bare chip；
Metal coupling, be positioned at described in again on wiring layer, by the contact pad electricity of described wiring layer again with described bare chip
Connect.
Alternatively, one or more during the material of described carrier is silicon, silicon oxide, metal, glass or pottery.
Alternatively, described carrier is plate.
Alternatively, the material of described molding compound is cure package material.
Alternatively, the material of described molding compound is that epoxylite, liquid type thermosetting epoxy resin or plastics become
Type compound.
Alternatively, described wiring layer again includes metal connecting line and is located at the dielectric layer around described metal connecting line, described
Metal connecting line is electrically connected with the contact pad of described bare chip by through hole, and electrically connects with described metal coupling.
Still optionally further, described dielectric layer covers the front of described bare chip and fills up described groove.
Still optionally further, the material of described dielectric layer is SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2, polyimides
(Polyimide, PI), polybenzoxazole (Polybenzoxazole, PBO), benzocyclobutene (Benzocyclobutene,
BCB) one or more in.
Still optionally further, the material of described metal connecting line include the one in Cu, Al, Ag, Au, Sn, Ni, Ti, Ta or
Multiple.
Alternatively, described wiring layer again covers described bare chip and extends at described carrier surface.
Alternatively, described fan-out package part also includes Underbump metallization layer, described Underbump metallization layer by described again
Wiring layer electrically connects with the contact pad of described bare chip, and described metal coupling is arranged on described Underbump metallization layer.
Alternatively, described metal coupling is solder ball, copper ball or gun-metal ball.
As it has been described above, the fan-out-type wafer-level packaging method of the present invention and packaging part, have the advantages that
Bare chip, by offering groove on carrier, is embedded in groove by the fan-out-type wafer-level packaging method of the present invention,
Such that it is able to utilize the screens effect of groove to fix bare chip position on carrier, it is to avoid or decrease naked core in encapsulation process
The displacement of sheet.The displacement problem of bare chip during owing to solving encapsulated moulding, utilizes the packaging part of the inventive method to have
There are narrower device bonding pad spacing and higher input and output number (I/O counts)；And subsequent optical carving technology can be improved
Alignment efficiency, thus product yield and yield can be improved；Live width and the line-spacing (LW/LS) of wiring layer can be reduced again, further
Reduce package dimension, reduce cost.
Accompanying drawing explanation
Fig. 1 is shown as the schematic diagram of the fan-out-type wafer-level packaging method that the present invention provides.
Fig. 2 a-2h is shown as the process flow diagram of the fan-out-type wafer-level packaging method that the embodiment of the present invention provides,
Wherein Fig. 2 h is shown as the structural representation of the fan-out-type wafer-level packaging part that the embodiment of the present invention provides.
Fig. 3 is shown as in the embodiment of the present invention having offered the carrier Facad structure schematic diagram of groove.
Fig. 4 is shown as in the embodiment of the present invention embedding the carrier Facad structure schematic diagram of bare chip.
Element numbers explanation
101 carriers
201 bare chips
2011 contact pads
202 protective layers
301 molding compound
400 wiring layers again
401 dielectric layers
402 metal connecting lines
501 metal couplings
502 Underbump metallization
S1～S7 step
Detailed description of the invention
Below by way of specific instantiation, embodiments of the present invention being described, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also be by the most different concrete realities
The mode of executing is carried out or applies, the every details in this specification can also based on different viewpoints and application, without departing from
Various modification or change is carried out under the spirit of the present invention.It should be noted that, in the case of not conflicting, following example and enforcement
Feature in example can be mutually combined.
It should be noted that the diagram provided in following example illustrates the basic structure of the present invention the most in a schematic way
Think, the most graphic in component count, shape and size time only display with relevant assembly in the present invention rather than is implemented according to reality
Drawing, during its actual enforcement, the kenel of each assembly, quantity and ratio can be a kind of random change, and its assembly layout kenel is also
It is likely more complexity.
Referring to Fig. 1, the present invention provides a kind of fan-out-type wafer-level packaging method, comprises the following steps:
S1 provides a carrier；
S2 offers groove in described carrier front；
S3 provides the bare chip with contact pad, described bare chip face down is put in described groove；
S4 forms the molding compound covering described bare chip at the bare chip back side；
S5 grinds the back side of described carrier, exposes the front of described bare chip；
S6 forms wiring layer again, make described in again wiring layer electrically connect with the contact pad of described bare chip；
S7 installs metal coupling, makes described metal coupling by the contact pad electricity of described wiring layer again with described bare chip
Connect.
Bare chip, by offering groove on carrier, is embedded in groove, such that it is able to utilize groove by this method for packing
Bare chip position on carrier is fixed in screens effect, it is to avoid or decrease the displacement of bare chip in encapsulation process.
Technical scheme is described in detail below by concrete example.
Embodiment one
Referring to Fig. 2 a-2h, the present embodiment provides a kind of fan-out-type wafer-level packaging method.
First, it is provided that a carrier 101, as shown in Figure 2 a.The material of described carrier 101 can be selected from silicon, silicon oxide, gold
One or more in genus, glass or pottery, or other analog, preferably silicon.Described carrier 101 can be plate.This
Carrier 101 described in embodiment is for having certain thickness silica-based circular flat board.
As shown in Figure 2 b, groove is offered in described carrier 101 front.The method offering groove can be laser drill, machine
Tool boring, deep reaction ion etching or other grooving methods being suitable for.Offer the width of groove and the bare chip needing encapsulation
Width or length consistent, make bare chip can just clamping fixing in the trench, i.e. to limit bare chip wide at it for groove
Position on degree or length direction, makes bare chip can not shift the most in one direction.The degree of depth of described groove is more than institute
State the thickness of bare chip.Such as, described gash depth can be 50～200 μm.Offer the carrier Facad structure such as Fig. 3 after groove
Shown in, the quantity of groove can be one or more, and groove arrangement position on carrier 101 can be carried out according to actual needs
Design, the invention is not limited in this regard.
As shown in Figure 2 c, it is provided that there is the bare chip 201 of contact pad 2011, described bare chip 201 face down is put
Enter in described groove.Bare chip 201 i.e. needs the chip naked core (Die) of encapsulation, can be to have multiple semiconductor device and electricity
The IC chip on road or discrete-semiconductor device etc..When described bare chip 201 face down is put in described groove, described naked core
Sheet 201 is completely embedded in described groove, also has certain space after bare chip 201 embeds groove in groove.Embed bare chip 201
After carrier Facad structure as shown in Figure 4, the quantity of bare chip 201 can be one or more, and bare chip 201 is arranged in the trench
The position of cloth can be designed according to actual needs, the invention is not limited in this regard.
The present embodiment preferably, when described bare chip 201 face down is put in described groove, at described bare chip
201 fronts are formed with protective layer 202.Described protective layer 202 1 aspect can protect the front face surface of bare chip 201 to avoid embedding
Damaging during entering or pollute, on the other hand protective layer 201 can help bare chip 201 to stick to, in groove, avoid further
The displacement of bare chip 201.Described protective layer 202 can be pasty state or glue, or is solid film, or discharges adhesive tape for ultraviolet
Or heat release adhesive tape.Formed the method for described protective layer 202 can be spin coating, printing, chemical gaseous phase deposition, lamination or other fit
The method closed.The thinner thickness of described protective layer 202, such as, can be 5～10 μm.
Then, as shown in Figure 2 d, the molding compound 301 covering described bare chip 201 is formed at bare chip 201 back side,
By described bare chip 201 encapsulated moulding.Molding compound 301 described in the present embodiment is filled in the trench, covers described
The back side of bare chip 201 and side, make bare chip 201 be encapsulated in the groove of carrier 101.Preferably, molding compound 301 can
So that described groove is filled up.The material forming described molding compound 301 can be cure package material, such as, can be epoxy
Resinoid, liquid type thermosetting epoxy resin, plastic molding compound or the like.Form the side of described molding compound 301
Method can be compression forming, transfer modling, fluid-tight molding, vacuum lamination, spin coating or other methods being suitable for.
It follows that grind the back side of described carrier 101, the front of described bare chip 201 is made to expose.Described in the present embodiment
The front of bare chip 201 is provided with protective layer 202, and the protective layer covering described bare chip 201 can be exposed in the back side of grinding carrier 101
202, as shown in Figure 2 e.Therefore, it is also desirable to remove described protective layer 202 to expose the front of described bare chip 201, such as Fig. 2 f institute
Show.The method removing described protective layer 202 can be laser ablation, stripping, dry or wet etch, chemical agent dissolving, ultraviolet
Line release, heat release or other methods being suitable for.The method grinding described carrier 101 back side can include mechanical lapping, chemistry
The combination of one or more in polishing, etching, or the Ginding process being suitable for for other.
As shown in Figure 2 g, form again wiring layer (RDL) 400, make described in the connecing of wiring layer 400 and described bare chip 201 again
Touch pad 2011 to electrically connect, to realize the redistribution of chip bonding pad.In the present embodiment, described wiring layer again 400 covers described naked
Chip 201 also extends at described carrier 101 backside surface.Specifically, described wiring layer again 400 can include metal connecting line 402
And it is located at the dielectric layer 401 around described metal connecting line 402, described metal connecting line 402 is by through hole and described bare chip 201
Contact pad 2011 electrically connect, and electrically connect with the metal coupling of subsequent installation.In the present embodiment, it is preferable that formed again
During wiring layer 400, described dielectric layer 401 covers the front of described bare chip 201 and fills up described groove, such that it is able to fill institute
State the thickness disparity between bare chip 201 and carrier 101.
Wherein, described metal connecting line 402 can include that one layer or multilayer interconnection metal level, described dielectric layer 401 also may be used
To include one or more layers dielectric material.Preferably, when described metal connecting line 402 comprises multilayer interconnection metal level, given an account of
Electric material can be arranged between described multilayer interconnection metal level, thus can be separated by every layer of interconnecting metal layer.In described multilamellar
Electrical connection can be realized by the way of forming through hole between interconnecting metal layer.
Specifically, the material of described dielectric layer 401 can be SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2, polyamides sub-
Amine (Polyimide, PI), polybenzoxazole (Polybenzoxazole, PBO), benzocyclobutene (Benzocyclobutene,
BCB) one or more in, or other insulant being suitable for.The method forming described dielectric layer 401 can be physical vapor
Deposition, chemical gaseous phase deposition, printing, spin coating, spray, sinter, thermal oxide or other dielectric deposition process being suitable for.Described metal
The material of line 402 can include one or more in Cu, Al, Ag, Au, Sn, Ni, Ti, Ta, or other conductive gold being suitable for
Belong to material.Such as, metal connecting line 402 can be Cu line, and the Seed Layer making Cu line can be Ti/Cu layer.Form described metal
The method of line 402 can include one or more being electrolysed in plating, chemical plating, silk screen printing, or other metals being suitable for sink
Long-pending technique.
Finally, as shown in fig. 2h, metal coupling 501 is installed, makes described metal coupling 501 by described wiring layer 400 again
Electrically connect with the contact pad 2011 of described bare chip 201.Specifically, can be formed under projection on described wiring layer again 400
Metal level (UBM) 502, described Underbump metallization layer 502 is by the Contact welding of described wiring layer again 400 with described bare chip 201
Dish 2011 electrically connects, and described metal coupling 501 is arranged on described Underbump metallization layer 502.Specifically, described metal coupling
The material of 501 can be selected from one or more in Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, and such as, described metal coupling 501 can
Think solder ball, copper ball or gun-metal ball.The forming method of described metal coupling 501 can be plating or plant ball.
Embodiment two
Referring to Fig. 2 h, the present embodiment provides a kind of fan-out-type wafer-level packaging method using embodiment one to prepare
Packaging part.This packaging part, including: bare chip 201, described bare chip 201 has contact pad 2011；Carrier 101, described load
Body 101 is provided with groove, and described bare chip 201 clamping is in the trench；Molding compound 301, covers described bare chip 201
The back side and fill in the trench；Wiring layer 400 again, are positioned on the front of described bare chip 201, with described bare chip
The contact pad 2011 of 201 electrically connects；Metal coupling 501, be positioned at described in again on wiring layer 400, by described wiring layer 400 again
It is connected with the contact pad electricity 2011 of described bare chip 201.
Specifically, the material of described carrier 101 can be the one in silicon, silicon oxide, metal, glass or pottery or many
Kind, or other analog, the present embodiment is preferably silicon.Described carrier 101 can be plate.Such as circular flat board.Described naked core
Sheet 201 can be IC chip or the discrete-semiconductor device etc. with multiple semiconductor device and circuit.
Specifically, the material of described molding compound 301 can be cure package material, such as, can be epoxies tree
Fat, liquid type thermosetting epoxy resin, plastic molding compound or the like.
Specifically, described wiring layer again 400 can include metal connecting line 402 and be located at around described metal connecting line 402
Dielectric layer 401, described metal connecting line 402 is electrically connected with the contact pad 2011 of described bare chip 201 by through hole, and with institute
State metal coupling 501 to electrically connect.Wherein, described dielectric layer 401 covers the front of described bare chip 201 and fills up described groove,
Such that it is able to the thickness disparity filled between described bare chip 201 and carrier 101.As the preferred version of the present invention, described again
Wiring layer 400 covers described bare chip 201 and extends on described carrier 101 surface.
Preferably, described metal connecting line 402 can include one layer or multilayer interconnection metal level, and described dielectric layer 401 is also
One or more layers dielectric material can be included.Wherein, when described metal connecting line 402 comprises multilayer interconnection metal level, given an account of
Electric material can be arranged between described multilayer interconnection metal level, thus can be separated by every layer of interconnecting metal layer.In described multilamellar
Electrical connection can be realized by the way of forming through hole between interconnecting metal layer.
Specifically, the material of described dielectric layer 401 can be SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2, polyamides sub-
Amine (Polyimide, PI), polybenzoxazole (Polybenzoxazole, PBO), benzocyclobutene (Benzocyclobutene,
BCB) one or more in, or other insulant being suitable for.The material of described metal connecting line 402 can include Cu, Al,
One or more in Ag, Au, Sn, Ni, Ti, Ta, or other conductive metallic materials being suitable for.Such as, metal connecting line 402 is permissible
For Cu line, the Seed Layer making Cu line can be Ti/Cu layer.
Specifically, described fan-out package part can also include Underbump metallization layer 502, described Underbump metallization layer 502
Being electrically connected by the contact pad 2011 of described wiring layer again 400 with described bare chip 201, described metal coupling 501 is arranged on
On described Underbump metallization layer 502.
Specifically, the material of described metal coupling 501 can be the one in Al, Sn, Ni, Au, Ag, Pb, Bi, Cu or many
Kind, such as, described metal coupling 501 can be solder ball, copper ball or gun-metal ball.
In sum, the fan-out-type wafer-level packaging method of the present invention is by offering groove on carrier, and bare chip is embedding
Enter in groove, such that it is able to utilize the screens effect of groove to fix bare chip position on carrier, it is to avoid or decrease encapsulation
During the displacement of bare chip.The displacement problem of bare chip during owing to solving encapsulated moulding, packaging part of the present invention can have
There are narrower device bonding pad spacing and higher input and output number (I/O counts).Use the inventive method can improve follow-up
The alignment efficiency of photoetching process, thus product yield and yield can be improved, live width and the line-spacing (LW/ of wiring layer can be reduced again
LS), reduce package dimension further, reduce cost.So, the present invention effectively overcome various shortcoming of the prior art and
Tool high industrial utilization.
The principle of above-described embodiment only illustrative present invention and effect thereof, not for limiting the present invention.Any ripe
Above-described embodiment all can be modified under the spirit and the scope of the present invention or change by the personage knowing this technology.Cause
This, have usually intellectual such as complete with institute under technological thought without departing from disclosed spirit in art
All equivalences become are modified or change, and must be contained by the claim of the present invention.
Claims (38)
1. a fan-out-type wafer-level packaging method, it is characterised in that comprise the following steps:
One carrier is provided；
Groove is offered in described carrier front；
The bare chip with contact pad is provided, described bare chip face down is put in described groove；
The molding compound covering described bare chip is formed at the bare chip back side；
Grind the back side of described carrier, make the front of described bare chip expose；
Form wiring layer again, make described in again wiring layer electrically connect with the contact pad of described bare chip；
Metal coupling is installed, makes described metal coupling be electrically connected with the contact pad of described bare chip by described wiring layer again.
Fan-out-type wafer-level packaging method the most according to claim 1, it is characterised in that: the material of described carrier is selected from
One or more in silicon, silicon oxide, metal, glass or pottery.
Fan-out-type wafer-level packaging method the most according to claim 1, it is characterised in that: described carrier is plate.
Fan-out-type wafer-level packaging method the most according to claim 1, it is characterised in that: the method offering groove is laser
Boring, machine drilling or deep reaction ion etching.
Fan-out-type wafer-level packaging method the most according to claim 1, it is characterised in that: the width of described groove is with described
The width of bare chip or length are consistent, make the lucky clamping of described bare chip fixing in the trench.
Fan-out-type wafer-level packaging method the most according to claim 1, it is characterised in that: the degree of depth of described groove is more than institute
State the thickness of bare chip.
Fan-out-type wafer-level packaging method the most according to claim 1, it is characterised in that: described gash depth be 50～
200μm。
Fan-out-type wafer-level packaging method the most according to claim 1, it is characterised in that: by described bare chip face down
When putting in described groove, described bare chip is completely embedded in described groove.
Fan-out-type wafer-level packaging method the most according to claim 1, it is characterised in that: by described bare chip face down
When putting in described groove, it is formed with protective layer in described bare chip front；Grind the back side of described carrier, expose covering described
The described protective layer in bare chip front, then removes described protective layer and exposes the front of described bare chip.
Fan-out-type wafer-level packaging method the most according to claim 9, it is characterised in that: described protective layer be pasty state or
Glue, or be solid film, or discharge adhesive tape for ultraviolet release adhesive tape or heat.
11. fan-out-type wafer-level packaging methods according to claim 9, it is characterised in that: form the side of described protective layer
Method is spin coating, printing, chemical gaseous phase deposition or lamination.
12. fan-out-type wafer-level packaging methods according to claim 9, it is characterised in that: the thickness of described protective layer is 5
～10 μm.
13. fan-out-type wafer-level packaging methods according to claim 9, it is characterised in that: remove the side of described protective layer
Method is laser ablation, stripping, dry or wet etch, chemical agent dissolves, ultraviolet discharges or heat release.
14. fan-out-type wafer-level packaging methods according to claim 1, it is characterised in that: described molding compound is filled
In the trench.
15. fan-out-type wafer-level packaging methods according to claim 1, it is characterised in that: form described molding compound
Material be epoxylite, liquid type thermosetting epoxy resin or plastic molding compound.
16. fan-out-type wafer-level packaging methods according to claim 1, it is characterised in that: form described molding compound
Method be compression forming, transfer modling, fluid-tight molding, vacuum lamination or spin coating.
17. fan-out-type wafer-level packaging methods according to claim 1, it is characterised in that: grind the described carrier back side
Method includes one or more in mechanical lapping, chemical polishing, etching.
18. fan-out-type wafer-level packaging methods according to claim 1, it is characterised in that: described wiring layer again includes gold
Belonging to line and be located at the dielectric layer around described metal connecting line, described metal connecting line is contacted by through hole and described bare chip
Pad electrically connects, and electrically connects with described metal coupling.
19. fan-out-type wafer-level packaging methods according to claim 18, it is characterised in that: when forming again wiring layer, institute
Give an account of electric layer cover the front of described bare chip and fill up described groove.
20. fan-out-type wafer-level packaging methods according to claim 18, it is characterised in that: the material of described dielectric layer is
SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2, polyimides, polybenzoxazole, one or more in benzocyclobutene.
21. fan-out-type wafer-level packaging methods according to claim 18, it is characterised in that: form the side of described dielectric layer
Method is physical vapour deposition (PVD), chemical gaseous phase deposition, printing, spin coating, sprays, sinters or thermal oxide.
22. fan-out-type wafer-level packaging methods according to claim 18, it is characterised in that: the material of described metal connecting line
Including one or more in Cu, Al, Ag, Au, Sn, Ni, Ti, Ta.
23. fan-out-type wafer-level packaging methods according to claim 18, it is characterised in that: form described metal connecting line
Method includes one or more being electrolysed in plating, chemical plating, silk screen printing.
24. fan-out-type wafer-level packaging methods according to claim 1, it is characterised in that: described wiring layer again covers institute
State bare chip and extend at described carrier backside surface.
25. fan-out-type wafer-level packaging methods according to claim 1, it is characterised in that: shape on described wiring layer again
Becoming Underbump metallization layer, described Underbump metallization layer is electrically connected with the contact pad of described bare chip by described wiring layer again,
Described metal coupling is arranged on described Underbump metallization layer.
26. fan-out-type wafer-level packaging methods according to claim 1, it is characterised in that: described metal coupling is scolding tin
Ball, copper ball or gun-metal ball；The forming method of described metal coupling is for plating or plants ball.
27. 1 kinds of fan-out-type wafer-level packaging parts, it is characterised in that including:
Bare chip, described bare chip has contact pad；
Carrier, described carrier is provided with groove, and described bare chip clamping is in the trench；
Molding compound, covers the back side of described bare chip and fills in the trench；
Wiring layer again, is positioned on the front of described bare chip, electrically connects with the contact pad of described bare chip；
Metal coupling, be positioned at described in again on wiring layer, electrically connected with the contact pad of described bare chip by described wiring layer again.
28. fan-out-type wafer-level packaging parts according to claim 27, it is characterised in that: the material of described carrier be silicon,
One or more in silicon oxide, metal, glass or pottery.
29. fan-out-type wafer-level packaging parts according to claim 27, it is characterised in that: described carrier is plate.
30. fan-out-type wafer-level packaging parts according to claim 27, it is characterised in that: the material of described molding compound
For cure package material.
31. fan-out-type wafer-level packaging parts according to claim 27, it is characterised in that: the material of described molding compound
For epoxylite, liquid type thermosetting epoxy resin or plastic molding compound.
32. fan-out-type wafer-level packaging parts according to claim 27, it is characterised in that: described wiring layer again includes metal
Line and be located at the dielectric layer around described metal connecting line, described metal connecting line is by the Contact welding of through hole with described bare chip
Dish electrically connects, and electrically connects with described metal coupling.
33. fan-out-type wafer-level packaging parts according to claim 32, it is characterised in that: described dielectric layer covers described naked
Described groove is also filled up in the front of chip.
34. fan-out-type wafer-level packaging parts according to claim 32, it is characterised in that: the material of described dielectric layer is
SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2, polyimides, polybenzoxazole, one or more in benzocyclobutene.
35. fan-out-type wafer-level packaging parts according to claim 32, it is characterised in that: the material bag of described metal connecting line
Include one or more in Cu, Al, Ag, Au, Sn, Ni, Ti, Ta.
36. fan-out-type wafer-level packaging parts according to claim 27, it is characterised in that: described wiring layer again covers described
Bare chip also extends at described carrier backside surface.
37. fan-out-type wafer-level packaging parts according to claim 27, it is characterised in that: formed on described wiring layer again
Underbump metallization layer, described Underbump metallization layer is electrically connected with the contact pad of described bare chip by described wiring layer again, institute
State metal coupling to be arranged on described Underbump metallization layer.
38. fan-out-type wafer-level packaging parts according to claim 27, it is characterised in that: described metal coupling is scolding tin
Ball, copper ball or gun-metal ball.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610648702.XA CN106098630A (en) | 2016-08-09 | 2016-08-09 | A kind of fan-out-type wafer-level packaging method and packaging part |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610648702.XA CN106098630A (en) | 2016-08-09 | 2016-08-09 | A kind of fan-out-type wafer-level packaging method and packaging part |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106098630A true CN106098630A (en) | 2016-11-09 |
Family
ID=57455364
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610648702.XA Pending CN106098630A (en) | 2016-08-09 | 2016-08-09 | A kind of fan-out-type wafer-level packaging method and packaging part |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106098630A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107195555A (en) * | 2017-07-03 | 2017-09-22 | 京东方科技集团股份有限公司 | A kind of chip packaging method |
| WO2018165815A1 (en) * | 2017-03-13 | 2018-09-20 | 深圳修远电子科技有限公司 | Chip fanning out method |
| CN110021558A (en) * | 2017-12-21 | 2019-07-16 | 美光科技公司 | Method for handling semiconductor bare chip and making reconstituted wafer |
| CN110211888A (en) * | 2019-06-14 | 2019-09-06 | 上海先方半导体有限公司 | A kind of embedded fan-out packaging structure and its manufacturing method |
| CN110335852A (en) * | 2019-07-18 | 2019-10-15 | 上海先方半导体有限公司 | A kind of fan-out packaging structure and packaging method |
| CN111370323A (en) * | 2018-12-26 | 2020-07-03 | 中芯集成电路（宁波）有限公司 | Method for manufacturing semiconductor device |
| CN112786540A (en) * | 2019-11-06 | 2021-05-11 | 富泰华工业（深圳）有限公司 | Fan-out type packaging structure and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1524293A (en) * | 2000-10-19 | 2004-08-25 | ض� | Microelectronic substrate with integrated devices |
| US20060094240A1 (en) * | 2002-11-06 | 2006-05-04 | Stern Jonathan | Neo-wafer device comprised of multiple singulated integrated circuit die |
| US20110127654A1 (en) * | 2009-11-27 | 2011-06-02 | Advanced Semiconductor Engineering, Inc.., | Semiconductor Package and Manufacturing Methods Thereof |
| CN206040642U (en) * | 2016-08-09 | 2017-03-22 | 中芯长电半导体（江阴）有限公司 | Fan -out type wafer -level package spare |
-
2016
- 2016-08-09 CN CN201610648702.XA patent/CN106098630A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1524293A (en) * | 2000-10-19 | 2004-08-25 | ض� | Microelectronic substrate with integrated devices |
| US20060094240A1 (en) * | 2002-11-06 | 2006-05-04 | Stern Jonathan | Neo-wafer device comprised of multiple singulated integrated circuit die |
| US20110127654A1 (en) * | 2009-11-27 | 2011-06-02 | Advanced Semiconductor Engineering, Inc.., | Semiconductor Package and Manufacturing Methods Thereof |
| CN206040642U (en) * | 2016-08-09 | 2017-03-22 | 中芯长电半导体（江阴）有限公司 | Fan -out type wafer -level package spare |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018165815A1 (en) * | 2017-03-13 | 2018-09-20 | 深圳修远电子科技有限公司 | Chip fanning out method |
| CN107195555A (en) * | 2017-07-03 | 2017-09-22 | 京东方科技集团股份有限公司 | A kind of chip packaging method |
| CN110021558A (en) * | 2017-12-21 | 2019-07-16 | 美光科技公司 | Method for handling semiconductor bare chip and making reconstituted wafer |
| US10559495B2 (en) | 2017-12-21 | 2020-02-11 | Micron Technology, Inc. | Methods for processing semiconductor dice and fabricating assemblies incorporating same |
| CN110021558B (en) * | 2017-12-21 | 2022-04-05 | 美光科技公司 | Methods for processing semiconductor dies and fabricating reconstituted wafers |
| CN111370323A (en) * | 2018-12-26 | 2020-07-03 | 中芯集成电路（宁波）有限公司 | Method for manufacturing semiconductor device |
| CN110211888A (en) * | 2019-06-14 | 2019-09-06 | 上海先方半导体有限公司 | A kind of embedded fan-out packaging structure and its manufacturing method |
| CN110335852A (en) * | 2019-07-18 | 2019-10-15 | 上海先方半导体有限公司 | A kind of fan-out packaging structure and packaging method |
| CN112786540A (en) * | 2019-11-06 | 2021-05-11 | 富泰华工业（深圳）有限公司 | Fan-out type packaging structure and manufacturing method thereof |
| US11462481B2 (en) | 2019-11-06 | 2022-10-04 | Kore Semiconductor Co., Ltd. | Fan-out packaging structure and method of making same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106098630A (en) | A kind of fan-out-type wafer-level packaging method and packaging part | |
| CN206657808U (en) | Electronic installation | |
| CN106409760B (en) | The method of semiconductor devices and encapsulation semiconductor element | |
| US10553458B2 (en) | Chip packaging method | |
| CN106158824B (en) | Ic package and forming method thereof | |
| CN103681613B (en) | There is the semiconductor device of discrete area | |
| CN103515252B (en) | Form the semiconductor devices and method of embedded SOP fan-out packages | |
| CN105374693B (en) | Semiconductor package part and forming method thereof | |
| CN103943553B (en) | The method that there is the low profile of perpendicular interconnection unit to be fanned out to formula encapsulation for semiconductor devices and formation | |
| CN103515260B (en) | Encapsulation and forming method thereof in encapsulation | |
| CN102194740B (en) | Semiconductor device and method of forming the same | |
| CN102347251B (en) | Embedded wafer-level bonding approaches | |
| CN103187388B (en) | The semiconductor device of encapsulation and the method for encapsulated semiconductor device | |
| CN103325690B (en) | Semiconductor packages and forming method thereof | |
| CN106328619A (en) | 3D package structure and methods of forming same | |
| CN106684033A (en) | Methods of forming connector pad structures and interconnect structures, and the structures | |
| US9287203B2 (en) | Package-on-package structure and method of forming same | |
| CN106356340A (en) | Semiconductor device and method of manufacture | |
| CN103165477A (en) | Method for forming vertical interconnect structure and semiconductor device | |
| US8916422B2 (en) | Semiconductor packages and methods of packaging semiconductor devices | |
| CN102683279A (en) | Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation | |
| CN105679741A (en) | Semiconductor packages and methods of forming the same | |
| CN106206333A (en) | A kind of fan-out-type wafer-level packaging method | |
| CN110085557A (en) | Semiconductor devices and the method for forming embedded wafer-level chip scale package using standard carriers | |
| CN105938804A (en) | Wafer level chip scale packaging method and package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20161109 |